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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_T4240RDB
14
15#define CONFIG_FSL_SATA_V2
16#define CONFIG_PCIE4
17
18#define CONFIG_ICS307_REFCLK_HZ 25000000
19
20#ifdef CONFIG_RAMBOOT_PBL
21#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
22#ifndef CONFIG_SDCARD
23#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
24#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
25#else
26#define CONFIG_SPL_FLUSH_IMAGE
27#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
28#define CONFIG_FSL_LAW
29#define CONFIG_SYS_TEXT_BASE 0x00201000
30#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
31#define CONFIG_SPL_PAD_TO 0x40000
32#define CONFIG_SPL_MAX_SIZE 0x28000
33#define RESET_VECTOR_OFFSET 0x27FFC
34#define BOOT_PAGE_OFFSET 0x27000
35
36#ifdef CONFIG_SDCARD
37#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
38#define CONFIG_SPL_MMC_MINIMAL
39#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
40#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
41#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
42#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
43#ifndef CONFIG_SPL_BUILD
44#define CONFIG_SYS_MPC85XX_NO_RESETVEC
45#endif
46#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
47#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
48#define CONFIG_SPL_MMC_BOOT
49#endif
50
51#ifdef CONFIG_SPL_BUILD
52#define CONFIG_SPL_SKIP_RELOCATE
53#define CONFIG_SPL_COMMON_INIT_DDR
54#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
55#define CONFIG_SYS_NO_FLASH
56#endif
57
58#endif
59#endif
60
61#define CONFIG_DDR_ECC
62
63#define CONFIG_CMD_REGINFO
64
65
66#define CONFIG_BOOKE
67#define CONFIG_E500
68#define CONFIG_E500MC
69#define CONFIG_SYS_BOOK3E_HV
70#define CONFIG_MP
71
72#ifndef CONFIG_SYS_TEXT_BASE
73#define CONFIG_SYS_TEXT_BASE 0xeff40000
74#endif
75
76#ifndef CONFIG_RESET_VECTOR_ADDRESS
77#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
78#endif
79
80#define CONFIG_SYS_FSL_CPC
81#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
82#define CONFIG_FSL_IFC
83#define CONFIG_FSL_CAAM
84#define CONFIG_PCIE1
85#define CONFIG_PCIE2
86#define CONFIG_PCIE3
87#define CONFIG_FSL_PCI_INIT
88#define CONFIG_SYS_PCI_64BIT
89
90#define CONFIG_FSL_LAW
91
92#define CONFIG_ENV_OVERWRITE
93
94
95
96
97#define CONFIG_SYS_CACHE_STASHING
98#define CONFIG_BTB
99#ifdef CONFIG_DDR_ECC
100#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
101#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
102#endif
103
104#define CONFIG_ENABLE_36BIT_PHYS
105
106#define CONFIG_ADDR_MAP
107#define CONFIG_SYS_NUM_ADDR_MAP 64
108
109#define CONFIG_SYS_MEMTEST_START 0x00200000
110#define CONFIG_SYS_MEMTEST_END 0x00400000
111#define CONFIG_SYS_ALT_MEMTEST
112#define CONFIG_PANIC_HANG
113
114
115
116
117#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
118#define CONFIG_SYS_L3_SIZE (512 << 10)
119#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
120#ifdef CONFIG_RAMBOOT_PBL
121#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
122#endif
123#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
124#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
125#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
126#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
127
128#define CONFIG_SYS_DCSRBAR 0xf0000000
129#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
130
131
132
133
134#define CONFIG_VERY_BIG_RAM
135#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
136#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
137
138
139#define CONFIG_DIMM_SLOTS_PER_CTLR 1
140#define CONFIG_CHIP_SELECTS_PER_CTRL 4
141#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
142
143#define CONFIG_DDR_SPD
144#define CONFIG_SYS_FSL_DDR3
145
146
147
148
149#define CONFIG_SYS_FLASH_BASE 0xe0000000
150#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
151
152#ifdef CONFIG_SPL_BUILD
153#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
154#else
155#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
156#endif
157
158#define CONFIG_BOARD_EARLY_INIT_R
159#define CONFIG_MISC_INIT_R
160
161#define CONFIG_HWCONFIG
162
163
164#define CONFIG_L1_INIT_RAM
165#define CONFIG_SYS_INIT_RAM_LOCK
166#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
167#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
168#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
169
170#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
171 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
172 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
173#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
174
175#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
176 GENERATED_GBL_DATA_SIZE)
177#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
178
179#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
180#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
181
182
183
184
185
186#define CONFIG_CONS_INDEX 1
187#define CONFIG_SYS_NS16550_SERIAL
188#define CONFIG_SYS_NS16550_REG_SIZE 1
189#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
190
191#define CONFIG_SYS_BAUDRATE_TABLE \
192 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
193
194#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
195#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
196#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
197#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
198
199
200#define CONFIG_SYS_I2C
201#define CONFIG_SYS_I2C_FSL
202#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
203#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
204#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
205#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
206
207
208
209
210
211
212
213#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
214#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
215#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
216#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
217#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
218#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
219#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
220#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
221
222
223#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
224#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
225#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
226#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
227#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
228#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
229#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
230#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
231
232
233#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
234#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
235#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
236#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
237#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
238#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
239#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
240#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
241
242
243#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
244#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
245#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000
246#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
247#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
248#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000
249
250#ifdef CONFIG_PCI
251#define CONFIG_PCI_INDIRECT_BRIDGE
252
253#define CONFIG_PCI_SCAN_SHOW
254#define CONFIG_DOS_PARTITION
255#endif
256
257
258#ifdef CONFIG_FSL_SATA_V2
259#define CONFIG_LIBATA
260#define CONFIG_FSL_SATA
261
262#define CONFIG_SYS_SATA_MAX_DEVICE 2
263#define CONFIG_SATA1
264#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
265#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
266#define CONFIG_SATA2
267#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
268#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
269
270#define CONFIG_LBA48
271#define CONFIG_CMD_SATA
272#define CONFIG_DOS_PARTITION
273#endif
274
275#ifdef CONFIG_FMAN_ENET
276#define CONFIG_MII
277#define CONFIG_ETHPRIME "FM1@DTSEC1"
278#define CONFIG_PHY_GIGE
279#endif
280
281
282
283
284#define CONFIG_LOADS_ECHO
285#define CONFIG_SYS_LOADS_BAUD_CHANGE
286
287
288
289
290#define CONFIG_CMD_ERRATA
291#define CONFIG_CMD_IRQ
292
293#ifdef CONFIG_PCI
294#define CONFIG_CMD_PCI
295#endif
296
297
298
299
300#define CONFIG_SYS_LONGHELP
301#define CONFIG_CMDLINE_EDITING
302#define CONFIG_AUTO_COMPLETE
303#define CONFIG_SYS_LOAD_ADDR 0x2000000
304#ifdef CONFIG_CMD_KGDB
305#define CONFIG_SYS_CBSIZE 1024
306#else
307#define CONFIG_SYS_CBSIZE 256
308#endif
309#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
310#define CONFIG_SYS_MAXARGS 16
311#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
312
313
314
315
316
317
318#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
319#define CONFIG_SYS_BOOTM_LEN (64 << 20)
320
321#ifdef CONFIG_CMD_KGDB
322#define CONFIG_KGDB_BAUDRATE 230400
323#endif
324
325
326
327
328#define CONFIG_ROOTPATH "/opt/nfsroot"
329#define CONFIG_BOOTFILE "uImage"
330#define CONFIG_UBOOTPATH "u-boot.bin"
331
332
333#define CONFIG_LOADADDR 1000000
334
335#define CONFIG_BAUDRATE 115200
336
337#define CONFIG_HVBOOT \
338 "setenv bootargs config-addr=0x60000000; " \
339 "bootm 0x01000000 - 0x00f00000"
340
341#ifdef CONFIG_SYS_NO_FLASH
342#ifndef CONFIG_RAMBOOT_PBL
343#define CONFIG_ENV_IS_NOWHERE
344#endif
345#else
346#define CONFIG_FLASH_CFI_DRIVER
347#define CONFIG_SYS_FLASH_CFI
348#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
349#endif
350
351#if defined(CONFIG_SPIFLASH)
352#define CONFIG_SYS_EXTRA_ENV_RELOC
353#define CONFIG_ENV_IS_IN_SPI_FLASH
354#define CONFIG_ENV_SPI_BUS 0
355#define CONFIG_ENV_SPI_CS 0
356#define CONFIG_ENV_SPI_MAX_HZ 10000000
357#define CONFIG_ENV_SPI_MODE 0
358#define CONFIG_ENV_SIZE 0x2000
359#define CONFIG_ENV_OFFSET 0x100000
360#define CONFIG_ENV_SECT_SIZE 0x10000
361#elif defined(CONFIG_SDCARD)
362#define CONFIG_SYS_EXTRA_ENV_RELOC
363#define CONFIG_ENV_IS_IN_MMC
364#define CONFIG_SYS_MMC_ENV_DEV 0
365#define CONFIG_ENV_SIZE 0x2000
366#define CONFIG_ENV_OFFSET (512 * 0x800)
367#elif defined(CONFIG_NAND)
368#define CONFIG_SYS_EXTRA_ENV_RELOC
369#define CONFIG_ENV_IS_IN_NAND
370#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
371#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
372#elif defined(CONFIG_ENV_IS_NOWHERE)
373#define CONFIG_ENV_SIZE 0x2000
374#else
375#define CONFIG_ENV_IS_IN_FLASH
376#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
377#define CONFIG_ENV_SIZE 0x2000
378#define CONFIG_ENV_SECT_SIZE 0x20000
379#endif
380
381#define CONFIG_SYS_CLK_FREQ 66666666
382#define CONFIG_DDR_CLK_FREQ 133333333
383
384#ifndef __ASSEMBLY__
385unsigned long get_board_sys_clk(void);
386unsigned long get_board_ddr_clk(void);
387#endif
388
389
390
391
392#define CONFIG_SYS_SPD_BUS_NUM 0
393#define SPD_EEPROM_ADDRESS1 0x52
394#define SPD_EEPROM_ADDRESS2 0x54
395#define SPD_EEPROM_ADDRESS3 0x56
396#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
397#define CONFIG_SYS_SDRAM_SIZE 4096
398
399
400
401
402#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
403#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
404 + 0x8000000) | \
405 CSPR_PORT_SIZE_16 | \
406 CSPR_MSEL_NOR | \
407 CSPR_V)
408#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
409#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
410 CSPR_PORT_SIZE_16 | \
411 CSPR_MSEL_NOR | \
412 CSPR_V)
413#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
414
415#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
416
417#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
418 FTIM0_NOR_TEADC(0x5) | \
419 FTIM0_NOR_TEAHC(0x5))
420#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
421 FTIM1_NOR_TRAD_NOR(0x1A) |\
422 FTIM1_NOR_TSEQRAD_NOR(0x13))
423#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
424 FTIM2_NOR_TCH(0x4) | \
425 FTIM2_NOR_TWPH(0x0E) | \
426 FTIM2_NOR_TWP(0x1c))
427#define CONFIG_SYS_NOR_FTIM3 0x0
428
429#define CONFIG_SYS_FLASH_QUIET_TEST
430#define CONFIG_FLASH_SHOW_PROGRESS 45
431
432#define CONFIG_SYS_MAX_FLASH_BANKS 2
433#define CONFIG_SYS_MAX_FLASH_SECT 1024
434#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
435#define CONFIG_SYS_FLASH_WRITE_TOUT 500
436
437#define CONFIG_SYS_FLASH_EMPTY_INFO
438#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
439 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
440
441
442#define CONFIG_NAND_FSL_IFC
443#define CONFIG_SYS_NAND_MAX_ECCPOS 256
444#define CONFIG_SYS_NAND_MAX_OOBFREE 2
445#define CONFIG_SYS_NAND_BASE 0xff800000
446#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
447
448#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
449#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
450 | CSPR_PORT_SIZE_8 \
451 | CSPR_MSEL_NAND \
452 | CSPR_V)
453#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
454
455#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
456 | CSOR_NAND_ECC_DEC_EN \
457 | CSOR_NAND_ECC_MODE_4 \
458 | CSOR_NAND_RAL_3 \
459 | CSOR_NAND_PGS_4K \
460 | CSOR_NAND_SPRZ_224 \
461 | CSOR_NAND_PB(128))
462
463#define CONFIG_SYS_NAND_ONFI_DETECTION
464
465
466#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
467 FTIM0_NAND_TWP(0x18) | \
468 FTIM0_NAND_TWCHT(0x07) | \
469 FTIM0_NAND_TWH(0x0a))
470#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
471 FTIM1_NAND_TWBE(0x39) | \
472 FTIM1_NAND_TRR(0x0e) | \
473 FTIM1_NAND_TRP(0x18))
474#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
475 FTIM2_NAND_TREH(0x0a) | \
476 FTIM2_NAND_TWHRE(0x1e))
477#define CONFIG_SYS_NAND_FTIM3 0x0
478
479#define CONFIG_SYS_NAND_DDR_LAW 11
480#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
481#define CONFIG_SYS_MAX_NAND_DEVICE 1
482#define CONFIG_CMD_NAND
483
484#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
485
486#if defined(CONFIG_NAND)
487#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
488#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
489#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
490#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
491#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
492#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
493#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
494#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
495#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
496#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
497#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
498#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
499#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
500#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
501#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
502#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
503#else
504#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
505#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
506#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
507#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
508#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
509#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
510#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
511#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
512#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
513#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
514#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
515#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
516#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
517#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
518#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
519#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
520#endif
521#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
522#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
523#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
524#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
525#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
526#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
527#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
528#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
529
530
531#define CONFIG_SYS_CPLD_BASE 0xffdf0000
532#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
533#define CONFIG_SYS_CSPR3_EXT (0xf)
534#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
535 | CSPR_PORT_SIZE_8 \
536 | CSPR_MSEL_GPCM \
537 | CSPR_V)
538
539#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
540#define CONFIG_SYS_CSOR3 0x0
541
542
543#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
544 FTIM0_GPCM_TEADC(0x0e) | \
545 FTIM0_GPCM_TEAHC(0x0e))
546#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
547 FTIM1_GPCM_TRAD(0x1f))
548#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
549 FTIM2_GPCM_TCH(0x8) | \
550 FTIM2_GPCM_TWP(0x1f))
551#define CONFIG_SYS_CS3_FTIM3 0x0
552
553#if defined(CONFIG_RAMBOOT_PBL)
554#define CONFIG_SYS_RAMBOOT
555#endif
556
557
558#define CONFIG_SYS_FSL_I2C_SPEED 100000
559#define CONFIG_SYS_FSL_I2C2_SPEED 100000
560#define I2C_MUX_PCA_ADDR_PRI 0x77
561#define I2C_MUX_PCA_ADDR_SEC 0x76
562
563#define I2C_MUX_CH_DEFAULT 0x8
564#define I2C_MUX_CH_VOL_MONITOR 0xa
565#define I2C_MUX_CH_VSC3316_FS 0xc
566#define I2C_MUX_CH_VSC3316_BS 0xd
567
568
569#define I2C_VOL_MONITOR_ADDR 0x40
570#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
571#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
572#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
573
574#define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
575#ifndef CONFIG_SPL_BUILD
576#define CONFIG_VID
577#endif
578#define CONFIG_VOL_MONITOR_IR36021_SET
579#define CONFIG_VOL_MONITOR_IR36021_READ
580
581#define VDD_MV_MIN 819
582#define VDD_MV_MAX 1212
583
584
585
586
587#define CONFIG_SF_DEFAULT_SPEED 10000000
588#define CONFIG_SF_DEFAULT_MODE 0
589
590
591#ifndef CONFIG_NOBQFMAN
592#define CONFIG_SYS_DPAA_QBMAN
593#define CONFIG_SYS_BMAN_NUM_PORTALS 50
594#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
595#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
596#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
597#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
598#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
599#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
600#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
601#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
602 CONFIG_SYS_BMAN_CENA_SIZE)
603#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
604#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
605#define CONFIG_SYS_QMAN_NUM_PORTALS 50
606#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
607#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
608#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
609#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
610#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
611#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
612#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
613#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
614 CONFIG_SYS_QMAN_CENA_SIZE)
615#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
616#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
617
618#define CONFIG_SYS_DPAA_FMAN
619#define CONFIG_SYS_DPAA_PME
620#define CONFIG_SYS_PMAN
621#define CONFIG_SYS_DPAA_DCE
622#define CONFIG_SYS_DPAA_RMAN
623#define CONFIG_SYS_INTERLAKEN
624
625
626#if defined(CONFIG_SPIFLASH)
627
628
629
630
631#define CONFIG_SYS_QE_FW_IN_SPIFLASH
632#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
633#elif defined(CONFIG_SDCARD)
634
635
636
637
638
639#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
640#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
641#elif defined(CONFIG_NAND)
642#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
643#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
644#else
645#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
646#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
647#endif
648#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
649#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
650#endif
651
652#ifdef CONFIG_SYS_DPAA_FMAN
653#define CONFIG_FMAN_ENET
654#define CONFIG_PHYLIB_10G
655#define CONFIG_PHY_VITESSE
656#define CONFIG_PHY_CORTINA
657#define CONFIG_SYS_CORTINA_FW_IN_NOR
658#define CONFIG_CORTINA_FW_ADDR 0xefe00000
659#define CONFIG_CORTINA_FW_LENGTH 0x40000
660#define CONFIG_PHY_TERANETICS
661#define SGMII_PHY_ADDR1 0x0
662#define SGMII_PHY_ADDR2 0x1
663#define SGMII_PHY_ADDR3 0x2
664#define SGMII_PHY_ADDR4 0x3
665#define SGMII_PHY_ADDR5 0x4
666#define SGMII_PHY_ADDR6 0x5
667#define SGMII_PHY_ADDR7 0x6
668#define SGMII_PHY_ADDR8 0x7
669#define FM1_10GEC1_PHY_ADDR 0x10
670#define FM1_10GEC2_PHY_ADDR 0x11
671#define FM2_10GEC1_PHY_ADDR 0x12
672#define FM2_10GEC2_PHY_ADDR 0x13
673#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
674#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
675#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
676#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
677#endif
678
679
680#ifdef CONFIG_FSL_SATA_V2
681#define CONFIG_LIBATA
682#define CONFIG_FSL_SATA
683
684#define CONFIG_SYS_SATA_MAX_DEVICE 2
685#define CONFIG_SATA1
686#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
687#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
688#define CONFIG_SATA2
689#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
690#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
691
692#define CONFIG_LBA48
693#define CONFIG_CMD_SATA
694#define CONFIG_DOS_PARTITION
695#endif
696
697#ifdef CONFIG_FMAN_ENET
698#define CONFIG_MII
699#define CONFIG_ETHPRIME "FM1@DTSEC1"
700#define CONFIG_PHY_GIGE
701#endif
702
703
704
705
706#define CONFIG_USB_EHCI
707#define CONFIG_USB_EHCI_FSL
708#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
709#define CONFIG_HAS_FSL_DR_USB
710
711#define CONFIG_MMC
712
713#ifdef CONFIG_MMC
714#define CONFIG_FSL_ESDHC
715#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
716#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
717#define CONFIG_GENERIC_MMC
718#define CONFIG_DOS_PARTITION
719#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
720#endif
721
722
723#ifdef CONFIG_FSL_CAAM
724#define CONFIG_CMD_HASH
725#define CONFIG_SHA_HW_ACCEL
726#endif
727
728
729#define __USB_PHY_TYPE utmi
730
731
732
733
734
735
736
737#ifdef CONFIG_PPC_T4240
738#define CTRL_INTLV_PREFERED 3way_4KB
739#else
740#define CTRL_INTLV_PREFERED cacheline
741#endif
742
743#define CONFIG_EXTRA_ENV_SETTINGS \
744 "hwconfig=fsl_ddr:" \
745 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
746 "bank_intlv=auto;" \
747 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
748 "netdev=eth0\0" \
749 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
750 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
751 "tftpflash=tftpboot $loadaddr $uboot && " \
752 "protect off $ubootaddr +$filesize && " \
753 "erase $ubootaddr +$filesize && " \
754 "cp.b $loadaddr $ubootaddr $filesize && " \
755 "protect on $ubootaddr +$filesize && " \
756 "cmp.b $loadaddr $ubootaddr $filesize\0" \
757 "consoledev=ttyS0\0" \
758 "ramdiskaddr=2000000\0" \
759 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
760 "fdtaddr=1e00000\0" \
761 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
762 "bdev=sda3\0"
763
764#define CONFIG_HVBOOT \
765 "setenv bootargs config-addr=0x60000000; " \
766 "bootm 0x01000000 - 0x00f00000"
767
768#define CONFIG_LINUX \
769 "setenv bootargs root=/dev/ram rw " \
770 "console=$consoledev,$baudrate $othbootargs;" \
771 "setenv ramdiskaddr 0x02000000;" \
772 "setenv fdtaddr 0x00c00000;" \
773 "setenv loadaddr 0x1000000;" \
774 "bootm $loadaddr $ramdiskaddr $fdtaddr"
775
776#define CONFIG_HDBOOT \
777 "setenv bootargs root=/dev/$bdev rw " \
778 "console=$consoledev,$baudrate $othbootargs;" \
779 "tftp $loadaddr $bootfile;" \
780 "tftp $fdtaddr $fdtfile;" \
781 "bootm $loadaddr - $fdtaddr"
782
783#define CONFIG_NFSBOOTCOMMAND \
784 "setenv bootargs root=/dev/nfs rw " \
785 "nfsroot=$serverip:$rootpath " \
786 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
787 "console=$consoledev,$baudrate $othbootargs;" \
788 "tftp $loadaddr $bootfile;" \
789 "tftp $fdtaddr $fdtfile;" \
790 "bootm $loadaddr - $fdtaddr"
791
792#define CONFIG_RAMBOOTCOMMAND \
793 "setenv bootargs root=/dev/ram rw " \
794 "console=$consoledev,$baudrate $othbootargs;" \
795 "tftp $ramdiskaddr $ramdiskfile;" \
796 "tftp $loadaddr $bootfile;" \
797 "tftp $fdtaddr $fdtfile;" \
798 "bootm $loadaddr $ramdiskaddr $fdtaddr"
799
800#define CONFIG_BOOTCOMMAND CONFIG_LINUX
801
802#include <asm/fsl_secure_boot.h>
803
804#endif
805