1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ 21#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */ 22 23#define CONFIG_SYS_TEXT_BASE 0x40000000 24 25#ifdef CONFIG_LCD /* with LCD controller ? */ 26#define CONFIG_MPC8XX_LCD 27/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ 28#endif 29 30#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 31#define CONFIG_SYS_SMC_RXBUFLEN 128 32#define CONFIG_SYS_MAXIDLE 10 33#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 34 35#define CONFIG_BOOTCOUNT_LIMIT 36 37 38#define CONFIG_BOARD_TYPES 1 /* support board types */ 39 40#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 41 42#undef CONFIG_BOOTARGS 43 44#define CONFIG_EXTRA_ENV_SETTINGS \ 45 "netdev=eth0\0" \ 46 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 47 "nfsroot=${serverip}:${rootpath}\0" \ 48 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 49 "addip=setenv bootargs ${bootargs} " \ 50 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 51 ":${hostname}:${netdev}:off panic=1\0" \ 52 "flash_nfs=run nfsargs addip;" \ 53 "bootm ${kernel_addr}\0" \ 54 "flash_self=run ramargs addip;" \ 55 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 56 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 57 "rootpath=/opt/eldk/ppc_8xx\0" \ 58 "hostname=TQM823M\0" \ 59 "bootfile=TQM823M/uImage\0" \ 60 "fdt_addr=40080000\0" \ 61 "kernel_addr=400A0000\0" \ 62 "ramdisk_addr=40280000\0" \ 63 "u-boot=TQM823M/u-image.bin\0" \ 64 "load=tftp 200000 ${u-boot}\0" \ 65 "update=prot off 40000000 +${filesize};" \ 66 "era 40000000 +${filesize};" \ 67 "cp.b 200000 40000000 ${filesize};" \ 68 "sete filesize;save\0" \ 69 "" 70#define CONFIG_BOOTCOMMAND "run flash_self" 71 72#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 73#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 74 75#undef CONFIG_WATCHDOG /* watchdog disabled */ 76 77#ifdef CONFIG_LCD 78# undef CONFIG_STATUS_LED /* disturbs display */ 79#else 80# define CONFIG_STATUS_LED 1 /* Status LED enabled */ 81#endif /* CONFIG_LCD */ 82 83#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 84 85/* 86 * BOOTP options 87 */ 88#define CONFIG_BOOTP_SUBNETMASK 89#define CONFIG_BOOTP_GATEWAY 90#define CONFIG_BOOTP_HOSTNAME 91#define CONFIG_BOOTP_BOOTPATH 92#define CONFIG_BOOTP_BOOTFILESIZE 93 94#define CONFIG_MAC_PARTITION 95#define CONFIG_DOS_PARTITION 96 97#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 98 99/* 100 * Command line configuration. 101 */ 102#define CONFIG_CMD_DATE 103#define CONFIG_CMD_IDE 104#define CONFIG_CMD_JFFS2 105 106#define CONFIG_NETCONSOLE 107 108/* 109 * Miscellaneous configurable options 110 */ 111#define CONFIG_SYS_LONGHELP /* undef to save memory */ 112 113#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 114 115#if defined(CONFIG_CMD_KGDB) 116#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 117#else 118#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 119#endif 120#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 121#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 122#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 123 124#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 125#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 126 127#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 128 129/* 130 * Low Level Configuration Settings 131 * (address mappings, register initial values, etc.) 132 * You should know what you are doing if you make changes here. 133 */ 134/*----------------------------------------------------------------------- 135 * Internal Memory Mapped Register 136 */ 137#define CONFIG_SYS_IMMR 0xFFF00000 138 139/*----------------------------------------------------------------------- 140 * Definitions for initial stack pointer and data area (in DPRAM) 141 */ 142#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 143#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 144#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 145#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 146 147/*----------------------------------------------------------------------- 148 * Start addresses for the final memory configuration 149 * (Set up by the startup code) 150 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 151 */ 152#define CONFIG_SYS_SDRAM_BASE 0x00000000 153#define CONFIG_SYS_FLASH_BASE 0x40000000 154#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 155#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 156#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 157 158/* 159 * For booting Linux, the board info and command line data 160 * have to be in the first 8 MB of memory, since this is 161 * the maximum mapped by the Linux kernel during initialization. 162 */ 163#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 164 165/*----------------------------------------------------------------------- 166 * FLASH organization 167 */ 168 169/* use CFI flash driver */ 170#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 171#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 172#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 173#define CONFIG_SYS_FLASH_EMPTY_INFO 174#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 175#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 176#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 177 178#define CONFIG_ENV_IS_IN_FLASH 1 179#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 180#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 181#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ 182 183/* Address and size of Redundant Environment Sector */ 184#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 185#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 186 187#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 188 189#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 190 191/*----------------------------------------------------------------------- 192 * Dynamic MTD partition support 193 */ 194#define CONFIG_CMD_MTDPARTS 195#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 196#define CONFIG_FLASH_CFI_MTD 197#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 198 199#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 200 "128k(dtb)," \ 201 "1920k(kernel)," \ 202 "5632(rootfs)," \ 203 "4m(data)" 204 205/*----------------------------------------------------------------------- 206 * Hardware Information Block 207 */ 208#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 209#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 210#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 211 212/*----------------------------------------------------------------------- 213 * Cache Configuration 214 */ 215#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 216#if defined(CONFIG_CMD_KGDB) 217#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 218#endif 219 220/*----------------------------------------------------------------------- 221 * SYPCR - System Protection Control 11-9 222 * SYPCR can only be written once after reset! 223 *----------------------------------------------------------------------- 224 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 225 */ 226#if defined(CONFIG_WATCHDOG) 227#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 228 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 229#else 230#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 231#endif 232 233/*----------------------------------------------------------------------- 234 * SIUMCR - SIU Module Configuration 11-6 235 *----------------------------------------------------------------------- 236 * PCMCIA config., multi-function pin tri-state 237 */ 238#ifndef CONFIG_CAN_DRIVER 239#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 240#else /* we must activate GPL5 in the SIUMCR for CAN */ 241#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 242#endif /* CONFIG_CAN_DRIVER */ 243 244/*----------------------------------------------------------------------- 245 * TBSCR - Time Base Status and Control 11-26 246 *----------------------------------------------------------------------- 247 * Clear Reference Interrupt Status, Timebase freezing enabled 248 */ 249#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 250 251/*----------------------------------------------------------------------- 252 * RTCSC - Real-Time Clock Status and Control Register 11-27 253 *----------------------------------------------------------------------- 254 */ 255#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 256 257/*----------------------------------------------------------------------- 258 * PISCR - Periodic Interrupt Status and Control 11-31 259 *----------------------------------------------------------------------- 260 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 261 */ 262#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 263 264/*----------------------------------------------------------------------- 265 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 266 *----------------------------------------------------------------------- 267 * Reset PLL lock status sticky bit, timer expired status bit and timer 268 * interrupt status bit 269 */ 270#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 271 272/*----------------------------------------------------------------------- 273 * SCCR - System Clock and reset Control Register 15-27 274 *----------------------------------------------------------------------- 275 * Set clock output, timebase and RTC source and divider, 276 * power management and some other internal clocks 277 */ 278#define SCCR_MASK SCCR_EBDF11 279#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 280 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 281 SCCR_DFALCD00) 282 283/*----------------------------------------------------------------------- 284 * PCMCIA stuff 285 *----------------------------------------------------------------------- 286 * 287 */ 288#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 289#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 290#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 291#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 292#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 293#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 294#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 295#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 296 297/*----------------------------------------------------------------------- 298 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 299 *----------------------------------------------------------------------- 300 */ 301 302#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 303#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 304 305#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 306#undef CONFIG_IDE_LED /* LED for ide not supported */ 307#undef CONFIG_IDE_RESET /* reset for ide not supported */ 308 309#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 310#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 311 312#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 313 314#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 315 316/* Offset for data I/O */ 317#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 318 319/* Offset for normal register accesses */ 320#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 321 322/* Offset for alternate registers */ 323#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 324 325/*----------------------------------------------------------------------- 326 * 327 *----------------------------------------------------------------------- 328 * 329 */ 330#define CONFIG_SYS_DER 0 331 332/* 333 * Init Memory Controller: 334 * 335 * BR0/1 and OR0/1 (FLASH) 336 */ 337 338#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 339#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 340 341/* used to re-map FLASH both when starting from SRAM or FLASH: 342 * restrict access enough to keep SRAM working (if any) 343 * but not too much to meddle with FLASH accesses 344 */ 345#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 346#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 347 348/* 349 * FLASH timing: 350 */ 351#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 352 OR_SCY_3_CLK | OR_EHTR | OR_BI) 353 354#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 355#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 356#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 357 358#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 359#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 360#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 361 362/* 363 * BR2/3 and OR2/3 (SDRAM) 364 * 365 */ 366#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 367#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 368#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 369 370/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 371#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 372 373#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 374#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 375 376#ifndef CONFIG_CAN_DRIVER 377#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 378#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 379#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 380#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 381#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 382#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 383#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 384 BR_PS_8 | BR_MS_UPMB | BR_V ) 385#endif /* CONFIG_CAN_DRIVER */ 386 387/* 388 * Memory Periodic Timer Prescaler 389 * 390 * The Divider for PTA (refresh timer) configuration is based on an 391 * example SDRAM configuration (64 MBit, one bank). The adjustment to 392 * the number of chip selects (NCS) and the actually needed refresh 393 * rate is done by setting MPTPR. 394 * 395 * PTA is calculated from 396 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 397 * 398 * gclk CPU clock (not bus clock!) 399 * Trefresh Refresh cycle * 4 (four word bursts used) 400 * 401 * 4096 Rows from SDRAM example configuration 402 * 1000 factor s -> ms 403 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 404 * 4 Number of refresh cycles per period 405 * 64 Refresh cycle in ms per number of rows 406 * -------------------------------------------- 407 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 408 * 409 * 50 MHz => 50.000.000 / Divider = 98 410 * 66 Mhz => 66.000.000 / Divider = 129 411 * 80 Mhz => 80.000.000 / Divider = 156 412 */ 413 414#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 415#define CONFIG_SYS_MAMR_PTA 98 416 417/* 418 * For 16 MBit, refresh rates could be 31.3 us 419 * (= 64 ms / 2K = 125 / quad bursts). 420 * For a simpler initialization, 15.6 us is used instead. 421 * 422 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 423 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 424 */ 425#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 426#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 427 428/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 429#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 430#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 431 432/* 433 * MAMR settings for SDRAM 434 */ 435 436/* 8 column SDRAM */ 437#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 438 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 439 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 440/* 9 column SDRAM */ 441#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 442 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 443 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 444 445#define CONFIG_HWCONFIG 1 446 447#endif /* __CONFIG_H */ 448