1/* 2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef _CONFIG_DB_MV7846MP_GP_H 8#define _CONFIG_DB_MV7846MP_GP_H 9 10/* 11 * High Level Configuration Options (easy to change) 12 */ 13#define CONFIG_DB_784MP_GP /* Board target name for DDR training */ 14 15#define CONFIG_DISPLAY_BOARDINFO_LATE 16 17/* 18 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 19 * for DDR ECC byte filling in the SPL before loading the main 20 * U-Boot into it. 21 */ 22#define CONFIG_SYS_TEXT_BASE 0x00800000 23#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 24 25/* 26 * Commands configuration 27 */ 28#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 29#define CONFIG_CMD_ENV 30#define CONFIG_CMD_NAND 31#define CONFIG_CMD_PCI 32#define CONFIG_CMD_SATA 33 34/* I2C */ 35#define CONFIG_SYS_I2C 36#define CONFIG_SYS_I2C_MVTWSI 37#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 38#define CONFIG_SYS_I2C_SLAVE 0x0 39#define CONFIG_SYS_I2C_SPEED 100000 40 41/* USB/EHCI configuration */ 42#define CONFIG_EHCI_IS_TDI 43#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 44 45/* SPI NOR flash default params, used by sf commands */ 46#define CONFIG_SF_DEFAULT_SPEED 1000000 47#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 48 49/* Environment in SPI NOR flash */ 50#define CONFIG_ENV_IS_IN_SPI_FLASH 51#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 52#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 53#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 54 55#define CONFIG_PHY_MARVELL /* there is a marvell phy */ 56#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 57 58#define CONFIG_SYS_ALT_MEMTEST 59 60/* SATA support */ 61#define CONFIG_SYS_SATA_MAX_DEVICE 2 62#define CONFIG_SATA_MV 63#define CONFIG_LIBATA 64#define CONFIG_LBA48 65#define CONFIG_EFI_PARTITION 66#define CONFIG_DOS_PARTITION 67 68/* Additional FS support/configuration */ 69#define CONFIG_SUPPORT_VFAT 70 71/* PCIe support */ 72#ifndef CONFIG_SPL_BUILD 73#define CONFIG_PCI_MVEBU 74#define CONFIG_PCI_SCAN_SHOW 75#endif 76 77/* NAND */ 78#define CONFIG_SYS_NAND_USE_FLASH_BBT 79#define CONFIG_SYS_NAND_ONFI_DETECTION 80 81/* 82 * mv-common.h should be defined after CMD configs since it used them 83 * to enable certain macros 84 */ 85#include "mv-common.h" 86 87/* 88 * Memory layout while starting into the bin_hdr via the 89 * BootROM: 90 * 91 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 92 * 0x4000.4030 bin_hdr start address 93 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 94 * 0x4007.fffc BootROM stack top 95 * 96 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 97 * L2 cache thus cannot be used. 98 */ 99 100/* SPL */ 101/* Defines for SPL */ 102#define CONFIG_SPL_FRAMEWORK 103#define CONFIG_SPL_TEXT_BASE 0x40004030 104#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 105 106#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 107#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 108 109#ifdef CONFIG_SPL_BUILD 110#define CONFIG_SYS_MALLOC_SIMPLE 111#endif 112 113#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 114#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 115 116/* SPL related SPI defines */ 117#define CONFIG_SPL_SPI_LOAD 118#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 119#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 120 121/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 122#define CONFIG_SPD_EEPROM 0x4e 123#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ 124 125#endif /* _CONFIG_DB_MV7846MP_GP_H */ 126