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8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12
13
14
15#define CONFIG_E300 1
16#define CONFIG_MPC83xx 1
17#define CONFIG_MPC830x 1
18#define CONFIG_MPC8308 1
19#define CONFIG_HRCON 1
20
21#define CONFIG_SYS_TEXT_BASE 0xFE000000
22
23#define CONFIG_BOARD_EARLY_INIT_F
24#define CONFIG_BOARD_EARLY_INIT_R
25#define CONFIG_LAST_STAGE_INIT
26
27#define CONFIG_MMC
28#define CONFIG_FSL_ESDHC
29#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
30#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
31
32#define CONFIG_GENERIC_MMC
33#define CONFIG_DOS_PARTITION
34
35#define CONFIG_CMD_FPGAD
36#define CONFIG_CMD_IOLOOP
37
38
39
40
41#define CONFIG_83XX_CLKIN 33333333
42#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
43
44
45
46
47
48
49
50#define CONFIG_SYS_HRCW_LOW (\
51 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
52 HRCWL_DDR_TO_SCB_CLK_2X1 |\
53 HRCWL_SVCOD_DIV_2 |\
54 HRCWL_CSB_TO_CLKIN_4X1 |\
55 HRCWL_CORE_TO_CSB_3X1)
56
57
58
59
60
61
62
63#define CONFIG_SYS_HRCW_HIGH (\
64 HRCWH_PCI_HOST |\
65 HRCWH_PCI1_ARBITER_ENABLE |\
66 HRCWH_CORE_ENABLE |\
67 HRCWH_FROM_0XFFF00100 |\
68 HRCWH_BOOTSEQ_DISABLE |\
69 HRCWH_SW_WATCHDOG_DISABLE |\
70 HRCWH_ROM_LOC_LOCAL_16BIT |\
71 HRCWH_RL_EXT_LEGACY |\
72 HRCWH_TSEC1M_IN_RGMII |\
73 HRCWH_TSEC2M_IN_RGMII |\
74 HRCWH_BIG_ENDIAN)
75
76
77
78
79#define CONFIG_SYS_SICRH (\
80 SICRH_ESDHC_A_SD |\
81 SICRH_ESDHC_B_SD |\
82 SICRH_ESDHC_C_SD |\
83 SICRH_GPIO_A_GPIO |\
84 SICRH_GPIO_B_GPIO |\
85 SICRH_IEEE1588_A_GPIO |\
86 SICRH_USB |\
87 SICRH_GTM_GPIO |\
88 SICRH_IEEE1588_B_GPIO |\
89 SICRH_ETSEC2_GPIO |\
90 SICRH_GPIOSEL_1 |\
91 SICRH_TMROBI_V3P3 |\
92 SICRH_TSOBI1_V2P5 |\
93 SICRH_TSOBI2_V2P5)
94#define CONFIG_SYS_SICRL (\
95 SICRL_SPI_PF0 |\
96 SICRL_UART_PF0 |\
97 SICRL_IRQ_PF0 |\
98 SICRL_I2C2_PF0 |\
99 SICRL_ETSEC1_GTX_CLK125)
100
101
102
103
104#define CONFIG_SYS_IMMR 0xE0000000
105
106
107
108
109#define CONFIG_FSL_SERDES
110#define CONFIG_FSL_SERDES1 0xe3000
111
112
113
114
115#define CONFIG_SYS_ACR_PIPE_DEP 3
116#define CONFIG_SYS_ACR_RPTCNT 3
117#define CONFIG_SYS_SPCR_TSECEP 3
118
119
120
121
122#define CONFIG_SYS_DDR_BASE 0x00000000
123#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
124#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
125#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
126#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
127 | DDRCDR_PZ_LOZ \
128 | DDRCDR_NZ_LOZ \
129 | DDRCDR_ODT \
130 | DDRCDR_Q_DRN)
131
132
133
134
135
136
137#define CONFIG_SYS_DDR_SIZE 128
138
139#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
140#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
141 | CSCONFIG_ODT_RD_NEVER \
142 | CSCONFIG_ODT_WR_ONLY_CURRENT \
143 | CSCONFIG_BANK_BIT_3 \
144 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
145
146#define CONFIG_SYS_DDR_TIMING_3 0
147#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
148 | (0 << TIMING_CFG0_WRT_SHIFT) \
149 | (0 << TIMING_CFG0_RRT_SHIFT) \
150 | (0 << TIMING_CFG0_WWT_SHIFT) \
151 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
152 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
153 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
154 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
155
156#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
157 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
158 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
159 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
160 | (9 << TIMING_CFG1_REFREC_SHIFT) \
161 | (2 << TIMING_CFG1_WRREC_SHIFT) \
162 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
163 | (2 << TIMING_CFG1_WRTORD_SHIFT))
164
165#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
166 | (4 << TIMING_CFG2_CPO_SHIFT) \
167 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
168 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
169 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
170 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
171 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
172
173#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
174 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
175
176#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
177 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
178 | SDRAM_CFG_DBW_16)
179
180
181#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
182#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
183 | (0x0242 << SDRAM_MODE_SD_SHIFT))
184
185#define CONFIG_SYS_DDR_MODE2 0x00000000
186
187
188
189
190#define CONFIG_SYS_MEMTEST_START 0x00001000
191#define CONFIG_SYS_MEMTEST_END 0x07f00000
192
193
194
195
196#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
197
198#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
199#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
200
201
202
203
204#define CONFIG_SYS_INIT_RAM_LOCK 1
205#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
206#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
207#define CONFIG_SYS_GBL_DATA_OFFSET \
208 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
209
210
211
212
213#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
214#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
215#define CONFIG_SYS_LBC_LBCR 0x00040000
216
217
218
219
220#if 1
221#define CONFIG_SYS_FLASH_CFI
222#define CONFIG_FLASH_CFI_DRIVER
223#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
224#define CONFIG_FLASH_CFI_LEGACY
225#define CONFIG_SYS_FLASH_LEGACY_512Kx16
226#else
227#define CONFIG_SYS_NO_FLASH
228#endif
229
230#define CONFIG_SYS_FLASH_BASE 0xFE000000
231#define CONFIG_SYS_FLASH_SIZE 8
232#define CONFIG_SYS_FLASH_PROTECTION 1
233
234
235#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
236#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
237
238#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
239 | BR_PS_16 \
240 | BR_MS_GPCM \
241 | BR_V)
242#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
243 | OR_UPM_XAM \
244 | OR_GPCM_CSNT \
245 | OR_GPCM_ACS_DIV2 \
246 | OR_GPCM_XACS \
247 | OR_GPCM_SCY_15 \
248 | OR_GPCM_TRLX_SET \
249 | OR_GPCM_EHTR_SET)
250
251#define CONFIG_SYS_MAX_FLASH_BANKS 1
252#define CONFIG_SYS_MAX_FLASH_SECT 135
253
254#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
255#define CONFIG_SYS_FLASH_WRITE_TOUT 500
256
257
258
259
260#define CONFIG_SYS_FPGA0_BASE 0xE0600000
261#define CONFIG_SYS_FPGA0_SIZE 1
262
263
264#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
265#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
266
267#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
268 | BR_PS_16 \
269 | BR_MS_GPCM \
270 | BR_V)
271#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
272 | OR_UPM_XAM \
273 | OR_GPCM_CSNT \
274 | OR_GPCM_ACS_DIV2 \
275 | OR_GPCM_XACS \
276 | OR_GPCM_SCY_15 \
277 | OR_GPCM_TRLX_SET \
278 | OR_GPCM_EHTR_SET)
279
280#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
281#define CONFIG_SYS_FPGA_DONE(k) 0x0010
282
283#define CONFIG_SYS_FPGA_COUNT 1
284
285#define CONFIG_SYS_MCLINK_MAX 3
286
287#define CONFIG_SYS_FPGA_PTR \
288 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
289
290
291
292
293#define CONFIG_CONS_INDEX 2
294#define CONFIG_SYS_NS16550_SERIAL
295#define CONFIG_SYS_NS16550_REG_SIZE 1
296#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
297
298#define CONFIG_SYS_BAUDRATE_TABLE \
299 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
300
301#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
302#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
303
304
305
306
307#define CONFIG_SYS_I2C
308#define CONFIG_SYS_I2C_FSL
309#define CONFIG_SYS_FSL_I2C_SPEED 400000
310#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
311#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
312
313#define CONFIG_PCA953X
314#define CONFIG_PCA9698
315
316#define CONFIG_SYS_I2C_IHS
317#define CONFIG_SYS_I2C_IHS_CH0
318#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
319#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
320#define CONFIG_SYS_I2C_IHS_CH1
321#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
322#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
323#define CONFIG_SYS_I2C_IHS_CH2
324#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
325#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
326#define CONFIG_SYS_I2C_IHS_CH3
327#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
328#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
329
330#ifdef CONFIG_HRCON_DH
331#define CONFIG_SYS_I2C_IHS_DUAL
332#define CONFIG_SYS_I2C_IHS_CH0_1
333#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
334#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
335#define CONFIG_SYS_I2C_IHS_CH1_1
336#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
337#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
338#define CONFIG_SYS_I2C_IHS_CH2_1
339#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
340#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
341#define CONFIG_SYS_I2C_IHS_CH3_1
342#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
343#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
344#endif
345
346
347
348
349#define CONFIG_SYS_I2C_SOFT
350#define CONFIG_SYS_I2C_SOFT_SPEED 50000
351#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
352#define I2C_SOFT_DECLARATIONS2
353#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
354#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
355#define I2C_SOFT_DECLARATIONS3
356#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
357#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
358#define I2C_SOFT_DECLARATIONS4
359#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
360#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
361#define I2C_SOFT_DECLARATIONS5
362#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
363#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
364#define I2C_SOFT_DECLARATIONS6
365#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
366#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
367#define I2C_SOFT_DECLARATIONS7
368#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
369#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
370#define I2C_SOFT_DECLARATIONS8
371#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
372#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
373
374#ifdef CONFIG_HRCON_DH
375#define I2C_SOFT_DECLARATIONS9
376#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
377#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
378#define I2C_SOFT_DECLARATIONS10
379#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
380#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
381#define I2C_SOFT_DECLARATIONS11
382#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
383#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
384#define I2C_SOFT_DECLARATIONS12
385#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
386#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
387#endif
388
389#ifdef CONFIG_HRCON_DH
390#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
391#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
392#define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \
393 {12, 0x4c} }
394#else
395#define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12}
396#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
397#define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \
398 {8, 0x4c} }
399#endif
400
401#ifndef __ASSEMBLY__
402void fpga_gpio_set(unsigned int bus, int pin);
403void fpga_gpio_clear(unsigned int bus, int pin);
404int fpga_gpio_get(unsigned int bus, int pin);
405void fpga_control_set(unsigned int bus, int pin);
406void fpga_control_clear(unsigned int bus, int pin);
407#endif
408
409#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
410#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
411#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
412
413#ifdef CONFIG_HRCON_DH
414#define I2C_ACTIVE \
415 do { \
416 if (I2C_ADAP_HWNR > 7) \
417 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
418 else \
419 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
420 } while (0)
421#else
422#define I2C_ACTIVE { }
423#endif
424#define I2C_TRISTATE { }
425#define I2C_READ \
426 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
427#define I2C_SDA(bit) \
428 do { \
429 if (bit) \
430 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
431 else \
432 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
433 } while (0)
434#define I2C_SCL(bit) \
435 do { \
436 if (bit) \
437 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
438 else \
439 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
440 } while (0)
441#define I2C_DELAY udelay(25)
442
443
444
445
446#define CONFIG_BITBANGMII
447#define CONFIG_BITBANGMII_MULTI
448
449
450
451
452#define CONFIG_SYS_OSD_SCREENS 1
453#define CONFIG_SYS_DP501_DIFFERENTIAL
454#define CONFIG_SYS_DP501_VCAPCTRL0 0x01
455
456#ifdef CONFIG_HRCON_DH
457#define CONFIG_SYS_OSD_DH
458#endif
459
460
461
462
463
464#define CONFIG_SYS_PCIE1_BASE 0xA0000000
465#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
466#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
467#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
468#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
469#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
470#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
471#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
472#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
473
474
475#define CONFIG_SYS_SCCR_PCIEXP1CM 1
476
477#define CONFIG_PCI_INDIRECT_BRIDGE
478#define CONFIG_PCIE
479
480#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
481#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
482
483
484
485
486#define CONFIG_TSEC_ENET
487#define CONFIG_SYS_TSEC1_OFFSET 0x24000
488#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
489
490
491
492
493#define CONFIG_MII 1
494#define CONFIG_TSEC1
495#define CONFIG_TSEC1_NAME "eTSEC0"
496#define TSEC1_PHY_ADDR 1
497#define TSEC1_PHYIDX 0
498#define TSEC1_FLAGS TSEC_GIGABIT
499
500
501#define CONFIG_ETHPRIME "eTSEC0"
502
503
504
505
506#if 1
507#define CONFIG_ENV_IS_IN_FLASH 1
508#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
509 CONFIG_SYS_MONITOR_LEN)
510#define CONFIG_ENV_SECT_SIZE 0x10000
511#define CONFIG_ENV_SIZE 0x2000
512#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
513#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
514#else
515#define CONFIG_ENV_IS_NOWHERE
516#define CONFIG_ENV_SIZE 0x2000
517#endif
518
519#define CONFIG_LOADS_ECHO 1
520#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
521
522
523
524
525#define CONFIG_CMD_PCI
526
527#define CONFIG_CMDLINE_EDITING 1
528#define CONFIG_AUTO_COMPLETE
529
530
531
532
533#define CONFIG_SYS_LONGHELP
534#define CONFIG_SYS_LOAD_ADDR 0x2000000
535#define CONFIG_SYS_HZ 1000
536
537#define CONFIG_SYS_CBSIZE 1024
538
539
540#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
541#define CONFIG_SYS_MAXARGS 16
542#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
543
544
545
546
547
548
549#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
550
551
552
553
554#define CONFIG_SYS_HID0_INIT 0x000000000
555#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
556 HID0_ENABLE_INSTRUCTION_CACHE | \
557 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
558#define CONFIG_SYS_HID2 HID2_HBE
559
560
561
562
563
564
565#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
566 BATL_MEMCOHERENCE)
567#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
568 BATU_VS | BATU_VP)
569#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
570#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
571
572
573#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
574 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
575#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
576 BATU_VP)
577#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
578#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
579
580
581#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
582 BATL_MEMCOHERENCE)
583#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
584 BATU_VS | BATU_VP)
585#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
586 BATL_CACHEINHIBIT | \
587 BATL_GUARDEDSTORAGE)
588#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
589
590
591#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
592#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
593 BATU_VS | BATU_VP)
594#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
595#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
596
597
598
599
600
601#define CONFIG_ENV_OVERWRITE
602
603#if defined(CONFIG_TSEC_ENET)
604#define CONFIG_HAS_ETH0
605#endif
606
607#define CONFIG_BAUDRATE 115200
608
609#define CONFIG_LOADADDR 800000
610
611
612#define CONFIG_HOSTNAME hrcon
613#define CONFIG_ROOTPATH "/opt/nfsroot"
614#define CONFIG_BOOTFILE "uImage"
615
616#define CONFIG_PREBOOT
617
618#define CONFIG_EXTRA_ENV_SETTINGS \
619 "netdev=eth0\0" \
620 "consoledev=ttyS1\0" \
621 "u-boot=u-boot.bin\0" \
622 "kernel_addr=1000000\0" \
623 "fdt_addr=C00000\0" \
624 "fdtfile=hrcon.dtb\0" \
625 "load=tftp ${loadaddr} ${u-boot}\0" \
626 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
627 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
628 " +${filesize};cp.b ${fileaddr} " \
629 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
630 "upd=run load update\0" \
631
632#define CONFIG_NFSBOOTCOMMAND \
633 "setenv bootargs root=/dev/nfs rw " \
634 "nfsroot=$serverip:$rootpath " \
635 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
636 "console=$consoledev,$baudrate $othbootargs;" \
637 "tftp ${kernel_addr} $bootfile;" \
638 "tftp ${fdt_addr} $fdtfile;" \
639 "bootm ${kernel_addr} - ${fdt_addr}"
640
641#define CONFIG_MMCBOOTCOMMAND \
642 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
643 "console=$consoledev,$baudrate $othbootargs;" \
644 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
645 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
646 "bootm ${kernel_addr} - ${fdt_addr}"
647
648#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
649
650#endif
651