LXR uboot/include/configs/ls1043a

   1/*
   2 * Copyright (C) 2015 Freescale Semiconductor
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#ifndef __LS1043A_COMMON_H
   8#define __LS1043A_COMMON_H
   9
  10#define CONFIG_REMAKE_ELF
  11#define CONFIG_FSL_LAYERSCAPE
  12#define CONFIG_LS1043A
  13#define CONFIG_MP
  14#define CONFIG_SYS_FSL_CLK
  15#define CONFIG_GICV2
  16
  17#include <asm/arch/config.h>
  18
  19/* Link Definitions */
  20#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  21
  22#define CONFIG_SUPPORT_RAW_INITRD
  23
  24#define CONFIG_SKIP_LOWLEVEL_INIT
  25#define CONFIG_BOARD_EARLY_INIT_F       1
  26
  27#define CONFIG_VERY_BIG_RAM
  28#define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
  29#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  30#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  31#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
  32
  33#define CPU_RELEASE_ADDR               secondary_boot_func
  34
  35/* Generic Timer Definitions */
  36#define COUNTER_FREQUENCY               25000000        /* 25MHz */
  37
  38/* Size of malloc() pool */
  39#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 1024 * 1024)
  40
  41/* Serial Port */
  42#define CONFIG_CONS_INDEX               1
  43#define CONFIG_SYS_NS16550_SERIAL
  44#define CONFIG_SYS_NS16550_REG_SIZE     1
  45#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0))
  46
  47#define CONFIG_BAUDRATE                 115200
  48#define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  49
  50/* SD boot SPL */
  51#ifdef CONFIG_SD_BOOT
  52#define CONFIG_SPL_FRAMEWORK
  53#define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
  54#define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  55#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0xf0
  56#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x500
  57
  58#define CONFIG_SPL_TEXT_BASE            0x10000000
  59#define CONFIG_SPL_MAX_SIZE             0x1d000
  60#define CONFIG_SPL_STACK                0x1001e000
  61#define CONFIG_SPL_PAD_TO               0x1d000
  62
  63#define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  64                                        CONFIG_SYS_MONITOR_LEN)
  65#define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  66#define CONFIG_SPL_BSS_START_ADDR       0x80100000
  67#define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  68#define CONFIG_SYS_MONITOR_LEN          0xa0000
  69#endif
  70
  71/* NAND SPL */
  72#ifdef CONFIG_NAND_BOOT
  73#define CONFIG_SPL_PBL_PAD
  74#define CONFIG_SPL_FRAMEWORK
  75#define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
  76#define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  77#define CONFIG_SPL_TEXT_BASE            0x10000000
  78#define CONFIG_SPL_MAX_SIZE             0x1a000
  79#define CONFIG_SPL_STACK                0x1001d000
  80#define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  81#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  82#define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  83#define CONFIG_SPL_BSS_START_ADDR       0x80100000
  84#define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  85#define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  86#define CONFIG_SYS_MONITOR_LEN          0xa0000
  87#endif
  88
  89/* IFC */
  90#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  91#define CONFIG_FSL_IFC
  92/*
  93 * CONFIG_SYS_FLASH_BASE has the final address (core view)
  94 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  95 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  96 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
  97 */
  98#define CONFIG_SYS_FLASH_BASE                   0x60000000
  99#define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
 100#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 101
 102#ifndef CONFIG_SYS_NO_FLASH
 103#define CONFIG_FLASH_CFI_DRIVER
 104#define CONFIG_SYS_FLASH_CFI
 105#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 106#define CONFIG_SYS_FLASH_QUIET_TEST
 107#define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 108#endif
 109#endif
 110
 111/* I2C */
 112#define CONFIG_SYS_I2C
 113#define CONFIG_SYS_I2C_MXC
 114#define CONFIG_SYS_I2C_MXC_I2C1
 115#define CONFIG_SYS_I2C_MXC_I2C2
 116#define CONFIG_SYS_I2C_MXC_I2C3
 117#define CONFIG_SYS_I2C_MXC_I2C4
 118
 119/* PCIe */
 120#define CONFIG_PCIE1            /* PCIE controller 1 */
 121#define CONFIG_PCIE2            /* PCIE controller 2 */
 122#define CONFIG_PCIE3            /* PCIE controller 3 */
 123#define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 124#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
 125
 126#define CONFIG_SYS_PCI_64BIT
 127
 128#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF   0x00000000
 129#define CONFIG_SYS_PCIE_CFG0_SIZE       0x00001000      /* 4k */
 130#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF   0x00001000
 131#define CONFIG_SYS_PCIE_CFG1_SIZE       0x00001000      /* 4k */
 132
 133#define CONFIG_SYS_PCIE_IO_BUS          0x00000000
 134#define CONFIG_SYS_PCIE_IO_PHYS_OFF     0x00010000
 135#define CONFIG_SYS_PCIE_IO_SIZE         0x00010000      /* 64k */
 136
 137#define CONFIG_SYS_PCIE_MEM_BUS         0x40000000
 138#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x40000000
 139#define CONFIG_SYS_PCIE_MEM_SIZE        0x40000000      /* 1G */
 140
 141#ifdef CONFIG_PCI
 142#define CONFIG_NET_MULTI
 143#define CONFIG_E1000
 144#define CONFIG_PCI_SCAN_SHOW
 145#define CONFIG_CMD_PCI
 146#endif
 147
 148/* Command line configuration */
 149#define CONFIG_CMD_ENV
 150#define CONFIG_MENU
 151#define CONFIG_CMD_PXE
 152
 153/*  MMC  */
 154#define CONFIG_MMC
 155#ifdef CONFIG_MMC
 156#define CONFIG_FSL_ESDHC
 157#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 158#define CONFIG_GENERIC_MMC
 159#define CONFIG_DOS_PARTITION
 160#endif
 161
 162/*  DSPI  */
 163#define CONFIG_FSL_DSPI
 164#ifdef CONFIG_FSL_DSPI
 165#define CONFIG_DM_SPI_FLASH
 166#define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
 167#define CONFIG_SPI_FLASH_SST            /* cs1 */
 168#define CONFIG_SPI_FLASH_EON            /* cs2 */
 169#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 170#define CONFIG_SF_DEFAULT_BUS           1
 171#define CONFIG_SF_DEFAULT_CS            0
 172#endif
 173#endif
 174
 175#define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
 176
 177/* FMan ucode */
 178#define CONFIG_SYS_DPAA_FMAN
 179#ifdef CONFIG_SYS_DPAA_FMAN
 180#define CONFIG_SYS_FM_MURAM_SIZE        0x60000
 181
 182#ifdef CONFIG_NAND_BOOT
 183/* Store Fman ucode at offeset 0x160000(11 blocks). */
 184#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 185#define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 186#elif defined(CONFIG_SD_BOOT)
 187/*
 188 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 189 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
 190 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
 191 */
 192#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 193#define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 194#elif defined(CONFIG_QSPI_BOOT)
 195#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 196#define CONFIG_SYS_FMAN_FW_ADDR         0x400d0000
 197#define CONFIG_ENV_SPI_BUS              0
 198#define CONFIG_ENV_SPI_CS               0
 199#define CONFIG_ENV_SPI_MAX_HZ           1000000
 200#define CONFIG_ENV_SPI_MODE             0x03
 201#else
 202#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 203/* FMan fireware Pre-load address */
 204#define CONFIG_SYS_FMAN_FW_ADDR         0x60300000
 205#endif
 206#define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 207#define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 208#endif
 209
 210/* Miscellaneous configurable options */
 211#define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 212#define CONFIG_ARCH_EARLY_INIT_R
 213#define CONFIG_BOARD_LATE_INIT
 214
 215#define CONFIG_HWCONFIG
 216#define HWCONFIG_BUFFER_SIZE            128
 217
 218#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 219#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
 220                        "5m(kernel),1m(dtb),9m(file_system)"
 221#else
 222#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
 223                        "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
 224                        "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
 225                        "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
 226                        "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
 227                        "40m(nor_bank4_fit);7e800000.flash:" \
 228                        "1m(nand_uboot),1m(nand_uboot_env)," \
 229                        "20m(nand_fit);spi0.0:1m(uboot)," \
 230                        "5m(kernel),1m(dtb),9m(file_system)"
 231#endif
 232
 233/* Initial environment variables */
 234#define CONFIG_EXTRA_ENV_SETTINGS               \
 235        "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 236        "loadaddr=0x80100000\0"                 \
 237        "fdt_high=0xffffffffffffffff\0"         \
 238        "initrd_high=0xffffffffffffffff\0"      \
 239        "kernel_start=0x61100000\0"             \
 240        "kernel_load=0xa0000000\0"              \
 241        "kernel_size=0x2800000\0"               \
 242        "console=ttyS0,115200\0"                \
 243        "mtdparts=" MTDPARTS_DEFAULT "\0"
 244
 245#define CONFIG_BOOTARGS                 "console=ttyS0,115200 root=/dev/ram0 " \
 246                                        "earlycon=uart8250,mmio,0x21c0500 "    \
 247                                        MTDPARTS_DEFAULT
 248
 249#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 250#define CONFIG_BOOTCOMMAND              "sf probe && sf read $kernel_load "    \
 251                                        "e0000 f00000 && bootm $kernel_load"
 252#else
 253#define CONFIG_BOOTCOMMAND              "cp.b $kernel_start $kernel_load "     \
 254                                        "$kernel_size && bootm $kernel_load"
 255#endif
 256
 257/* Monitor Command Prompt */
 258#define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 259#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 260                                        sizeof(CONFIG_SYS_PROMPT) + 16)
 261#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 262#define CONFIG_SYS_LONGHELP
 263#define CONFIG_CMDLINE_EDITING          1
 264#define CONFIG_AUTO_COMPLETE
 265#define CONFIG_SYS_MAXARGS              64      /* max command args */
 266
 267#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 268
 269/* Hash command with SHA acceleration supported in hardware */
 270#ifdef CONFIG_FSL_CAAM
 271#define CONFIG_CMD_HASH
 272#define CONFIG_SHA_HW_ACCEL
 273#endif
 274
 275#endif /* __LS1043A_COMMON_H */
 276