1/* 2 * Configuation settings for the Hitachi Solution Engine 7720 3 * 4 * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef __MS7720SE_H 10#define __MS7720SE_H 11 12#define CONFIG_CPU_SH7720 1 13#define CONFIG_MS7720SE 1 14 15#define CONFIG_CMD_SDRAM 16#define CONFIG_CMD_PCMCIA 17#define CONFIG_CMD_IDE 18 19#define CONFIG_BAUDRATE 115200 20#define CONFIG_BOOTARGS "console=ttySC0,115200" 21#define CONFIG_BOOTFILE "/boot/zImage" 22#define CONFIG_LOADADDR 0x8E000000 23 24#undef CONFIG_SHOW_BOOT_PROGRESS 25 26/* MEMORY */ 27#define MS7720SE_SDRAM_BASE 0x8C000000 28#define MS7720SE_FLASH_BASE_1 0xA0000000 29#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024) 30 31#define CONFIG_SYS_TEXT_BASE 0x8FFC0000 32#define CONFIG_SYS_LONGHELP /* undef to save memory */ 33#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ 34#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 35#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 36/* Buffer size for Boot Arguments passed to kernel */ 37#define CONFIG_SYS_BARGSIZE 512 38/* List of legal baudrate settings for this board */ 39#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 40 41/* SCIF */ 42#define CONFIG_SCIF_CONSOLE 1 43#define CONFIG_CONS_SCIF0 1 44 45#define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE 46#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 47 48#define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE 49#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 50 51#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 52#define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1 53#define CONFIG_SYS_MONITOR_LEN (128 * 1024) 54#define CONFIG_SYS_MALLOC_LEN (256 * 1024) 55#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 56 57/* FLASH */ 58#define CONFIG_SYS_FLASH_CFI 59#define CONFIG_FLASH_CFI_DRIVER 60#undef CONFIG_SYS_FLASH_QUIET_TEST 61#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 62 63#define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1 64 65#define CONFIG_SYS_MAX_FLASH_SECT 150 66#define CONFIG_SYS_MAX_FLASH_BANKS 1 67#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 68 69#define CONFIG_ENV_IS_IN_FLASH 70#define CONFIG_ENV_SECT_SIZE (64 * 1024) 71#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 72#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 73#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 74#define CONFIG_SYS_FLASH_WRITE_TOUT 500 75 76/* Board Clock */ 77#define CONFIG_SYS_CLK_FREQ 33333333 78#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 79#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 80#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */ 81 82/* PCMCIA */ 83#define CONFIG_IDE_PCMCIA 1 84#define CONFIG_MARUBUN_PCCARD 1 85#define CONFIG_PCMCIA_SLOT_A 1 86#define CONFIG_SYS_IDE_MAXDEVICE 1 87#define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0 88#define CONFIG_SYS_MARUBUN_MW1 0xb8400000 89#define CONFIG_SYS_MARUBUN_MW2 0xb8500000 90#define CONFIG_SYS_MARUBUN_IO 0xb8600000 91 92#define CONFIG_SYS_PIO_MODE 1 93#define CONFIG_SYS_IDE_MAXBUS 1 94#define CONFIG_DOS_PARTITION 1 95#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */ 96#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ 97#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ 98#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ 99#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ 100#define CONFIG_IDE_SWAP_IO 101 102#endif /* __MS7720SE_H */ 103