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11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14
15
16
17#define CONFIG_BOOKE 1
18#define CONFIG_E500 1
19#define CONFIG_MPC8572 1
20#define CONFIG_XPEDITE5370 1
21#define CONFIG_SYS_BOARD_NAME "XPedite5370"
22#define CONFIG_SYS_FORM_3U_VPX 1
23#define CONFIG_BOARD_EARLY_INIT_R
24
25#ifndef CONFIG_SYS_TEXT_BASE
26#define CONFIG_SYS_TEXT_BASE 0xfff80000
27#endif
28
29#define CONFIG_PCI_SCAN_SHOW 1
30#define CONFIG_PCIE1 1
31#define CONFIG_PCIE2 1
32#define CONFIG_FSL_PCI_INIT 1
33#define CONFIG_PCI_INDIRECT_BRIDGE 1
34#define CONFIG_SYS_PCI_64BIT 1
35#define CONFIG_FSL_PCIE_RESET 1
36#define CONFIG_FSL_LAW 1
37#define CONFIG_FSL_ELBC 1
38
39
40
41
42#define CONFIG_MP
43#define CONFIG_BPTR_VIRT_ADDR 0xee000000
44#define CONFIG_MPC8xxx_DISABLE_BPTR
45
46
47
48
49#define CONFIG_SYS_FSL_DDR2
50#undef CONFIG_FSL_DDR_INTERACTIVE
51#define CONFIG_SPD_EEPROM
52#define CONFIG_DDR_SPD
53#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
54#define SPD_EEPROM_ADDRESS1 0x54
55#define SPD_EEPROM_ADDRESS2 0x54
56#define SPD_EEPROM_OFFSET 0x200
57#define CONFIG_NUM_DDR_CONTROLLERS 2
58#define CONFIG_DIMM_SLOTS_PER_CTLR 1
59#define CONFIG_CHIP_SELECTS_PER_CTRL 1
60#define CONFIG_DDR_ECC
61#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
62#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
63#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
64#define CONFIG_VERY_BIG_RAM
65
66#ifndef __ASSEMBLY__
67extern unsigned long get_board_sys_clk(unsigned long dummy);
68extern unsigned long get_board_ddr_clk(unsigned long dummy);
69#endif
70
71#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
72#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
73
74
75
76
77#define CONFIG_L2_CACHE
78#define CONFIG_BTB
79#define CONFIG_ENABLE_36BIT_PHYS 1
80
81#define CONFIG_SYS_CCSRBAR 0xef000000
82#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
83
84
85
86
87#define CONFIG_SYS_ALT_MEMTEST
88#define CONFIG_SYS_MEMTEST_START 0x10000000
89#define CONFIG_SYS_MEMTEST_END 0x20000000
90#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
91 CONFIG_SYS_POST_I2C)
92#define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
93 CONFIG_SYS_I2C_DS4510_ADDR, \
94 CONFIG_SYS_I2C_EEPROM_ADDR, \
95 CONFIG_SYS_I2C_LM90_ADDR, \
96 CONFIG_SYS_I2C_PCA953X_ADDR0, \
97 CONFIG_SYS_I2C_PCA953X_ADDR1, \
98 CONFIG_SYS_I2C_PCA953X_ADDR2, \
99 CONFIG_SYS_I2C_PCA953X_ADDR3, \
100 CONFIG_SYS_I2C_PEX8518_ADDR, \
101 CONFIG_SYS_I2C_RTC_ADDR}
102
103#define I2C_ADDR_IGNORE_LIST {0x50}
104
105
106
107
108
109
110
111
112
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114
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116
117
118
119
120#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
121
122
123
124
125#define CONFIG_SYS_NAND_BASE 0xef800000
126#define CONFIG_SYS_NAND_BASE2 0xef840000
127#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
128 CONFIG_SYS_NAND_BASE2}
129#define CONFIG_SYS_MAX_NAND_DEVICE 2
130#define CONFIG_NAND_FSL_ELBC
131
132
133
134
135#define CONFIG_SYS_FLASH_BASE 0xf8000000
136#define CONFIG_SYS_FLASH_BASE2 0xf0000000
137#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
138#define CONFIG_SYS_MAX_FLASH_BANKS 2
139#define CONFIG_SYS_MAX_FLASH_SECT 1024
140#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
141#define CONFIG_SYS_FLASH_WRITE_TOUT 500
142#define CONFIG_FLASH_CFI_DRIVER
143#define CONFIG_SYS_FLASH_CFI
144#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
145#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
146 {0xf7f40000, 0xc0000} }
147#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
148
149
150
151
152
153#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
154 BR_PS_16 | \
155 BR_V)
156#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
157 OR_GPCM_CSNT | \
158 OR_GPCM_XACS | \
159 OR_GPCM_ACS_DIV2 | \
160 OR_GPCM_SCY_8 | \
161 OR_GPCM_TRLX | \
162 OR_GPCM_EHTR | \
163 OR_GPCM_EAD)
164
165
166#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
167 BR_PS_16 | \
168 BR_V)
169#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
170
171
172#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
173 (2<<BR_DECC_SHIFT) | \
174 BR_PS_8 | \
175 BR_MS_FCM | \
176 BR_V)
177
178
179#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
180 OR_FCM_PGS | \
181 OR_FCM_CSCT | \
182 OR_FCM_CST | \
183 OR_FCM_CHT | \
184 OR_FCM_SCY_1 | \
185 OR_FCM_TRLX | \
186 OR_FCM_EHTR)
187
188
189#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
190 (2<<BR_DECC_SHIFT) | \
191 BR_PS_8 | \
192 BR_MS_FCM | \
193 BR_V)
194#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
195
196
197
198
199#define CONFIG_SYS_INIT_RAM_LOCK 1
200#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
201#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
202
203#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
204#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
205
206#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
207#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
208
209
210
211
212#define CONFIG_CONS_INDEX 1
213#define CONFIG_SYS_NS16550_SERIAL
214#define CONFIG_SYS_NS16550_REG_SIZE 1
215#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
216#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
217#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
218#define CONFIG_SYS_BAUDRATE_TABLE \
219 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
220#define CONFIG_BAUDRATE 115200
221#define CONFIG_LOADS_ECHO 1
222#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
223
224
225
226
227#define CONFIG_SYS_I2C
228#define CONFIG_SYS_I2C_FSL
229#define CONFIG_SYS_FSL_I2C_SPEED 400000
230#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
231#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
232#define CONFIG_SYS_FSL_I2C2_SPEED 400000
233#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
234#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
235#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
236
237
238#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
239
240
241#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
242#define CONFIG_DTT_DS1621
243#define CONFIG_DTT_SENSORS { 0 }
244#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
245
246
247#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
248#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
249#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
250#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
251
252
253#define CONFIG_RTC_M41T11 1
254#define CONFIG_SYS_I2C_RTC_ADDR 0x68
255#define CONFIG_SYS_M41T11_BASE_YEAR 2000
256
257
258#define CONFIG_DS4510
259#define CONFIG_SYS_I2C_DS4510_ADDR 0x51
260
261
262#define CONFIG_PCA953X
263#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
264#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
265#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
266#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
267#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
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273
274#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01
275#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02
276#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04
277#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08
278#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10
279#define CONFIG_SYS_PCA953X_NVM_WP 0x20
280#define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40
281#define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80
282
283
284#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01
285#define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02
286#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04
287#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08
288#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10
289#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20
290#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40
291#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80
292
293
294#define CONFIG_SYS_PCA953X_P0_GA0 0x01
295#define CONFIG_SYS_PCA953X_P0_GA1 0x02
296#define CONFIG_SYS_PCA953X_P0_GA2 0x04
297#define CONFIG_SYS_PCA953X_P0_GA3 0x08
298#define CONFIG_SYS_PCA953X_P0_GA4 0x10
299#define CONFIG_SYS_PCA953X_P0_GAP 0x20
300#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80
301
302
303#define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01
304#define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02
305#define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04
306#define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08
307#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10
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309
310
311
312
313
314#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
315#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
316#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000
317#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
318#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
319#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
320
321
322#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
323#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
324#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
325#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
326#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
327#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
328
329
330
331
332#define CONFIG_TSEC_ENET
333#define CONFIG_PHY_GIGE 1
334#define CONFIG_TSEC_TBI
335#define CONFIG_MII 1
336#define CONFIG_MII_DEFAULT_TSEC 1
337#define CONFIG_ETHPRIME "eTSEC2"
338
339
340
341
342
343#define CONFIG_TSEC_TBICR_SETTINGS ( \
344 TBICR_PHY_RESET \
345 | TBICR_FULL_DUPLEX \
346 | TBICR_SPEED1_SET \
347 )
348
349#define CONFIG_TSEC1 1
350#define CONFIG_TSEC1_NAME "eTSEC1"
351#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
352#define TSEC1_PHY_ADDR 1
353#define TSEC1_PHYIDX 0
354#define CONFIG_HAS_ETH0
355
356#define CONFIG_TSEC2 1
357#define CONFIG_TSEC2_NAME "eTSEC2"
358#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
359#define TSEC2_PHY_ADDR 2
360#define TSEC2_PHYIDX 0
361#define CONFIG_HAS_ETH1
362
363
364
365
366#define CONFIG_CMD_DATE
367#define CONFIG_CMD_DS4510
368#define CONFIG_CMD_DS4510_INFO
369#define CONFIG_CMD_DTT
370#define CONFIG_CMD_EEPROM
371#define CONFIG_CMD_JFFS2
372#define CONFIG_CMD_NAND
373#define CONFIG_CMD_PCA953X
374#define CONFIG_CMD_PCA953X_INFO
375#define CONFIG_CMD_PCI
376#define CONFIG_CMD_PCI_ENUM
377#define CONFIG_CMD_REGINFO
378
379
380
381
382#define CONFIG_SYS_LONGHELP
383#define CONFIG_SYS_LOAD_ADDR 0x2000000
384#define CONFIG_SYS_CBSIZE 256
385#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
386#define CONFIG_SYS_MAXARGS 16
387#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
388#define CONFIG_CMDLINE_EDITING 1
389#define CONFIG_AUTO_COMPLETE 1
390#define CONFIG_LOADADDR 0x1000000
391#define CONFIG_PANIC_HANG
392#define CONFIG_PREBOOT
393#define CONFIG_INTEGRITY
394
395
396
397
398
399
400#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
401#define CONFIG_SYS_BOOTM_LEN (16 << 20)
402
403
404
405
406#define CONFIG_ENV_IS_IN_FLASH 1
407#define CONFIG_ENV_SECT_SIZE 0x20000
408#define CONFIG_ENV_SIZE 0x8000
409#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
410
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421
422
423
424
425#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
426#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
427#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
428#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
429#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
430#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
431
432#define CONFIG_PROG_UBOOT1 \
433 "$download_cmd $loadaddr $ubootfile; " \
434 "if test $? -eq 0; then " \
435 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
436 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
437 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
438 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
439 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
440 "if test $? -ne 0; then " \
441 "echo PROGRAM FAILED; " \
442 "else; " \
443 "echo PROGRAM SUCCEEDED; " \
444 "fi; " \
445 "else; " \
446 "echo DOWNLOAD FAILED; " \
447 "fi;"
448
449#define CONFIG_PROG_UBOOT2 \
450 "$download_cmd $loadaddr $ubootfile; " \
451 "if test $? -eq 0; then " \
452 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
453 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
454 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
455 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
456 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
457 "if test $? -ne 0; then " \
458 "echo PROGRAM FAILED; " \
459 "else; " \
460 "echo PROGRAM SUCCEEDED; " \
461 "fi; " \
462 "else; " \
463 "echo DOWNLOAD FAILED; " \
464 "fi;"
465
466#define CONFIG_BOOT_OS_NET \
467 "$download_cmd $osaddr $osfile; " \
468 "if test $? -eq 0; then " \
469 "if test -n $fdtaddr; then " \
470 "$download_cmd $fdtaddr $fdtfile; " \
471 "if test $? -eq 0; then " \
472 "bootm $osaddr - $fdtaddr; " \
473 "else; " \
474 "echo FDT DOWNLOAD FAILED; " \
475 "fi; " \
476 "else; " \
477 "bootm $osaddr; " \
478 "fi; " \
479 "else; " \
480 "echo OS DOWNLOAD FAILED; " \
481 "fi;"
482
483#define CONFIG_PROG_OS1 \
484 "$download_cmd $osaddr $osfile; " \
485 "if test $? -eq 0; then " \
486 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
487 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
488 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
489 "if test $? -ne 0; then " \
490 "echo OS PROGRAM FAILED; " \
491 "else; " \
492 "echo OS PROGRAM SUCCEEDED; " \
493 "fi; " \
494 "else; " \
495 "echo OS DOWNLOAD FAILED; " \
496 "fi;"
497
498#define CONFIG_PROG_OS2 \
499 "$download_cmd $osaddr $osfile; " \
500 "if test $? -eq 0; then " \
501 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
502 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
503 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
504 "if test $? -ne 0; then " \
505 "echo OS PROGRAM FAILED; " \
506 "else; " \
507 "echo OS PROGRAM SUCCEEDED; " \
508 "fi; " \
509 "else; " \
510 "echo OS DOWNLOAD FAILED; " \
511 "fi;"
512
513#define CONFIG_PROG_FDT1 \
514 "$download_cmd $fdtaddr $fdtfile; " \
515 "if test $? -eq 0; then " \
516 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
517 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
518 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
519 "if test $? -ne 0; then " \
520 "echo FDT PROGRAM FAILED; " \
521 "else; " \
522 "echo FDT PROGRAM SUCCEEDED; " \
523 "fi; " \
524 "else; " \
525 "echo FDT DOWNLOAD FAILED; " \
526 "fi;"
527
528#define CONFIG_PROG_FDT2 \
529 "$download_cmd $fdtaddr $fdtfile; " \
530 "if test $? -eq 0; then " \
531 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
532 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
533 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
534 "if test $? -ne 0; then " \
535 "echo FDT PROGRAM FAILED; " \
536 "else; " \
537 "echo FDT PROGRAM SUCCEEDED; " \
538 "fi; " \
539 "else; " \
540 "echo FDT DOWNLOAD FAILED; " \
541 "fi;"
542
543#define CONFIG_EXTRA_ENV_SETTINGS \
544 "autoload=yes\0" \
545 "download_cmd=tftp\0" \
546 "console_args=console=ttyS0,115200\0" \
547 "root_args=root=/dev/nfs rw\0" \
548 "misc_args=ip=on\0" \
549 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
550 "bootfile=/home/user/file\0" \
551 "osfile=/home/user/board.uImage\0" \
552 "fdtfile=/home/user/board.dtb\0" \
553 "ubootfile=/home/user/u-boot.bin\0" \
554 "fdtaddr=0x1e00000\0" \
555 "osaddr=0x1000000\0" \
556 "loadaddr=0x1000000\0" \
557 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
558 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
559 "prog_os1="CONFIG_PROG_OS1"\0" \
560 "prog_os2="CONFIG_PROG_OS2"\0" \
561 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
562 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
563 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
564 "bootcmd_flash1=run set_bootargs; " \
565 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
566 "bootcmd_flash2=run set_bootargs; " \
567 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
568 "bootcmd=run bootcmd_flash1\0"
569#endif
570