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16#ifndef __LINUX_MTD_NAND_H
17#define __LINUX_MTD_NAND_H
18
19#include <config.h>
20
21#include <linux/compat.h>
22#include <linux/mtd/mtd.h>
23#include <linux/mtd/flashchip.h>
24#include <linux/mtd/bbm.h>
25
26struct mtd_info;
27struct nand_flash_dev;
28struct device_node;
29
30
31extern int nand_scan(struct mtd_info *mtd, int max_chips);
32
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34
35
36extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
37 struct nand_flash_dev *table);
38extern int nand_scan_tail(struct mtd_info *mtd);
39
40
41extern void nand_release(struct mtd_info *mtd);
42
43
44extern void nand_wait_ready(struct mtd_info *mtd);
45
46
47
48
49
50
51#define NAND_MAX_OOBSIZE 1664
52#define NAND_MAX_PAGESIZE 16384
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59
60
61#define NAND_NCE 0x01
62
63#define NAND_CLE 0x02
64
65#define NAND_ALE 0x04
66
67#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
68#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
69#define NAND_CTRL_CHANGE 0x80
70
71
72
73
74#define NAND_CMD_READ0 0
75#define NAND_CMD_READ1 1
76#define NAND_CMD_RNDOUT 5
77#define NAND_CMD_PAGEPROG 0x10
78#define NAND_CMD_READOOB 0x50
79#define NAND_CMD_ERASE1 0x60
80#define NAND_CMD_STATUS 0x70
81#define NAND_CMD_SEQIN 0x80
82#define NAND_CMD_RNDIN 0x85
83#define NAND_CMD_READID 0x90
84#define NAND_CMD_ERASE2 0xd0
85#define NAND_CMD_PARAM 0xec
86#define NAND_CMD_GET_FEATURES 0xee
87#define NAND_CMD_SET_FEATURES 0xef
88#define NAND_CMD_RESET 0xff
89
90#define NAND_CMD_LOCK 0x2a
91#define NAND_CMD_UNLOCK1 0x23
92#define NAND_CMD_UNLOCK2 0x24
93
94
95#define NAND_CMD_READSTART 0x30
96#define NAND_CMD_RNDOUTSTART 0xE0
97#define NAND_CMD_CACHEDPROG 0x15
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105
106#define NAND_CMD_DEPLETE1 0x100
107#define NAND_CMD_DEPLETE2 0x38
108#define NAND_CMD_STATUS_MULTI 0x71
109#define NAND_CMD_STATUS_ERROR 0x72
110
111#define NAND_CMD_STATUS_ERROR0 0x73
112#define NAND_CMD_STATUS_ERROR1 0x74
113#define NAND_CMD_STATUS_ERROR2 0x75
114#define NAND_CMD_STATUS_ERROR3 0x76
115#define NAND_CMD_STATUS_RESET 0x7f
116#define NAND_CMD_STATUS_CLEAR 0xff
117
118#define NAND_CMD_NONE -1
119
120
121#define NAND_STATUS_FAIL 0x01
122#define NAND_STATUS_FAIL_N1 0x02
123#define NAND_STATUS_TRUE_READY 0x20
124#define NAND_STATUS_READY 0x40
125#define NAND_STATUS_WP 0x80
126
127
128
129
130typedef enum {
131 NAND_ECC_NONE,
132 NAND_ECC_SOFT,
133 NAND_ECC_HW,
134 NAND_ECC_HW_SYNDROME,
135 NAND_ECC_HW_OOB_FIRST,
136 NAND_ECC_SOFT_BCH,
137} nand_ecc_modes_t;
138
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142
143#define NAND_ECC_READ 0
144
145#define NAND_ECC_WRITE 1
146
147#define NAND_ECC_READSYN 2
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154
155#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
156
157
158#define NAND_GET_DEVICE 0x80
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165
166#define NAND_BUSWIDTH_16 0x00000002
167
168#define NAND_NO_PADDING 0x00000004
169
170#define NAND_CACHEPRG 0x00000008
171
172#define NAND_COPYBACK 0x00000010
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177
178#define NAND_NEED_READRDY 0x00000100
179
180
181#define NAND_NO_SUBPAGE_WRITE 0x00000200
182
183
184#define NAND_BROKEN_XD 0x00000400
185
186
187#define NAND_ROM 0x00000800
188
189
190#define NAND_SUBPAGE_READ 0x00001000
191
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194
195
196#define NAND_NEED_SCRAMBLING 0x00002000
197
198
199#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
200
201
202#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
203#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
204
205
206
207#define NAND_SKIP_BBTSCAN 0x00010000
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211
212#define NAND_OWN_BUFFERS 0x00020000
213
214#define NAND_SCAN_SILENT_NODEV 0x00040000
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220
221#define NAND_BUSWIDTH_AUTO 0x00080000
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225
226#define NAND_USE_BOUNCE_BUFFER 0x00100000
227
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229
230#define NAND_BBT_SCANNED 0x40000000
231
232#define NAND_CONTROLLER_ALLOC 0x80000000
233
234
235#define NAND_CI_CHIPNR_MSK 0x03
236#define NAND_CI_CELLTYPE_MSK 0x0C
237#define NAND_CI_CELLTYPE_SHIFT 2
238
239
240struct nand_chip;
241
242
243#define ONFI_FEATURE_16_BIT_BUS (1 << 0)
244#define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
245
246
247#define ONFI_TIMING_MODE_0 (1 << 0)
248#define ONFI_TIMING_MODE_1 (1 << 1)
249#define ONFI_TIMING_MODE_2 (1 << 2)
250#define ONFI_TIMING_MODE_3 (1 << 3)
251#define ONFI_TIMING_MODE_4 (1 << 4)
252#define ONFI_TIMING_MODE_5 (1 << 5)
253#define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
254
255
256#define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
257
258
259#define ONFI_FEATURE_ADDR_READ_RETRY 0x89
260
261
262#define ONFI_SUBFEATURE_PARAM_LEN 4
263
264
265#define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
266
267struct nand_onfi_params {
268
269
270 u8 sig[4];
271 __le16 revision;
272 __le16 features;
273 __le16 opt_cmd;
274 u8 reserved0[2];
275 __le16 ext_param_page_length;
276 u8 num_of_param_pages;
277 u8 reserved1[17];
278
279
280 char manufacturer[12];
281 char model[20];
282 u8 jedec_id;
283 __le16 date_code;
284 u8 reserved2[13];
285
286
287 __le32 byte_per_page;
288 __le16 spare_bytes_per_page;
289 __le32 data_bytes_per_ppage;
290 __le16 spare_bytes_per_ppage;
291 __le32 pages_per_block;
292 __le32 blocks_per_lun;
293 u8 lun_count;
294 u8 addr_cycles;
295 u8 bits_per_cell;
296 __le16 bb_per_lun;
297 __le16 block_endurance;
298 u8 guaranteed_good_blocks;
299 __le16 guaranteed_block_endurance;
300 u8 programs_per_page;
301 u8 ppage_attr;
302 u8 ecc_bits;
303 u8 interleaved_bits;
304 u8 interleaved_ops;
305 u8 reserved3[13];
306
307
308 u8 io_pin_capacitance_max;
309 __le16 async_timing_mode;
310 __le16 program_cache_timing_mode;
311 __le16 t_prog;
312 __le16 t_bers;
313 __le16 t_r;
314 __le16 t_ccs;
315 __le16 src_sync_timing_mode;
316 u8 src_ssync_features;
317 __le16 clk_pin_capacitance_typ;
318 __le16 io_pin_capacitance_typ;
319 __le16 input_pin_capacitance_typ;
320 u8 input_pin_capacitance_max;
321 u8 driver_strength_support;
322 __le16 t_int_r;
323 __le16 t_adl;
324 u8 reserved4[8];
325
326
327 __le16 vendor_revision;
328 u8 vendor[88];
329
330 __le16 crc;
331} __packed;
332
333#define ONFI_CRC_BASE 0x4F4E
334
335
336struct onfi_ext_ecc_info {
337 u8 ecc_bits;
338 u8 codeword_size;
339 __le16 bb_per_lun;
340 __le16 block_endurance;
341 u8 reserved[2];
342} __packed;
343
344#define ONFI_SECTION_TYPE_0 0
345#define ONFI_SECTION_TYPE_1 1
346#define ONFI_SECTION_TYPE_2 2
347struct onfi_ext_section {
348 u8 type;
349 u8 length;
350} __packed;
351
352#define ONFI_EXT_SECTION_MAX 8
353
354
355struct onfi_ext_param_page {
356 __le16 crc;
357 u8 sig[4];
358 u8 reserved0[10];
359 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
360
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366
367} __packed;
368
369struct nand_onfi_vendor_micron {
370 u8 two_plane_read;
371 u8 read_cache;
372 u8 read_unique_id;
373 u8 dq_imped;
374 u8 dq_imped_num_settings;
375 u8 dq_imped_feat_addr;
376 u8 rb_pulldown_strength;
377 u8 rb_pulldown_strength_feat_addr;
378 u8 rb_pulldown_strength_num_settings;
379 u8 otp_mode;
380 u8 otp_page_start;
381 u8 otp_data_prot_addr;
382 u8 otp_num_pages;
383 u8 otp_feat_addr;
384 u8 read_retry_options;
385 u8 reserved[72];
386 u8 param_revision;
387} __packed;
388
389struct jedec_ecc_info {
390 u8 ecc_bits;
391 u8 codeword_size;
392 __le16 bb_per_lun;
393 __le16 block_endurance;
394 u8 reserved[2];
395} __packed;
396
397
398#define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
399
400struct nand_jedec_params {
401
402
403 u8 sig[4];
404 __le16 revision;
405 __le16 features;
406 u8 opt_cmd[3];
407 __le16 sec_cmd;
408 u8 num_of_param_pages;
409 u8 reserved0[18];
410
411
412 char manufacturer[12];
413 char model[20];
414 u8 jedec_id[6];
415 u8 reserved1[10];
416
417
418 __le32 byte_per_page;
419 __le16 spare_bytes_per_page;
420 u8 reserved2[6];
421 __le32 pages_per_block;
422 __le32 blocks_per_lun;
423 u8 lun_count;
424 u8 addr_cycles;
425 u8 bits_per_cell;
426 u8 programs_per_page;
427 u8 multi_plane_addr;
428 u8 multi_plane_op_attr;
429 u8 reserved3[38];
430
431
432 __le16 async_sdr_speed_grade;
433 __le16 toggle_ddr_speed_grade;
434 __le16 sync_ddr_speed_grade;
435 u8 async_sdr_features;
436 u8 toggle_ddr_features;
437 u8 sync_ddr_features;
438 __le16 t_prog;
439 __le16 t_bers;
440 __le16 t_r;
441 __le16 t_r_multi_plane;
442 __le16 t_ccs;
443 __le16 io_pin_capacitance_typ;
444 __le16 input_pin_capacitance_typ;
445 __le16 clk_pin_capacitance_typ;
446 u8 driver_strength_support;
447 __le16 t_adl;
448 u8 reserved4[36];
449
450
451 u8 guaranteed_good_blocks;
452 __le16 guaranteed_block_endurance;
453 struct jedec_ecc_info ecc_info[4];
454 u8 reserved5[29];
455
456
457 u8 reserved6[148];
458
459
460 __le16 vendor_rev_num;
461 u8 reserved7[88];
462
463
464 __le16 crc;
465} __packed;
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474
475struct nand_hw_control {
476 spinlock_t lock;
477 struct nand_chip *active;
478};
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531struct nand_ecc_ctrl {
532 nand_ecc_modes_t mode;
533 int steps;
534 int size;
535 int bytes;
536 int total;
537 int strength;
538 int prepad;
539 int postpad;
540 unsigned int options;
541 struct nand_ecclayout *layout;
542 void *priv;
543 void (*hwctl)(struct mtd_info *mtd, int mode);
544 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
545 uint8_t *ecc_code);
546 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
547 uint8_t *calc_ecc);
548 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
549 uint8_t *buf, int oob_required, int page);
550 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
551 const uint8_t *buf, int oob_required, int page);
552 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
553 uint8_t *buf, int oob_required, int page);
554 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
555 uint32_t offs, uint32_t len, uint8_t *buf, int page);
556 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
557 uint32_t offset, uint32_t data_len,
558 const uint8_t *data_buf, int oob_required, int page);
559 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
560 const uint8_t *buf, int oob_required, int page);
561 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
562 int page);
563 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
564 int page);
565 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
566 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
567 int page);
568};
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578
579struct nand_buffers {
580 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
581 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
582 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
583 ARCH_DMA_MINALIGN)];
584};
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688struct nand_chip {
689 struct mtd_info mtd;
690 void __iomem *IO_ADDR_R;
691 void __iomem *IO_ADDR_W;
692
693 int flash_node;
694
695 uint8_t (*read_byte)(struct mtd_info *mtd);
696 u16 (*read_word)(struct mtd_info *mtd);
697 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
698 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
699 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
700 void (*select_chip)(struct mtd_info *mtd, int chip);
701 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
702 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
703 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
704 int (*dev_ready)(struct mtd_info *mtd);
705 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
706 int page_addr);
707 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
708 int (*erase)(struct mtd_info *mtd, int page);
709 int (*scan_bbt)(struct mtd_info *mtd);
710 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
711 int status, int page);
712 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
713 uint32_t offset, int data_len, const uint8_t *buf,
714 int oob_required, int page, int cached, int raw);
715 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
716 int feature_addr, uint8_t *subfeature_para);
717 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
718 int feature_addr, uint8_t *subfeature_para);
719 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
720
721 int chip_delay;
722 unsigned int options;
723 unsigned int bbt_options;
724
725 int page_shift;
726 int phys_erase_shift;
727 int bbt_erase_shift;
728 int chip_shift;
729 int numchips;
730 uint64_t chipsize;
731 int pagemask;
732 int pagebuf;
733 unsigned int pagebuf_bitflips;
734 int subpagesize;
735 uint8_t bits_per_cell;
736 uint16_t ecc_strength_ds;
737 uint16_t ecc_step_ds;
738 int onfi_timing_mode_default;
739 int badblockpos;
740 int badblockbits;
741
742 int onfi_version;
743 int jedec_version;
744#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
745 struct nand_onfi_params onfi_params;
746#endif
747 struct nand_jedec_params jedec_params;
748
749 int read_retries;
750
751 flstate_t state;
752
753 uint8_t *oob_poi;
754 struct nand_hw_control *controller;
755 struct nand_ecclayout *ecclayout;
756
757 struct nand_ecc_ctrl ecc;
758 struct nand_buffers *buffers;
759 struct nand_hw_control hwcontrol;
760
761 uint8_t *bbt;
762 struct nand_bbt_descr *bbt_td;
763 struct nand_bbt_descr *bbt_md;
764
765 struct nand_bbt_descr *badblock_pattern;
766
767 void *priv;
768};
769
770static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
771{
772 return container_of(mtd, struct nand_chip, mtd);
773}
774
775static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
776{
777 return &chip->mtd;
778}
779
780static inline void *nand_get_controller_data(struct nand_chip *chip)
781{
782 return chip->priv;
783}
784
785static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
786{
787 chip->priv = priv;
788}
789
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792
793#define NAND_MFR_TOSHIBA 0x98
794#define NAND_MFR_SAMSUNG 0xec
795#define NAND_MFR_FUJITSU 0x04
796#define NAND_MFR_NATIONAL 0x8f
797#define NAND_MFR_RENESAS 0x07
798#define NAND_MFR_STMICRO 0x20
799#define NAND_MFR_HYNIX 0xad
800#define NAND_MFR_MICRON 0x2c
801#define NAND_MFR_AMD 0x01
802#define NAND_MFR_MACRONIX 0xc2
803#define NAND_MFR_EON 0x92
804#define NAND_MFR_SANDISK 0x45
805#define NAND_MFR_INTEL 0x89
806#define NAND_MFR_ATO 0x9b
807
808
809#define NAND_MAX_ID_LEN 8
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815
816#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
817 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
818 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
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830#define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
831 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
832 .options = (opts) }
833
834#define NAND_ECC_INFO(_strength, _step) \
835 { .strength_ds = (_strength), .step_ds = (_step) }
836#define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
837#define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
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868struct nand_flash_dev {
869 char *name;
870 union {
871 struct {
872 uint8_t mfr_id;
873 uint8_t dev_id;
874 };
875 uint8_t id[NAND_MAX_ID_LEN];
876 };
877 unsigned int pagesize;
878 unsigned int chipsize;
879 unsigned int erasesize;
880 unsigned int options;
881 uint16_t id_len;
882 uint16_t oobsize;
883 struct {
884 uint16_t strength_ds;
885 uint16_t step_ds;
886 } ecc;
887 int onfi_timing_mode_default;
888};
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894
895struct nand_manufacturers {
896 int id;
897 char *name;
898};
899
900extern struct nand_flash_dev nand_flash_ids[];
901extern struct nand_manufacturers nand_manuf_ids[];
902
903extern int nand_default_bbt(struct mtd_info *mtd);
904extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
905extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
906extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
907extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
908 int allowbbt);
909extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
910 size_t *retlen, uint8_t *buf);
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914
915#define NAND_SMALL_BADBLOCK_POS 5
916#define NAND_LARGE_BADBLOCK_POS 0
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929struct platform_nand_chip {
930 int nr_chips;
931 int chip_offset;
932 int nr_partitions;
933 struct mtd_partition *partitions;
934 int chip_delay;
935 unsigned int options;
936 unsigned int bbt_options;
937 const char **part_probe_types;
938};
939
940
941struct platform_device;
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959struct platform_nand_ctrl {
960 int (*probe)(struct platform_device *pdev);
961 void (*remove)(struct platform_device *pdev);
962 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
963 int (*dev_ready)(struct mtd_info *mtd);
964 void (*select_chip)(struct mtd_info *mtd, int chip);
965 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
966 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
967 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
968 unsigned char (*read_byte)(struct mtd_info *mtd);
969 void *priv;
970};
971
972
973
974
975
976
977struct platform_nand_data {
978 struct platform_nand_chip chip;
979 struct platform_nand_ctrl ctrl;
980};
981
982#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
983
984static inline int onfi_feature(struct nand_chip *chip)
985{
986 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
987}
988
989
990static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
991{
992 if (!chip->onfi_version)
993 return ONFI_TIMING_MODE_UNKNOWN;
994 return le16_to_cpu(chip->onfi_params.async_timing_mode);
995}
996
997
998static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
999{
1000 if (!chip->onfi_version)
1001 return ONFI_TIMING_MODE_UNKNOWN;
1002 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1003}
1004#endif
1005
1006
1007
1008
1009
1010
1011static inline bool nand_is_slc(struct nand_chip *chip)
1012{
1013 return chip->bits_per_cell == 1;
1014}
1015
1016
1017
1018
1019
1020static inline int nand_opcode_8bits(unsigned int command)
1021{
1022 switch (command) {
1023 case NAND_CMD_READID:
1024 case NAND_CMD_PARAM:
1025 case NAND_CMD_GET_FEATURES:
1026 case NAND_CMD_SET_FEATURES:
1027 return 1;
1028 default:
1029 break;
1030 }
1031 return 0;
1032}
1033
1034
1035static inline int jedec_feature(struct nand_chip *chip)
1036{
1037 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1038 : 0;
1039}
1040
1041
1042void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
1043void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
1044void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
1045void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
1046uint8_t nand_read_byte(struct mtd_info *mtd);
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060struct nand_sdr_timings {
1061 u32 tALH_min;
1062 u32 tADL_min;
1063 u32 tALS_min;
1064 u32 tAR_min;
1065 u32 tCEA_max;
1066 u32 tCEH_min;
1067 u32 tCH_min;
1068 u32 tCHZ_max;
1069 u32 tCLH_min;
1070 u32 tCLR_min;
1071 u32 tCLS_min;
1072 u32 tCOH_min;
1073 u32 tCS_min;
1074 u32 tDH_min;
1075 u32 tDS_min;
1076 u32 tFEAT_max;
1077 u32 tIR_min;
1078 u32 tITC_max;
1079 u32 tRC_min;
1080 u32 tREA_max;
1081 u32 tREH_min;
1082 u32 tRHOH_min;
1083 u32 tRHW_min;
1084 u32 tRHZ_max;
1085 u32 tRLOH_min;
1086 u32 tRP_min;
1087 u32 tRR_min;
1088 u64 tRST_max;
1089 u32 tWB_max;
1090 u32 tWC_min;
1091 u32 tWH_min;
1092 u32 tWHR_min;
1093 u32 tWP_min;
1094 u32 tWW_min;
1095};
1096
1097
1098const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1099
1100int nand_check_erased_ecc_chunk(void *data, int datalen,
1101 void *ecc, int ecclen,
1102 void *extraoob, int extraooblen,
1103 int threshold);
1104#endif
1105