1/* 2 * Freescale i.MX28 USB OTG Register Definitions 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10#ifndef __REGS_USB_H__ 11#define __REGS_USB_H__ 12 13struct mxs_usb_regs { 14 uint32_t hw_usbctrl_id; /* 0x000 */ 15 uint32_t hw_usbctrl_hwgeneral; /* 0x004 */ 16 uint32_t hw_usbctrl_hwhost; /* 0x008 */ 17 uint32_t hw_usbctrl_hwdevice; /* 0x00c */ 18 uint32_t hw_usbctrl_hwtxbuf; /* 0x010 */ 19 uint32_t hw_usbctrl_hwrxbuf; /* 0x014 */ 20 21 uint32_t reserved1[26]; 22 23 uint32_t hw_usbctrl_gptimer0ld; /* 0x080 */ 24 uint32_t hw_usbctrl_gptimer0ctrl; /* 0x084 */ 25 uint32_t hw_usbctrl_gptimer1ld; /* 0x088 */ 26 uint32_t hw_usbctrl_gptimer1ctrl; /* 0x08c */ 27 uint32_t hw_usbctrl_sbuscfg; /* 0x090 */ 28 29 uint32_t reserved2[27]; 30 31 uint32_t hw_usbctrl_caplength; /* 0x100 */ 32 uint32_t hw_usbctrl_hcsparams; /* 0x104 */ 33 uint32_t hw_usbctrl_hccparams; /* 0x108 */ 34 35 uint32_t reserved3[5]; 36 37 uint32_t hw_usbctrl_dciversion; /* 0x120 */ 38 uint32_t hw_usbctrl_dccparams; /* 0x124 */ 39 40 uint32_t reserved4[6]; 41 42 uint32_t hw_usbctrl_usbcmd; /* 0x140 */ 43 uint32_t hw_usbctrl_usbsts; /* 0x144 */ 44 uint32_t hw_usbctrl_usbintr; /* 0x148 */ 45 uint32_t hw_usbctrl_frindex; /* 0x14c */ 46 47 uint32_t reserved5; 48 49 union { 50 uint32_t hw_usbctrl_periodiclistbase; /* 0x154 */ 51 uint32_t hw_usbctrl_deviceaddr; /* 0x154 */ 52 }; 53 union { 54 uint32_t hw_usbctrl_asynclistaddr; /* 0x158 */ 55 uint32_t hw_usbctrl_endpointlistaddr; /* 0x158 */ 56 }; 57 58 uint32_t hw_usbctrl_ttctrl; /* 0x15c */ 59 uint32_t hw_usbctrl_burstsize; /* 0x160 */ 60 uint32_t hw_usbctrl_txfilltuning; /* 0x164 */ 61 62 uint32_t reserved6; 63 64 uint32_t hw_usbctrl_ic_usb; /* 0x16c */ 65 uint32_t hw_usbctrl_ulpi; /* 0x170 */ 66 67 uint32_t reserved7; 68 69 uint32_t hw_usbctrl_endptnak; /* 0x178 */ 70 uint32_t hw_usbctrl_endptnaken; /* 0x17c */ 71 72 uint32_t reserved8; 73 74 uint32_t hw_usbctrl_portsc1; /* 0x184 */ 75 76 uint32_t reserved9[7]; 77 78 uint32_t hw_usbctrl_otgsc; /* 0x1a4 */ 79 uint32_t hw_usbctrl_usbmode; /* 0x1a8 */ 80 uint32_t hw_usbctrl_endptsetupstat; /* 0x1ac */ 81 uint32_t hw_usbctrl_endptprime; /* 0x1b0 */ 82 uint32_t hw_usbctrl_endptflush; /* 0x1b4 */ 83 uint32_t hw_usbctrl_endptstat; /* 0x1b8 */ 84 uint32_t hw_usbctrl_endptcomplete; /* 0x1bc */ 85 uint32_t hw_usbctrl_endptctrl0; /* 0x1c0 */ 86 uint32_t hw_usbctrl_endptctrl1; /* 0x1c4 */ 87 uint32_t hw_usbctrl_endptctrl2; /* 0x1c8 */ 88 uint32_t hw_usbctrl_endptctrl3; /* 0x1cc */ 89 uint32_t hw_usbctrl_endptctrl4; /* 0x1d0 */ 90 uint32_t hw_usbctrl_endptctrl5; /* 0x1d4 */ 91 uint32_t hw_usbctrl_endptctrl6; /* 0x1d8 */ 92 uint32_t hw_usbctrl_endptctrl7; /* 0x1dc */ 93}; 94 95#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) 96 97#define HW_USBCTRL_ID_CIVERSION_OFFSET 29 98#define HW_USBCTRL_ID_CIVERSION_MASK (0x7 << 29) 99#define HW_USBCTRL_ID_VERSION_OFFSET 25 100#define HW_USBCTRL_ID_VERSION_MASK (0xf << 25) 101#define HW_USBCTRL_ID_REVISION_OFFSET 21 102#define HW_USBCTRL_ID_REVISION_MASK (0xf << 21) 103#define HW_USBCTRL_ID_TAG_OFFSET 16 104#define HW_USBCTRL_ID_TAG_MASK (0x1f << 16) 105#define HW_USBCTRL_ID_NID_OFFSET 8 106#define HW_USBCTRL_ID_NID_MASK (0x3f << 8) 107#define HW_USBCTRL_ID_ID_OFFSET 0 108#define HW_USBCTRL_ID_ID_MASK (0x3f << 0) 109 110#define HW_USBCTRL_HWGENERAL_SM_OFFSET 9 111#define HW_USBCTRL_HWGENERAL_SM_MASK (0x3 << 9) 112#define HW_USBCTRL_HWGENERAL_PHYM_OFFSET 6 113#define HW_USBCTRL_HWGENERAL_PHYM_MASK (0x7 << 6) 114#define HW_USBCTRL_HWGENERAL_PHYW_OFFSET 4 115#define HW_USBCTRL_HWGENERAL_PHYW_MASK (0x3 << 4) 116#define HW_USBCTRL_HWGENERAL_BWT (1 << 3) 117#define HW_USBCTRL_HWGENERAL_CLKC_OFFSET 1 118#define HW_USBCTRL_HWGENERAL_CLKC_MASK (0x3 << 1) 119#define HW_USBCTRL_HWGENERAL_RT (1 << 0) 120 121#define HW_USBCTRL_HWHOST_TTPER_OFFSET 24 122#define HW_USBCTRL_HWHOST_TTPER_MASK (0xff << 24) 123#define HW_USBCTRL_HWHOST_TTASY_OFFSET 16 124#define HW_USBCTRL_HWHOST_TTASY_MASK (0xff << 19) 125#define HW_USBCTRL_HWHOST_NPORT_OFFSET 1 126#define HW_USBCTRL_HWHOST_NPORT_MASK (0x7 << 1) 127#define HW_USBCTRL_HWHOST_HC (1 << 0) 128 129#define HW_USBCTRL_HWDEVICE_DEVEP_OFFSET 1 130#define HW_USBCTRL_HWDEVICE_DEVEP_MASK (0x1f << 1) 131#define HW_USBCTRL_HWDEVICE_DC (1 << 0) 132 133#define HW_USBCTRL_HWTXBUF_TXLCR (1 << 31) 134#define HW_USBCTRL_HWTXBUF_TXCHANADD_OFFSET 16 135#define HW_USBCTRL_HWTXBUF_TXCHANADD_MASK (0xff << 16) 136#define HW_USBCTRL_HWTXBUF_TXADD_OFFSET 8 137#define HW_USBCTRL_HWTXBUF_TXADD_MASK (0xff << 8) 138#define HW_USBCTRL_HWTXBUF_TXBURST_OFFSET 0 139#define HW_USBCTRL_HWTXBUF_TXBURST_MASK 0xff 140 141#define HW_USBCTRL_HWRXBUF_RXADD_OFFSET 8 142#define HW_USBCTRL_HWRXBUF_RXADD_MASK (0xff << 8) 143#define HW_USBCTRL_HWRXBUF_RXBURST_OFFSET 0 144#define HW_USBCTRL_HWRXBUF_RXBURST_MASK 0xff 145 146#define HW_USBCTRL_GPTIMERLD_GPTLD_OFFSET 0 147#define HW_USBCTRL_GPTIMERLD_GPTLD_MASK 0xffffff 148 149#define HW_USBCTRL_GPTIMERCTRL_GPTRUN (1 << 31) 150#define HW_USBCTRL_GPTIMERCTRL_GPTRST (1 << 30) 151#define HW_USBCTRL_GPTIMERCTRL_GPTMODE (1 << 24) 152#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_OFFSET 0 153#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_MASK 0xffffff 154 155#define HW_USBCTRL_SBUSCFG_AHBBURST_OFFSET 0 156#define HW_USBCTRL_SBUSCFG_AHBBURST_MASK 0x7 157#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR 0x0 158#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR4 0x1 159#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR8 0x2 160#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR16 0x3 161#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR4 0x5 162#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR8 0x6 163#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR16 0x7 164 165#endif /* __REGS_USB_H__ */ 166