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9#ifndef _ASM_ARCH_CRU_RK3288_H
10#define _ASM_ARCH_CRU_RK3288_H
11
12#define OSC_HZ (24 * 1000 * 1000)
13
14#define APLL_HZ (1800 * 1000000)
15#define GPLL_HZ (594 * 1000000)
16#define CPLL_HZ (384 * 1000000)
17#define NPLL_HZ (384 * 1000000)
18
19
20#define PD_BUS_ACLK_HZ 297000000
21#define PD_BUS_HCLK_HZ 148500000
22#define PD_BUS_PCLK_HZ 74250000
23
24#define PERI_ACLK_HZ 148500000
25#define PERI_HCLK_HZ 148500000
26#define PERI_PCLK_HZ 74250000
27
28
29struct rk3288_clk_priv {
30 struct rk3288_grf *grf;
31 struct rk3288_cru *cru;
32 ulong rate;
33};
34
35struct rk3288_cru {
36 struct rk3288_pll {
37 u32 con0;
38 u32 con1;
39 u32 con2;
40 u32 con3;
41 } pll[5];
42 u32 cru_mode_con;
43 u32 reserved0[3];
44 u32 cru_clksel_con[43];
45 u32 reserved1[21];
46 u32 cru_clkgate_con[19];
47 u32 reserved2;
48 u32 cru_glb_srst_fst_value;
49 u32 cru_glb_srst_snd_value;
50 u32 cru_softrst_con[12];
51 u32 cru_misc_con;
52 u32 cru_glb_cnt_th;
53 u32 cru_glb_rst_con;
54 u32 reserved3;
55 u32 cru_glb_rst_st;
56 u32 reserved4;
57 u32 cru_sdmmc_con[2];
58 u32 cru_sdio0_con[2];
59 u32 cru_sdio1_con[2];
60 u32 cru_emmc_con[2];
61};
62check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
63
64
65enum {
66 HSICPHY_DIV_SHIFT = 8,
67 HSICPHY_DIV_MASK = 0x3f,
68
69 MMC0_PLL_SHIFT = 6,
70 MMC0_PLL_MASK = 3,
71 MMC0_PLL_SELECT_CODEC = 0,
72 MMC0_PLL_SELECT_GENERAL,
73 MMC0_PLL_SELECT_24MHZ,
74
75 MMC0_DIV_SHIFT = 0,
76 MMC0_DIV_MASK = 0x3f,
77};
78
79
80enum {
81 EMMC_PLL_SHIFT = 0xe,
82 EMMC_PLL_MASK = 3,
83 EMMC_PLL_SELECT_CODEC = 0,
84 EMMC_PLL_SELECT_GENERAL,
85 EMMC_PLL_SELECT_24MHZ,
86
87 EMMC_DIV_SHIFT = 8,
88 EMMC_DIV_MASK = 0x3f,
89
90 SDIO0_PLL_SHIFT = 6,
91 SDIO0_PLL_MASK = 3,
92 SDIO0_PLL_SELECT_CODEC = 0,
93 SDIO0_PLL_SELECT_GENERAL,
94 SDIO0_PLL_SELECT_24MHZ,
95
96 SDIO0_DIV_SHIFT = 0,
97 SDIO0_DIV_MASK = 0x3f,
98};
99
100
101enum {
102 MAC_DIV_CON_SHIFT = 0xf,
103 MAC_DIV_CON_MASK = 0x1f,
104
105 RMII_EXTCLK_SHIFT = 4,
106 RMII_EXTCLK_MASK = 1,
107 RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
108 RMII_EXTCLK_SELECT_EXT_CLK = 1,
109
110 EMAC_PLL_SHIFT = 0,
111 EMAC_PLL_MASK = 0x3,
112 EMAC_PLL_SELECT_NEW = 0x0,
113 EMAC_PLL_SELECT_CODEC = 0x1,
114 EMAC_PLL_SELECT_GENERAL = 0x2,
115};
116
117
118enum {
119 SPI1_PLL_SHIFT = 0xf,
120 SPI1_PLL_MASK = 1,
121 SPI1_PLL_SELECT_CODEC = 0,
122 SPI1_PLL_SELECT_GENERAL,
123
124 SPI1_DIV_SHIFT = 8,
125 SPI1_DIV_MASK = 0x7f,
126
127 SPI0_PLL_SHIFT = 7,
128 SPI0_PLL_MASK = 1,
129 SPI0_PLL_SELECT_CODEC = 0,
130 SPI0_PLL_SELECT_GENERAL,
131
132 SPI0_DIV_SHIFT = 0,
133 SPI0_DIV_MASK = 0x7f,
134};
135
136
137enum {
138 PCLK_CORE_DBG_DIV_SHIFT = 9,
139 PCLK_CORE_DBG_DIV_MASK = 0x1f,
140
141 ATCLK_CORE_DIV_CON_SHIFT = 4,
142 ATCLK_CORE_DIV_CON_MASK = 0x1f,
143
144 CLK_L2RAM_DIV_SHIFT = 0,
145 CLK_L2RAM_DIV_MASK = 7,
146};
147
148
149enum {
150 ACLK_HEVC_PLL_SHIFT = 0xe,
151 ACLK_HEVC_PLL_MASK = 3,
152 ACLK_HEVC_PLL_SELECT_CODEC = 0,
153 ACLK_HEVC_PLL_SELECT_GENERAL,
154 ACLK_HEVC_PLL_SELECT_NEW,
155
156 ACLK_HEVC_DIV_SHIFT = 8,
157 ACLK_HEVC_DIV_MASK = 0x1f,
158
159 SPI2_PLL_SHIFT = 7,
160 SPI2_PLL_MASK = 1,
161 SPI2_PLL_SELECT_CODEC = 0,
162 SPI2_PLL_SELECT_GENERAL,
163
164 SPI2_DIV_SHIFT = 0,
165 SPI2_DIV_MASK = 0x7f,
166};
167
168
169enum {
170 NPLL_MODE_SHIFT = 0xe,
171 NPLL_MODE_MASK = 3,
172 NPLL_MODE_SLOW = 0,
173 NPLL_MODE_NORMAL,
174 NPLL_MODE_DEEP,
175
176 GPLL_MODE_SHIFT = 0xc,
177 GPLL_MODE_MASK = 3,
178 GPLL_MODE_SLOW = 0,
179 GPLL_MODE_NORMAL,
180 GPLL_MODE_DEEP,
181
182 CPLL_MODE_SHIFT = 8,
183 CPLL_MODE_MASK = 3,
184 CPLL_MODE_SLOW = 0,
185 CPLL_MODE_NORMAL,
186 CPLL_MODE_DEEP,
187
188 DPLL_MODE_SHIFT = 4,
189 DPLL_MODE_MASK = 3,
190 DPLL_MODE_SLOW = 0,
191 DPLL_MODE_NORMAL,
192 DPLL_MODE_DEEP,
193
194 APLL_MODE_SHIFT = 0,
195 APLL_MODE_MASK = 3,
196 APLL_MODE_SLOW = 0,
197 APLL_MODE_NORMAL,
198 APLL_MODE_DEEP,
199};
200
201
202enum {
203 CLKR_SHIFT = 8,
204 CLKR_MASK = 0x3f,
205
206 CLKOD_SHIFT = 0,
207 CLKOD_MASK = 0xf,
208};
209
210
211enum {
212 LOCK_SHIFT = 0x1f,
213 LOCK_MASK = 1,
214 LOCK_UNLOCK = 0,
215 LOCK_LOCK,
216
217 CLKF_SHIFT = 0,
218 CLKF_MASK = 0x1fff,
219};
220
221#endif
222
