LXR uboot/arch/arm/mach-at91/phy.c

   1/*
   2 * (C) Copyright 2007-2008
   3 * Stelian Pop <stelian@popies.net>
   4 * Lead Tech Design <www.leadtechdesign.com>
   5 *
   6 * (C) Copyright 2012
   7 * Markus Hubig <mhubig@imko.de>
   8 * IMKO GmbH <www.imko.de>
   9 *
  10 * Copyright (C) 2013 DENX Software Engineering, hs@denx.de
  11 *
  12 * SPDX-License-Identifier:     GPL-2.0+
  13 */
  14
  15#include <common.h>
  16#include <asm/io.h>
  17#include <linux/sizes.h>
  18#include <asm/arch/at91_rstc.h>
  19#include <watchdog.h>
  20
  21void at91_phy_reset(void)
  22{
  23        unsigned long erstl;
  24        unsigned long start = get_timer(0);
  25        unsigned long const timeout = 1000; /* 1000ms */
  26        at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
  27
  28        erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
  29
  30        /*
  31         * Need to reset PHY -> 500ms reset
  32         * Reset PHY by pulling the NRST line for 500ms to low. To do so
  33         * disable user reset for low level on NRST pin and poll the NRST
  34         * level in reset status register.
  35         */
  36        writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
  37                AT91_RSTC_MR_URSTEN, &rstc->mr);
  38
  39        writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
  40
  41        /* Wait for end of hardware reset */
  42        while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
  43                /* avoid shutdown by watchdog */
  44                WATCHDOG_RESET();
  45                mdelay(10);
  46
  47                /* timeout for not getting stuck in an endless loop */
  48                if (get_timer(start) >= timeout) {
  49                        puts("*** ERROR: Timeout waiting for PHY reset!\n");
  50                        break;
  51                }
  52        };
  53
  54        /* Restore NRST value */
  55        writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
  56}
  57