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12#ifndef __IMMAP_85xx__
13#define __IMMAP_85xx__
14
15#include <asm/types.h>
16#include <asm/fsl_dma.h>
17#include <asm/fsl_i2c.h>
18#include <fsl_ifc.h>
19#include <fsl_sec.h>
20#include <fsl_sfp.h>
21#include <asm/fsl_lbc.h>
22#include <fsl_fman.h>
23#include <fsl_immap.h>
24
25typedef struct ccsr_local {
26 u32 ccsrbarh;
27 u32 ccsrbarl;
28 u32 ccsrar;
29#define CCSRAR_C 0x80000000
30 u8 res1[4];
31 u32 altcbarh;
32 u32 altcbarl;
33 u32 altcar;
34 u8 res2[4];
35 u32 bstrh;
36 u32 bstrl;
37 u32 bstrar;
38 u8 res3[0xbd4];
39 struct {
40 u32 lawbarh;
41 u32 lawbarl;
42 u32 lawar;
43 u8 res4[4];
44 } law[32];
45 u8 res35[0x204];
46} ccsr_local_t;
47
48
49typedef struct ccsr_local_ecm {
50 u32 ccsrbar;
51 u8 res1[4];
52 u32 altcbar;
53 u8 res2[4];
54 u32 altcar;
55 u8 res3[12];
56 u32 bptr;
57 u8 res4[3044];
58 u32 lawbar0;
59 u8 res5[4];
60 u32 lawar0;
61 u8 res6[20];
62 u32 lawbar1;
63 u8 res7[4];
64 u32 lawar1;
65 u8 res8[20];
66 u32 lawbar2;
67 u8 res9[4];
68 u32 lawar2;
69 u8 res10[20];
70 u32 lawbar3;
71 u8 res11[4];
72 u32 lawar3;
73 u8 res12[20];
74 u32 lawbar4;
75 u8 res13[4];
76 u32 lawar4;
77 u8 res14[20];
78 u32 lawbar5;
79 u8 res15[4];
80 u32 lawar5;
81 u8 res16[20];
82 u32 lawbar6;
83 u8 res17[4];
84 u32 lawar6;
85 u8 res18[20];
86 u32 lawbar7;
87 u8 res19[4];
88 u32 lawar7;
89 u8 res19_8a[20];
90 u32 lawbar8;
91 u8 res19_8b[4];
92 u32 lawar8;
93 u8 res19_9a[20];
94 u32 lawbar9;
95 u8 res19_9b[4];
96 u32 lawar9;
97 u8 res19_10a[20];
98 u32 lawbar10;
99 u8 res19_10b[4];
100 u32 lawar10;
101 u8 res19_11a[20];
102 u32 lawbar11;
103 u8 res19_11b[4];
104 u32 lawar11;
105 u8 res20[652];
106 u32 eebacr;
107 u8 res21[12];
108 u32 eebpcr;
109 u8 res22[3564];
110 u32 eedr;
111 u8 res23[4];
112 u32 eeer;
113 u32 eeatr;
114 u32 eeadr;
115 u8 res24[492];
116} ccsr_local_ecm_t;
117
118#define DDR_EOR_RD_BDW_OPT_DIS 0x80000000
119#define DDR_EOR_ADDR_HASH_EN 0x40000000
120
121
122typedef struct ccsr_i2c {
123 struct fsl_i2c_base i2c[1];
124 u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
125} ccsr_i2c_t;
126
127#if defined(CONFIG_ARCH_MPC8540) || \
128 defined(CONFIG_ARCH_MPC8541) || \
129 defined(CONFIG_ARCH_MPC8548) || \
130 defined(CONFIG_ARCH_MPC8555)
131
132typedef struct ccsr_duart {
133 u8 res1[1280];
134
135 u8 urbr1_uthr1_udlb1;
136
137 u8 uier1_udmb1;
138
139 u8 uiir1_ufcr1_uafr1;
140 u8 ulcr1;
141 u8 umcr1;
142 u8 ulsr1;
143 u8 umsr1;
144 u8 uscr1;
145 u8 res2[8];
146 u8 udsr1;
147 u8 res3[239];
148
149 u8 urbr2_uthr2_udlb2;
150
151 u8 uier2_udmb2;
152
153 u8 uiir2_ufcr2_uafr2;
154 u8 ulcr2;
155 u8 umcr2;
156 u8 ulsr2;
157 u8 umsr2;
158 u8 uscr2;
159 u8 res4[8];
160 u8 udsr2;
161 u8 res5[2543];
162} ccsr_duart_t;
163#else
164typedef struct ccsr_duart {
165 u8 res[4096];
166} ccsr_duart_t;
167#endif
168
169
170typedef struct ccsr_espi {
171 u32 mode;
172 u32 event;
173 u32 mask;
174 u32 com;
175 u32 tx;
176 u32 rx;
177 u8 res1[8];
178 u32 csmode[4];
179 u8 res2[4048];
180} ccsr_espi_t;
181
182
183typedef struct ccsr_pcix {
184 u32 cfg_addr;
185 u32 cfg_data;
186 u32 int_ack;
187 u8 res000c[52];
188 u32 liodn_base;
189 u8 res0044[2996];
190 u32 ipver1;
191 u32 ipver2;
192 u32 potar0;
193 u32 potear0;
194 u32 powbar0;
195 u32 powbear0;
196 u32 powar0;
197 u8 res2[12];
198 u32 potar1;
199 u32 potear1;
200 u32 powbar1;
201 u32 powbear1;
202 u32 powar1;
203 u8 res3[12];
204 u32 potar2;
205 u32 potear2;
206 u32 powbar2;
207 u32 powbear2;
208 u32 powar2;
209 u8 res4[12];
210 u32 potar3;
211 u32 potear3;
212 u32 powbar3;
213 u32 powbear3;
214 u32 powar3;
215 u8 res5[12];
216 u32 potar4;
217 u32 potear4;
218 u32 powbar4;
219 u32 powbear4;
220 u32 powar4;
221 u8 res6[268];
222 u32 pitar3;
223 u32 pitear3;
224 u32 piwbar3;
225 u32 piwbear3;
226 u32 piwar3;
227 u8 res7[12];
228 u32 pitar2;
229 u32 pitear2;
230 u32 piwbar2;
231 u32 piwbear2;
232 u32 piwar2;
233 u8 res8[12];
234 u32 pitar1;
235 u32 pitear1;
236 u32 piwbar1;
237 u8 res9[4];
238 u32 piwar1;
239 u8 res10[12];
240 u32 pedr;
241 u32 pecdr;
242 u32 peer;
243 u32 peattrcr;
244 u32 peaddrcr;
245 u32 peextaddrcr;
246 u32 pedlcr;
247 u32 pedhcr;
248 u32 gas_timr;
249 u8 res11[476];
250} ccsr_pcix_t;
251
252#define PCIX_COMMAND 0x62
253#define POWAR_EN 0x80000000
254#define POWAR_IO_READ 0x00080000
255#define POWAR_MEM_READ 0x00040000
256#define POWAR_IO_WRITE 0x00008000
257#define POWAR_MEM_WRITE 0x00004000
258#define POWAR_MEM_512M 0x0000001c
259#define POWAR_IO_1M 0x00000013
260
261#define PIWAR_EN 0x80000000
262#define PIWAR_PF 0x20000000
263#define PIWAR_LOCAL 0x00f00000
264#define PIWAR_READ_SNOOP 0x00050000
265#define PIWAR_WRITE_SNOOP 0x00005000
266#define PIWAR_MEM_2G 0x0000001e
267
268#ifndef CONFIG_MPC85XX_GPIO
269typedef struct ccsr_gpio {
270 u32 gpdir;
271 u32 gpodr;
272 u32 gpdat;
273 u32 gpier;
274 u32 gpimr;
275 u32 gpicr;
276} ccsr_gpio_t;
277#endif
278
279
280typedef struct ccsr_l2cache {
281 u32 l2ctl;
282 u8 res1[12];
283 u32 l2cewar0;
284 u8 res2[4];
285 u32 l2cewcr0;
286 u8 res3[4];
287 u32 l2cewar1;
288 u8 res4[4];
289 u32 l2cewcr1;
290 u8 res5[4];
291 u32 l2cewar2;
292 u8 res6[4];
293 u32 l2cewcr2;
294 u8 res7[4];
295 u32 l2cewar3;
296 u8 res8[4];
297 u32 l2cewcr3;
298 u8 res9[180];
299 u32 l2srbar0;
300 u8 res10[4];
301 u32 l2srbar1;
302 u8 res11[3316];
303 u32 l2errinjhi;
304 u32 l2errinjlo;
305 u32 l2errinjctl;
306 u8 res12[20];
307 u32 l2captdatahi;
308 u32 l2captdatalo;
309 u32 l2captecc;
310 u8 res13[20];
311 u32 l2errdet;
312 u32 l2errdis;
313 u32 l2errinten;
314 u32 l2errattr;
315 u32 l2erraddr;
316 u8 res14[4];
317 u32 l2errctl;
318 u8 res15[420];
319} ccsr_l2cache_t;
320
321#define MPC85xx_L2CTL_L2E 0x80000000
322#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
323#define MPC85xx_L2ERRDIS_MBECC 0x00000008
324#define MPC85xx_L2ERRDIS_SBECC 0x00000004
325
326
327typedef struct ccsr_dma {
328 u8 res1[256];
329 struct fsl_dma dma[4];
330 u32 dgsr;
331 u8 res2[11516];
332} ccsr_dma_t;
333
334
335typedef struct ccsr_tsec {
336 u8 res1[16];
337 u32 ievent;
338 u32 imask;
339 u32 edis;
340 u8 res2[4];
341 u32 ecntrl;
342 u32 minflr;
343 u32 ptv;
344 u32 dmactrl;
345 u32 tbipa;
346 u8 res3[88];
347 u32 fifo_tx_thr;
348 u8 res4[8];
349 u32 fifo_tx_starve;
350 u32 fifo_tx_starve_shutoff;
351 u8 res5[96];
352 u32 tctrl;
353 u32 tstat;
354 u8 res6[4];
355 u32 tbdlen;
356 u8 res7[16];
357 u32 ctbptrh;
358 u32 ctbptr;
359 u8 res8[88];
360 u32 tbptrh;
361 u32 tbptr;
362 u8 res9[120];
363 u32 tbaseh;
364 u32 tbase;
365 u8 res10[168];
366 u32 ostbd;
367 u32 ostbdp;
368 u32 os32tbdp;
369 u32 os32iptrh;
370 u32 os32iptrl;
371 u32 os32tbdr;
372 u32 os32iil;
373 u8 res11[52];
374 u32 rctrl;
375 u32 rstat;
376 u8 res12[4];
377 u32 rbdlen;
378 u8 res13[16];
379 u32 crbptrh;
380 u32 crbptr;
381 u8 res14[24];
382 u32 mrblr;
383 u32 mrblr2r3;
384 u8 res15[56];
385 u32 rbptrh;
386 u32 rbptr;
387 u32 rbptrh1;
388 u32 rbptrl1;
389 u32 rbptrh2;
390 u32 rbptrl2;
391 u32 rbptrh3;
392 u32 rbptrl3;
393 u8 res16[96];
394 u32 rbaseh;
395 u32 rbase;
396 u32 rbaseh1;
397 u32 rbasel1;
398 u32 rbaseh2;
399 u32 rbasel2;
400 u32 rbaseh3;
401 u32 rbasel3;
402 u8 res17[224];
403 u32 maccfg1;
404 u32 maccfg2;
405 u32 ipgifg;
406 u32 hafdup;
407 u32 maxfrm;
408 u8 res18[12];
409 u32 miimcfg;
410 u32 miimcom;
411 u32 miimadd;
412 u32 miimcon;
413 u32 miimstat;
414 u32 miimind;
415 u8 res19[4];
416 u32 ifstat;
417 u32 macstnaddr1;
418 u32 macstnaddr2;
419 u8 res20[312];
420 u32 tr64;
421 u32 tr127;
422 u32 tr255;
423 u32 tr511;
424 u32 tr1k;
425 u32 trmax;
426 u32 trmgv;
427 u32 rbyt;
428 u32 rpkt;
429 u32 rfcs;
430 u32 rmca;
431 u32 rbca;
432 u32 rxcf;
433 u32 rxpf;
434 u32 rxuo;
435 u32 raln;
436 u32 rflr;
437 u32 rcde;
438 u32 rcse;
439 u32 rund;
440 u32 rovr;
441 u32 rfrg;
442 u32 rjbr;
443 u32 rdrp;
444 u32 tbyt;
445 u32 tpkt;
446 u32 tmca;
447 u32 tbca;
448 u32 txpf;
449 u32 tdfr;
450 u32 tedf;
451 u32 tscl;
452 u32 tmcl;
453 u32 tlcl;
454 u32 txcl;
455 u32 tncl;
456 u8 res21[4];
457 u32 tdrp;
458 u32 tjbr;
459 u32 tfcs;
460 u32 txcf;
461 u32 tovr;
462 u32 tund;
463 u32 tfrg;
464 u32 car1;
465 u32 car2;
466 u32 cam1;
467 u32 cam2;
468 u8 res22[192];
469 u32 iaddr0;
470 u32 iaddr1;
471 u32 iaddr2;
472 u32 iaddr3;
473 u32 iaddr4;
474 u32 iaddr5;
475 u32 iaddr6;
476 u32 iaddr7;
477 u8 res23[96];
478 u32 gaddr0;
479 u32 gaddr1;
480 u32 gaddr2;
481 u32 gaddr3;
482 u32 gaddr4;
483 u32 gaddr5;
484 u32 gaddr6;
485 u32 gaddr7;
486 u8 res24[96];
487 u32 pmd0;
488 u8 res25[4];
489 u32 pmask0;
490 u8 res26[4];
491 u32 pcntrl0;
492 u8 res27[4];
493 u32 pattrb0;
494 u32 pattrbeli0;
495 u32 pmd1;
496 u8 res28[4];
497 u32 pmask1;
498 u8 res29[4];
499 u32 pcntrl1;
500 u8 res30[4];
501 u32 pattrb1;
502 u32 pattrbeli1;
503 u32 pmd2;
504 u8 res31[4];
505 u32 pmask2;
506 u8 res32[4];
507 u32 pcntrl2;
508 u8 res33[4];
509 u32 pattrb2;
510 u32 pattrbeli2;
511 u32 pmd3;
512 u8 res34[4];
513 u32 pmask3;
514 u8 res35[4];
515 u32 pcntrl3;
516 u8 res36[4];
517 u32 pattrb3;
518 u32 pattrbeli3;
519 u32 pmd4;
520 u8 res37[4];
521 u32 pmask4;
522 u8 res38[4];
523 u32 pcntrl4;
524 u8 res39[4];
525 u32 pattrb4;
526 u32 pattrbeli4;
527 u32 pmd5;
528 u8 res40[4];
529 u32 pmask5;
530 u8 res41[4];
531 u32 pcntrl5;
532 u8 res42[4];
533 u32 pattrb5;
534 u32 pattrbeli5;
535 u32 pmd6;
536 u8 res43[4];
537 u32 pmask6;
538 u8 res44[4];
539 u32 pcntrl6;
540 u8 res45[4];
541 u32 pattrb6;
542 u32 pattrbeli6;
543 u32 pmd7;
544 u8 res46[4];
545 u32 pmask7;
546 u8 res47[4];
547 u32 pcntrl7;
548 u8 res48[4];
549 u32 pattrb7;
550 u32 pattrbeli7;
551 u32 pmd8;
552 u8 res49[4];
553 u32 pmask8;
554 u8 res50[4];
555 u32 pcntrl8;
556 u8 res51[4];
557 u32 pattrb8;
558 u32 pattrbeli8;
559 u32 pmd9;
560 u8 res52[4];
561 u32 pmask9;
562 u8 res53[4];
563 u32 pcntrl9;
564 u8 res54[4];
565 u32 pattrb9;
566 u32 pattrbeli9;
567 u32 pmd10;
568 u8 res55[4];
569 u32 pmask10;
570 u8 res56[4];
571 u32 pcntrl10;
572 u8 res57[4];
573 u32 pattrb10;
574 u32 pattrbeli10;
575 u32 pmd11;
576 u8 res58[4];
577 u32 pmask11;
578 u8 res59[4];
579 u32 pcntrl11;
580 u8 res60[4];
581 u32 pattrb11;
582 u32 pattrbeli11;
583 u32 pmd12;
584 u8 res61[4];
585 u32 pmask12;
586 u8 res62[4];
587 u32 pcntrl12;
588 u8 res63[4];
589 u32 pattrb12;
590 u32 pattrbeli12;
591 u32 pmd13;
592 u8 res64[4];
593 u32 pmask13;
594 u8 res65[4];
595 u32 pcntrl13;
596 u8 res66[4];
597 u32 pattrb13;
598 u32 pattrbeli13;
599 u32 pmd14;
600 u8 res67[4];
601 u32 pmask14;
602 u8 res68[4];
603 u32 pcntrl14;
604 u8 res69[4];
605 u32 pattrb14;
606 u32 pattrbeli14;
607 u32 pmd15;
608 u8 res70[4];
609 u32 pmask15;
610 u8 res71[4];
611 u32 pcntrl15;
612 u8 res72[4];
613 u32 pattrb15;
614 u32 pattrbeli15;
615 u8 res73[248];
616 u32 attr;
617 u32 attreli;
618 u8 res74[1024];
619} ccsr_tsec_t;
620
621
622typedef struct ccsr_pic {
623 u8 res1[64];
624 u32 ipidr0;
625 u8 res2[12];
626 u32 ipidr1;
627 u8 res3[12];
628 u32 ipidr2;
629 u8 res4[12];
630 u32 ipidr3;
631 u8 res5[12];
632 u32 ctpr;
633 u8 res6[12];
634 u32 whoami;
635 u8 res7[12];
636 u32 iack;
637 u8 res8[12];
638 u32 eoi;
639 u8 res9[3916];
640 u32 frr;
641 u8 res10[28];
642 u32 gcr;
643#define MPC85xx_PICGCR_RST 0x80000000
644#define MPC85xx_PICGCR_M 0x20000000
645 u8 res11[92];
646 u32 vir;
647 u8 res12[12];
648 u32 pir;
649 u8 res13[12];
650 u32 ipivpr0;
651 u8 res14[12];
652 u32 ipivpr1;
653 u8 res15[12];
654 u32 ipivpr2;
655 u8 res16[12];
656 u32 ipivpr3;
657 u8 res17[12];
658 u32 svr;
659 u8 res18[12];
660 u32 tfrr;
661 u8 res19[12];
662 u32 gtccr0;
663 u8 res20[12];
664 u32 gtbcr0;
665 u8 res21[12];
666 u32 gtvpr0;
667 u8 res22[12];
668 u32 gtdr0;
669 u8 res23[12];
670 u32 gtccr1;
671 u8 res24[12];
672 u32 gtbcr1;
673 u8 res25[12];
674 u32 gtvpr1;
675 u8 res26[12];
676 u32 gtdr1;
677 u8 res27[12];
678 u32 gtccr2;
679 u8 res28[12];
680 u32 gtbcr2;
681 u8 res29[12];
682 u32 gtvpr2;
683 u8 res30[12];
684 u32 gtdr2;
685 u8 res31[12];
686 u32 gtccr3;
687 u8 res32[12];
688 u32 gtbcr3;
689 u8 res33[12];
690 u32 gtvpr3;
691 u8 res34[12];
692 u32 gtdr3;
693 u8 res35[268];
694 u32 tcr;
695 u8 res36[12];
696 u32 irqsr0;
697 u8 res37[12];
698 u32 irqsr1;
699 u8 res38[12];
700 u32 cisr0;
701 u8 res39[12];
702 u32 cisr1;
703 u8 res40[188];
704 u32 msgr0;
705 u8 res41[12];
706 u32 msgr1;
707 u8 res42[12];
708 u32 msgr2;
709 u8 res43[12];
710 u32 msgr3;
711 u8 res44[204];
712 u32 mer;
713 u8 res45[12];
714 u32 msr;
715 u8 res46[60140];
716 u32 eivpr0;
717 u8 res47[12];
718 u32 eidr0;
719 u8 res48[12];
720 u32 eivpr1;
721 u8 res49[12];
722 u32 eidr1;
723 u8 res50[12];
724 u32 eivpr2;
725 u8 res51[12];
726 u32 eidr2;
727 u8 res52[12];
728 u32 eivpr3;
729 u8 res53[12];
730 u32 eidr3;
731 u8 res54[12];
732 u32 eivpr4;
733 u8 res55[12];
734 u32 eidr4;
735 u8 res56[12];
736 u32 eivpr5;
737 u8 res57[12];
738 u32 eidr5;
739 u8 res58[12];
740 u32 eivpr6;
741 u8 res59[12];
742 u32 eidr6;
743 u8 res60[12];
744 u32 eivpr7;
745 u8 res61[12];
746 u32 eidr7;
747 u8 res62[12];
748 u32 eivpr8;
749 u8 res63[12];
750 u32 eidr8;
751 u8 res64[12];
752 u32 eivpr9;
753 u8 res65[12];
754 u32 eidr9;
755 u8 res66[12];
756 u32 eivpr10;
757 u8 res67[12];
758 u32 eidr10;
759 u8 res68[12];
760 u32 eivpr11;
761 u8 res69[12];
762 u32 eidr11;
763 u8 res70[140];
764 u32 iivpr0;
765 u8 res71[12];
766 u32 iidr0;
767 u8 res72[12];
768 u32 iivpr1;
769 u8 res73[12];
770 u32 iidr1;
771 u8 res74[12];
772 u32 iivpr2;
773 u8 res75[12];
774 u32 iidr2;
775 u8 res76[12];
776 u32 iivpr3;
777 u8 res77[12];
778 u32 iidr3;
779 u8 res78[12];
780 u32 iivpr4;
781 u8 res79[12];
782 u32 iidr4;
783 u8 res80[12];
784 u32 iivpr5;
785 u8 res81[12];
786 u32 iidr5;
787 u8 res82[12];
788 u32 iivpr6;
789 u8 res83[12];
790 u32 iidr6;
791 u8 res84[12];
792 u32 iivpr7;
793 u8 res85[12];
794 u32 iidr7;
795 u8 res86[12];
796 u32 iivpr8;
797 u8 res87[12];
798 u32 iidr8;
799 u8 res88[12];
800 u32 iivpr9;
801 u8 res89[12];
802 u32 iidr9;
803 u8 res90[12];
804 u32 iivpr10;
805 u8 res91[12];
806 u32 iidr10;
807 u8 res92[12];
808 u32 iivpr11;
809 u8 res93[12];
810 u32 iidr11;
811 u8 res94[12];
812 u32 iivpr12;
813 u8 res95[12];
814 u32 iidr12;
815 u8 res96[12];
816 u32 iivpr13;
817 u8 res97[12];
818 u32 iidr13;
819 u8 res98[12];
820 u32 iivpr14;
821 u8 res99[12];
822 u32 iidr14;
823 u8 res100[12];
824 u32 iivpr15;
825 u8 res101[12];
826 u32 iidr15;
827 u8 res102[12];
828 u32 iivpr16;
829 u8 res103[12];
830 u32 iidr16;
831 u8 res104[12];
832 u32 iivpr17;
833 u8 res105[12];
834 u32 iidr17;
835 u8 res106[12];
836 u32 iivpr18;
837 u8 res107[12];
838 u32 iidr18;
839 u8 res108[12];
840 u32 iivpr19;
841 u8 res109[12];
842 u32 iidr19;
843 u8 res110[12];
844 u32 iivpr20;
845 u8 res111[12];
846 u32 iidr20;
847 u8 res112[12];
848 u32 iivpr21;
849 u8 res113[12];
850 u32 iidr21;
851 u8 res114[12];
852 u32 iivpr22;
853 u8 res115[12];
854 u32 iidr22;
855 u8 res116[12];
856 u32 iivpr23;
857 u8 res117[12];
858 u32 iidr23;
859 u8 res118[12];
860 u32 iivpr24;
861 u8 res119[12];
862 u32 iidr24;
863 u8 res120[12];
864 u32 iivpr25;
865 u8 res121[12];
866 u32 iidr25;
867 u8 res122[12];
868 u32 iivpr26;
869 u8 res123[12];
870 u32 iidr26;
871 u8 res124[12];
872 u32 iivpr27;
873 u8 res125[12];
874 u32 iidr27;
875 u8 res126[12];
876 u32 iivpr28;
877 u8 res127[12];
878 u32 iidr28;
879 u8 res128[12];
880 u32 iivpr29;
881 u8 res129[12];
882 u32 iidr29;
883 u8 res130[12];
884 u32 iivpr30;
885 u8 res131[12];
886 u32 iidr30;
887 u8 res132[12];
888 u32 iivpr31;
889 u8 res133[12];
890 u32 iidr31;
891 u8 res134[4108];
892 u32 mivpr0;
893 u8 res135[12];
894 u32 midr0;
895 u8 res136[12];
896 u32 mivpr1;
897 u8 res137[12];
898 u32 midr1;
899 u8 res138[12];
900 u32 mivpr2;
901 u8 res139[12];
902 u32 midr2;
903 u8 res140[12];
904 u32 mivpr3;
905 u8 res141[12];
906 u32 midr3;
907 u8 res142[59852];
908 u32 ipi0dr0;
909 u8 res143[12];
910 u32 ipi0dr1;
911 u8 res144[12];
912 u32 ipi0dr2;
913 u8 res145[12];
914 u32 ipi0dr3;
915 u8 res146[12];
916 u32 ctpr0;
917 u8 res147[12];
918 u32 whoami0;
919 u8 res148[12];
920 u32 iack0;
921 u8 res149[12];
922 u32 eoi0;
923 u8 res150[130892];
924} ccsr_pic_t;
925
926
927#ifndef CONFIG_CPM2
928typedef struct ccsr_cpm {
929 u8 res[262144];
930} ccsr_cpm_t;
931#else
932
933
934
935
936typedef struct ccsr_cpm_siu {
937 u8 res1[80];
938 u32 smaer;
939 u32 smser;
940 u32 smevr;
941 u8 res2[4];
942 u32 lmaer;
943 u32 lmser;
944 u32 lmevr;
945 u8 res3[2964];
946} ccsr_cpm_siu_t;
947
948
949typedef struct ccsr_cpm_intctl {
950 u16 sicr;
951 u8 res1[2];
952 u32 sivec;
953 u32 sipnrh;
954 u32 sipnrl;
955 u32 siprr;
956 u32 scprrh;
957 u32 scprrl;
958 u32 simrh;
959 u32 simrl;
960 u32 siexr;
961 u8 res2[88];
962 u32 sccr;
963 u8 res3[124];
964} ccsr_cpm_intctl_t;
965
966
967typedef struct ccsr_cpm_iop {
968 u32 pdira;
969 u32 ppara;
970 u32 psora;
971 u32 podra;
972 u32 pdata;
973 u8 res1[12];
974 u32 pdirb;
975 u32 pparb;
976 u32 psorb;
977 u32 podrb;
978 u32 pdatb;
979 u8 res2[12];
980 u32 pdirc;
981 u32 pparc;
982 u32 psorc;
983 u32 podrc;
984 u32 pdatc;
985 u8 res3[12];
986 u32 pdird;
987 u32 ppard;
988 u32 psord;
989 u32 podrd;
990 u32 pdatd;
991 u8 res4[12];
992} ccsr_cpm_iop_t;
993
994
995typedef struct ccsr_cpm_timer {
996 u8 tgcr1;
997 u8 res1[3];
998 u8 tgcr2;
999 u8 res2[11];
1000 u16 tmr1;
1001 u16 tmr2;
1002 u16 trr1;
1003 u16 trr2;
1004 u16 tcr1;
1005 u16 tcr2;
1006 u16 tcn1;
1007 u16 tcn2;
1008 u16 tmr3;
1009 u16 tmr4;
1010 u16 trr3;
1011 u16 trr4;
1012 u16 tcr3;
1013 u16 tcr4;
1014 u16 tcn3;
1015 u16 tcn4;
1016 u16 ter1;
1017 u16 ter2;
1018 u16 ter3;
1019 u16 ter4;
1020 u8 res3[608];
1021} ccsr_cpm_timer_t;
1022
1023
1024typedef struct ccsr_cpm_sdma {
1025 u8 sdsr;
1026 u8 res1[3];
1027 u8 sdmr;
1028 u8 res2[739];
1029} ccsr_cpm_sdma_t;
1030
1031
1032typedef struct ccsr_cpm_fcc1 {
1033 u32 gfmr;
1034 u32 fpsmr;
1035 u16 ftodr;
1036 u8 res1[2];
1037 u16 fdsr;
1038 u8 res2[2];
1039 u16 fcce;
1040 u8 res3[2];
1041 u16 fccm;
1042 u8 res4[2];
1043 u8 fccs;
1044 u8 res5[3];
1045 u8 ftirr_phy[4];
1046} ccsr_cpm_fcc1_t;
1047
1048
1049typedef struct ccsr_cpm_fcc2 {
1050 u32 gfmr;
1051 u32 fpsmr;
1052 u16 ftodr;
1053 u8 res1[2];
1054 u16 fdsr;
1055 u8 res2[2];
1056 u16 fcce;
1057 u8 res3[2];
1058 u16 fccm;
1059 u8 res4[2];
1060 u8 fccs;
1061 u8 res5[3];
1062 u8 ftirr_phy[4];
1063} ccsr_cpm_fcc2_t;
1064
1065
1066typedef struct ccsr_cpm_fcc3 {
1067 u32 gfmr;
1068 u32 fpsmr;
1069 u16 ftodr;
1070 u8 res1[2];
1071 u16 fdsr;
1072 u8 res2[2];
1073 u16 fcce;
1074 u8 res3[2];
1075 u16 fccm;
1076 u8 res4[2];
1077 u8 fccs;
1078 u8 res5[3];
1079 u8 res[36];
1080} ccsr_cpm_fcc3_t;
1081
1082
1083typedef struct ccsr_cpm_fcc1_ext {
1084 u32 firper;
1085 u32 firer;
1086 u32 firsr_h;
1087 u32 firsr_l;
1088 u8 gfemr;
1089 u8 res[15];
1090
1091} ccsr_cpm_fcc1_ext_t;
1092
1093
1094typedef struct ccsr_cpm_fcc2_ext {
1095 u32 firper;
1096 u32 firer;
1097 u32 firsr_h;
1098 u32 firsr_l;
1099 u8 gfemr;
1100 u8 res[31];
1101} ccsr_cpm_fcc2_ext_t;
1102
1103
1104typedef struct ccsr_cpm_fcc3_ext {
1105 u8 gfemr;
1106 u8 res[47];
1107} ccsr_cpm_fcc3_ext_t;
1108
1109
1110typedef struct ccsr_cpm_tmp1 {
1111 u8 res[496];
1112} ccsr_cpm_tmp1_t;
1113
1114
1115typedef struct ccsr_cpm_brg2 {
1116 u32 brgc5;
1117 u32 brgc6;
1118 u32 brgc7;
1119 u32 brgc8;
1120 u8 res[608];
1121} ccsr_cpm_brg2_t;
1122
1123
1124typedef struct ccsr_cpm_i2c {
1125 u8 i2mod;
1126 u8 res1[3];
1127 u8 i2add;
1128 u8 res2[3];
1129 u8 i2brg;
1130 u8 res3[3];
1131 u8 i2com;
1132 u8 res4[3];
1133 u8 i2cer;
1134 u8 res5[3];
1135 u8 i2cmr;
1136 u8 res6[331];
1137} ccsr_cpm_i2c_t;
1138
1139
1140typedef struct ccsr_cpm_cp {
1141 u32 cpcr;
1142 u32 rccr;
1143 u8 res1[14];
1144 u16 rter;
1145 u8 res2[2];
1146 u16 rtmr;
1147 u16 rtscr;
1148 u8 res3[2];
1149 u32 rtsr;
1150 u8 res4[12];
1151} ccsr_cpm_cp_t;
1152
1153
1154typedef struct ccsr_cpm_brg1 {
1155 u32 brgc1;
1156 u32 brgc2;
1157 u32 brgc3;
1158 u32 brgc4;
1159} ccsr_cpm_brg1_t;
1160
1161
1162typedef struct ccsr_cpm_scc {
1163 u32 gsmrl;
1164 u32 gsmrh;
1165 u16 psmr;
1166 u8 res1[2];
1167 u16 todr;
1168 u16 dsr;
1169 u16 scce;
1170 u8 res2[2];
1171 u16 sccm;
1172 u8 res3;
1173 u8 sccs;
1174 u8 res4[8];
1175} ccsr_cpm_scc_t;
1176
1177typedef struct ccsr_cpm_tmp2 {
1178 u8 res[32];
1179} ccsr_cpm_tmp2_t;
1180
1181
1182typedef struct ccsr_cpm_spi {
1183 u16 spmode;
1184 u8 res1[4];
1185 u8 spie;
1186 u8 res2[3];
1187 u8 spim;
1188 u8 res3[2];
1189 u8 spcom;
1190 u8 res4[82];
1191} ccsr_cpm_spi_t;
1192
1193
1194typedef struct ccsr_cpm_mux {
1195 u8 cmxsi1cr;
1196 u8 res1;
1197 u8 cmxsi2cr;
1198 u8 res2;
1199 u32 cmxfcr;
1200 u32 cmxscr;
1201 u8 res3[2];
1202 u16 cmxuar;
1203 u8 res4[16];
1204} ccsr_cpm_mux_t;
1205
1206
1207typedef struct ccsr_cpm_tmp3 {
1208 u8 res[58592];
1209} ccsr_cpm_tmp3_t;
1210
1211typedef struct ccsr_cpm_iram {
1212 u32 iram[8192];
1213 u8 res[98304];
1214} ccsr_cpm_iram_t;
1215
1216typedef struct ccsr_cpm {
1217
1218
1219
1220#define im_dprambase im_dpram1
1221 u8 im_dpram1[16*1024];
1222 u8 res1[16*1024];
1223 u8 im_dpram2[16*1024];
1224 u8 res2[16*1024];
1225 ccsr_cpm_siu_t im_cpm_siu;
1226 ccsr_cpm_intctl_t im_cpm_intctl;
1227 ccsr_cpm_iop_t im_cpm_iop;
1228 ccsr_cpm_timer_t im_cpm_timer;
1229 ccsr_cpm_sdma_t im_cpm_sdma;
1230 ccsr_cpm_fcc1_t im_cpm_fcc1;
1231 ccsr_cpm_fcc2_t im_cpm_fcc2;
1232 ccsr_cpm_fcc3_t im_cpm_fcc3;
1233 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1234 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1235 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1236 ccsr_cpm_tmp1_t im_cpm_tmp1;
1237 ccsr_cpm_brg2_t im_cpm_brg2;
1238 ccsr_cpm_i2c_t im_cpm_i2c;
1239 ccsr_cpm_cp_t im_cpm_cp;
1240 ccsr_cpm_brg1_t im_cpm_brg1;
1241 ccsr_cpm_scc_t im_cpm_scc[4];
1242 ccsr_cpm_tmp2_t im_cpm_tmp2;
1243 ccsr_cpm_spi_t im_cpm_spi;
1244 ccsr_cpm_mux_t im_cpm_mux;
1245 ccsr_cpm_tmp3_t im_cpm_tmp3;
1246 ccsr_cpm_iram_t im_cpm_iram;
1247} ccsr_cpm_t;
1248#endif
1249
1250#ifdef CONFIG_SYS_SRIO
1251
1252struct rio_arch {
1253 u32 didcar;
1254 u32 dicar;
1255 u32 aidcar;
1256 u32 aicar;
1257 u32 pefcar;
1258 u8 res0[4];
1259 u32 socar;
1260 u32 docar;
1261 u8 res1[32];
1262 u32 mcsr;
1263 u32 pwdcsr;
1264 u8 res2[4];
1265 u32 pellccsr;
1266 u8 res3[12];
1267 u32 lcsbacsr;
1268 u32 bdidcsr;
1269 u8 res4[4];
1270 u32 hbdidlcsr;
1271 u32 ctcsr;
1272};
1273
1274
1275struct rio_lp_serial_port {
1276 u32 plmreqcsr;
1277 u32 plmrespcsr;
1278 u32 plascsr;
1279 u8 res0[12];
1280 u32 pescsr;
1281 u32 pccsr;
1282};
1283
1284
1285struct rio_lp_serial {
1286 u32 pmbh0csr;
1287 u8 res0[28];
1288 u32 pltoccsr;
1289 u32 prtoccsr;
1290 u8 res1[20];
1291 u32 pgccsr;
1292 struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1293};
1294
1295
1296struct rio_logical_err {
1297 u32 erbh;
1298 u8 res0[4];
1299 u32 ltledcsr;
1300 u32 ltleecsr;
1301 u8 res1[4];
1302 u32 ltlaccsr;
1303 u32 ltldidccsr;
1304 u32 ltlcccsr;
1305};
1306
1307
1308struct rio_phys_err_port {
1309 u32 edcsr;
1310 u32 erecsr;
1311 u32 ecacsr;
1312 u32 pcseccsr0;
1313 u32 peccsr[3];
1314 u8 res0[12];
1315 u32 ercsr;
1316 u32 ertcsr;
1317 u8 res1[16];
1318};
1319
1320
1321struct rio_phys_err {
1322 struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1323};
1324
1325
1326struct rio_impl_common {
1327 u8 res0[4];
1328 u32 llcr;
1329 u8 res1[8];
1330 u32 epwisr;
1331 u8 res2[12];
1332 u32 lretcr;
1333 u8 res3[92];
1334 u32 pretcr;
1335 u8 res4[124];
1336};
1337
1338
1339struct rio_impl_port_spec {
1340 u32 adidcsr;
1341 u8 res0[28];
1342 u32 ptaacr;
1343 u32 lopttlcr;
1344 u8 res1[8];
1345 u32 iecsr;
1346 u8 res2[12];
1347 u32 pcr;
1348 u8 res3[20];
1349 u32 slcsr;
1350 u8 res4[4];
1351 u32 sleicr;
1352 u32 a0txcr;
1353 u32 a1txcr;
1354 u32 a2txcr;
1355 u32 mreqtxbacr[3];
1356 u32 mrspfctxbacr;
1357};
1358
1359
1360struct rio_implement {
1361 struct rio_impl_common com;
1362 struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1363};
1364
1365
1366struct rio_rev_ctrl {
1367 u32 ipbrr[2];
1368};
1369
1370struct rio_atmu_row {
1371 u32 rowtar;
1372 u32 rowtear;
1373 u32 rowbar;
1374 u8 res0[4];
1375 u32 rowar;
1376 u32 rowsr[3];
1377};
1378
1379struct rio_atmu_riw {
1380 u32 riwtar;
1381 u8 res0[4];
1382 u32 riwbar;
1383 u8 res1[4];
1384 u32 riwar;
1385 u8 res2[12];
1386};
1387
1388
1389struct rio_atmu_win {
1390 struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
1391 u8 res0[64];
1392 struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
1393};
1394
1395struct rio_atmu {
1396 struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1397};
1398
1399#ifdef CONFIG_SYS_FSL_RMU
1400struct rio_msg {
1401 u32 omr;
1402 u32 osr;
1403 u32 eodqdpar;
1404 u32 odqdpar;
1405 u32 eosar;
1406 u32 osar;
1407 u32 odpr;
1408 u32 odatr;
1409 u32 odcr;
1410 u32 eodqepar;
1411 u32 odqepar;
1412 u32 oretr;
1413 u32 omgr;
1414 u32 omlr;
1415 u8 res0[40];
1416 u32 imr;
1417 u32 isr;
1418 u32 eidqdpar;
1419 u32 idqdpar;
1420 u32 eifqepar;
1421 u32 ifqepar;
1422 u32 imirir;
1423 u8 res1[4];
1424 u32 eihqepar;
1425 u32 ihqepar;
1426 u8 res2[120];
1427};
1428
1429struct rio_dbell {
1430 u32 odmr;
1431 u32 odsr;
1432 u8 res0[16];
1433 u32 oddpr;
1434 u32 oddatr;
1435 u8 res1[12];
1436 u32 oddretr;
1437 u8 res2[48];
1438 u32 idmr;
1439 u32 idsr;
1440 u32 iedqdpar;
1441 u32 iqdpar;
1442 u32 iedqepar;
1443 u32 idqepar;
1444 u32 idmirir;
1445};
1446
1447struct rio_pw {
1448 u32 pwmr;
1449 u32 pwsr;
1450 u32 epwqbar;
1451 u32 pwqbar;
1452};
1453#endif
1454
1455#ifdef CONFIG_SYS_FSL_SRIO_LIODN
1456struct rio_liodn {
1457 u32 plbr;
1458 u8 res0[28];
1459 u32 plaor;
1460 u8 res1[12];
1461 u32 pludr;
1462 u32 plldr;
1463 u8 res2[456];
1464};
1465#endif
1466
1467
1468struct ccsr_rio {
1469 struct rio_arch arch;
1470 u8 res0[144];
1471 struct rio_lp_serial lp_serial;
1472 u8 res1[1152];
1473 struct rio_logical_err logical_err;
1474 u8 res2[32];
1475 struct rio_phys_err phys_err;
1476 u8 res3[63808];
1477 struct rio_implement impl;
1478 u8 res4[2552];
1479 struct rio_rev_ctrl rev;
1480 struct rio_atmu atmu;
1481#ifdef CONFIG_SYS_FSL_RMU
1482 u8 res5[8192];
1483 struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
1484 u8 res6[512];
1485 struct rio_dbell dbell;
1486 u8 res7[100];
1487 struct rio_pw pw;
1488#endif
1489#ifdef CONFIG_SYS_FSL_SRIO_LIODN
1490 u8 res5[8192];
1491 struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1492#endif
1493};
1494#endif
1495
1496
1497typedef struct par_io {
1498 u32 cpodr;
1499 u32 cpdat;
1500 u32 cpdir1;
1501 u32 cpdir2;
1502 u32 cppar1;
1503 u32 cppar2;
1504 u8 res[8];
1505} par_io_t;
1506
1507#ifdef CONFIG_SYS_FSL_CPC
1508
1509
1510
1511
1512
1513
1514typedef struct cpc_corenet {
1515 u32 cpccsr0;
1516 u32 res1;
1517 u32 cpccfg0;
1518 u32 res2;
1519 u32 cpcewcr0;
1520 u32 cpcewabr0;
1521 u32 res3[2];
1522 u32 cpcewcr1;
1523 u32 cpcewabr1;
1524 u32 res4[54];
1525 u32 cpcsrcr1;
1526 u32 cpcsrcr0;
1527 u32 res5[62];
1528 struct {
1529 u32 id;
1530 u32 res;
1531 u32 alloc;
1532 u32 way;
1533 } partition_regs[16];
1534 u32 res6[704];
1535 u32 cpcerrinjhi;
1536 u32 cpcerrinjlo;
1537 u32 cpcerrinjctl;
1538 u32 res7[5];
1539 u32 cpccaptdatahi;
1540 u32 cpccaptdatalo;
1541 u32 cpcaptecc;
1542 u32 res8[5];
1543 u32 cpcerrdet;
1544 u32 cpcerrdis;
1545 u32 cpcerrinten;
1546 u32 cpcerrattr;
1547 u32 cpcerreaddr;
1548 u32 cpcerraddr;
1549 u32 cpcerrctl;
1550 u32 res9[41];
1551 u32 cpchdbcr0;
1552 u32 res10[63];
1553} cpc_corenet_t;
1554
1555#define CPC_CSR0_CE 0x80000000
1556#define CPC_CSR0_PE 0x40000000
1557#define CPC_CSR0_FI 0x00200000
1558#define CPC_CSR0_WT 0x00080000
1559#define CPC_CSR0_FL 0x00000800
1560#define CPC_CSR0_LFC 0x00000400
1561#define CPC_CFG0_SZ_MASK 0x00003fff
1562#define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
1563#define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
1564#define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
1565#define CPC_SRCR1_SRBARU_MASK 0x0000ffff
1566#define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
1567 & CPC_SRCR1_SRBARU_MASK)
1568#define CPC_SRCR0_SRBARL_MASK 0xffff8000
1569#define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
1570#define CPC_SRCR0_INTLVEN 0x00000100
1571#define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
1572#define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
1573#define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
1574#define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
1575#define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
1576#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
1577#define CPC_SRCR0_SRAMEN 0x00000001
1578#define CPC_ERRDIS_TMHITDIS 0x00000080
1579#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
1580#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
1581#define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
1582#define CPC_HDBCR0_SPLRU_LEVEL_EN 0x001e0000
1583#endif
1584
1585
1586#ifdef CONFIG_FSL_CORENET
1587typedef struct ccsr_gur {
1588 u32 porsr1;
1589 u32 porsr2;
1590#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
1591#define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15
1592#define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1
1593#define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1
1594#define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0
1595#endif
1596 u8 res_008[0x20-0x8];
1597 u32 gpporcr1;
1598 u32 gpporcr2;
1599 u32 dcfg_fusesr;
1600#define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25
1601#define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F
1602#define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20
1603#define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F
1604 u8 res_02c[0x70-0x2c];
1605 u32 devdisr;
1606 u32 devdisr2;
1607 u32 devdisr3;
1608 u32 devdisr4;
1609#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1610 u32 devdisr5;
1611#define FSL_CORENET_DEVDISR_PBL 0x80000000
1612#define FSL_CORENET_DEVDISR_PMAN 0x40000000
1613#define FSL_CORENET_DEVDISR_ESDHC 0x20000000
1614#define FSL_CORENET_DEVDISR_DMA1 0x00800000
1615#define FSL_CORENET_DEVDISR_DMA2 0x00400000
1616#define FSL_CORENET_DEVDISR_USB1 0x00080000
1617#define FSL_CORENET_DEVDISR_USB2 0x00040000
1618#define FSL_CORENET_DEVDISR_SATA1 0x00008000
1619#define FSL_CORENET_DEVDISR_SATA2 0x00004000
1620#define FSL_CORENET_DEVDISR_PME 0x00000800
1621#define FSL_CORENET_DEVDISR_SEC 0x00000200
1622#define FSL_CORENET_DEVDISR_RMU 0x00000080
1623#define FSL_CORENET_DEVDISR_DCE 0x00000040
1624#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000
1625#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000
1626#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000
1627#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000
1628#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000
1629#define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
1630#define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
1631#define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
1632#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
1633#define FSL_CORENET_DEVDISR2_10GEC1_1 0x80000000
1634#define FSL_CORENET_DEVDISR2_10GEC1_2 0x40000000
1635#else
1636#define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
1637#define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
1638#define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000
1639#define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000
1640#endif
1641#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
1642#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
1643#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
1644#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000
1645#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000
1646#define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000
1647#define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800
1648#define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400
1649#define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800
1650#define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400
1651#define FSL_CORENET_DEVDISR2_FM1 0x00000080
1652#define FSL_CORENET_DEVDISR2_FM2 0x00000040
1653#define FSL_CORENET_DEVDISR2_CPRI 0x00000008
1654#define FSL_CORENET_DEVDISR3_PCIE1 0x80000000
1655#define FSL_CORENET_DEVDISR3_PCIE2 0x40000000
1656#define FSL_CORENET_DEVDISR3_PCIE3 0x20000000
1657#define FSL_CORENET_DEVDISR3_PCIE4 0x10000000
1658#define FSL_CORENET_DEVDISR3_SRIO1 0x08000000
1659#define FSL_CORENET_DEVDISR3_SRIO2 0x04000000
1660#define FSL_CORENET_DEVDISR3_QMAN 0x00080000
1661#define FSL_CORENET_DEVDISR3_BMAN 0x00040000
1662#define FSL_CORENET_DEVDISR3_LA1 0x00008000
1663#define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800
1664#define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400
1665#define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200
1666#define FSL_CORENET_DEVDISR4_I2C1 0x80000000
1667#define FSL_CORENET_DEVDISR4_I2C2 0x40000000
1668#define FSL_CORENET_DEVDISR4_DUART1 0x20000000
1669#define FSL_CORENET_DEVDISR4_DUART2 0x10000000
1670#define FSL_CORENET_DEVDISR4_ESPI 0x08000000
1671#define FSL_CORENET_DEVDISR5_DDR1 0x80000000
1672#define FSL_CORENET_DEVDISR5_DDR2 0x40000000
1673#define FSL_CORENET_DEVDISR5_DDR3 0x20000000
1674#define FSL_CORENET_DEVDISR5_CPC1 0x08000000
1675#define FSL_CORENET_DEVDISR5_CPC2 0x04000000
1676#define FSL_CORENET_DEVDISR5_CPC3 0x02000000
1677#define FSL_CORENET_DEVDISR5_IFC 0x00800000
1678#define FSL_CORENET_DEVDISR5_GPIO 0x00400000
1679#define FSL_CORENET_DEVDISR5_DBG 0x00200000
1680#define FSL_CORENET_DEVDISR5_NAL 0x00100000
1681#define FSL_CORENET_DEVDISR5_TIMERS 0x00020000
1682#define FSL_CORENET_NUM_DEVDISR 5
1683#else
1684#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
1685#define FSL_CORENET_DEVDISR_PCIE2 0x40000000
1686#define FSL_CORENET_DEVDISR_PCIE3 0x20000000
1687#define FSL_CORENET_DEVDISR_PCIE4 0x10000000
1688#define FSL_CORENET_DEVDISR_RMU 0x08000000
1689#define FSL_CORENET_DEVDISR_SRIO1 0x04000000
1690#define FSL_CORENET_DEVDISR_SRIO2 0x02000000
1691#define FSL_CORENET_DEVDISR_DMA1 0x00400000
1692#define FSL_CORENET_DEVDISR_DMA2 0x00200000
1693#define FSL_CORENET_DEVDISR_DDR1 0x00100000
1694#define FSL_CORENET_DEVDISR_DDR2 0x00080000
1695#define FSL_CORENET_DEVDISR_DBG 0x00010000
1696#define FSL_CORENET_DEVDISR_NAL 0x00008000
1697#define FSL_CORENET_DEVDISR_SATA1 0x00004000
1698#define FSL_CORENET_DEVDISR_SATA2 0x00002000
1699#define FSL_CORENET_DEVDISR_ELBC 0x00001000
1700#define FSL_CORENET_DEVDISR_USB1 0x00000800
1701#define FSL_CORENET_DEVDISR_USB2 0x00000400
1702#define FSL_CORENET_DEVDISR_ESDHC 0x00000100
1703#define FSL_CORENET_DEVDISR_GPIO 0x00000080
1704#define FSL_CORENET_DEVDISR_ESPI 0x00000040
1705#define FSL_CORENET_DEVDISR_I2C1 0x00000020
1706#define FSL_CORENET_DEVDISR_I2C2 0x00000010
1707#define FSL_CORENET_DEVDISR_DUART1 0x00000002
1708#define FSL_CORENET_DEVDISR_DUART2 0x00000001
1709#define FSL_CORENET_DEVDISR2_PME 0x80000000
1710#define FSL_CORENET_DEVDISR2_SEC 0x40000000
1711#define FSL_CORENET_DEVDISR2_QMBM 0x08000000
1712#define FSL_CORENET_DEVDISR2_FM1 0x02000000
1713#define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
1714#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
1715#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
1716#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
1717#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
1718#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
1719#define FSL_CORENET_DEVDISR2_FM2 0x00020000
1720#define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
1721#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
1722#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
1723#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
1724#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
1725#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
1726#define FSL_CORENET_NUM_DEVDISR 2
1727 u32 powmgtcsr;
1728#endif
1729 u8 res8[12];
1730 u32 coredisru;
1731 u32 coredisrl;
1732 u8 res9[8];
1733 u32 pvr;
1734 u32 svr;
1735 u8 res10[8];
1736 u32 rstcr;
1737 u32 rstrqpblsr;
1738 u8 res11[8];
1739 u32 rstrqmr1;
1740#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1741#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800
1742#endif
1743 u8 res12[4];
1744 u32 rstrqsr1;
1745 u8 res13[4];
1746 u8 res14[4];
1747 u32 rstrqwdtmrl;
1748 u8 res15[4];
1749 u32 rstrqwdtsrl;
1750 u8 res16[4];
1751 u32 brrl;
1752 u8 res17[24];
1753 u32 rcwsr[16];
1754#define RCW_SB_EN_REG_INDEX 7
1755#define RCW_SB_EN_MASK 0x00200000
1756
1757#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1758#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
1759
1760#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
1761#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
1762#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
1763#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
1764#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
1765#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1766#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1767#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800
1768#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
1769#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
1770#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
1771#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1772#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
1773#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
1774#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
1775#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1776#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
1777#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1778#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
1779#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1780#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1781#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1782#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1783#define FSL_CORENET_RCWSR13_EC1 0x30000000
1784#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000
1785#define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000
1786#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000
1787#define FSL_CORENET_RCWSR13_EC2 0x0c000000
1788#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1789#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
1790#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000
1791#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
1792#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
1793#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000
1794#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
1795#define PXCKEN_MASK 0x80000000
1796#define PXCK_MASK 0x00FF0000
1797#define PXCK_BITS_START 16
1798#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
1799#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
1800#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23
1801#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1802#define FSL_CORENET_RCWSR13_EC1 0x30000000
1803#define FSL_CORENET_RCWSR13_EC1_RGMII 0x00000000
1804#define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000
1805#define FSL_CORENET_RCWSR13_EC2 0x0c000000
1806#define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000
1807#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
1808#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00
1809#define PXCKEN_MASK 0x80000000
1810#define PXCK_MASK 0x00FF0000
1811#define PXCK_BITS_START 16
1812#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
1813#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1814#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1815#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1816#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
1817#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1818#endif
1819#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
1820#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
1821#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000
1822#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000
1823#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000
1824#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
1825#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
1826#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
1827#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
1828#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011
1829#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1
1830
1831#else
1832#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17
1833#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f
1834#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
1835#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
1836#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
1837#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
1838#define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000
1839#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1840#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000
1841#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000
1842#endif
1843
1844#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
1845#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
1846#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
1847#define FSL_CORENET_RCWSR11_EC1 0x00c00000
1848#ifdef CONFIG_ARCH_P4080
1849#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
1850#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
1851#define FSL_CORENET_RCWSR11_EC2 0x001c0000
1852#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
1853#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
1854#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
1855#endif
1856#if defined(CONFIG_ARCH_P2041) || \
1857 defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020)
1858#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
1859#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
1860#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
1861#define FSL_CORENET_RCWSR11_EC2 0x00180000
1862#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000
1863#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
1864#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
1865#endif
1866#if defined(CONFIG_ARCH_P5040)
1867#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
1868#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
1869#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
1870#define FSL_CORENET_RCWSR11_EC2 0x00180000
1871#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000
1872#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
1873#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
1874#endif
1875#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
1876#define FSL_CORENET_RCWSR13_EC1 0x60000000
1877#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
1878#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
1879#define FSL_CORENET_RCWSR13_EC2 0x18000000
1880#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1881#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
1882#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
1883#endif
1884#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
1885#define FSL_CORENET_RCWSR13_EC1 0x60000000
1886#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
1887#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
1888#define FSL_CORENET_RCWSR13_EC2 0x18000000
1889#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
1890#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000
1891#define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000
1892#endif
1893 u8 res18[192];
1894 u32 scratchrw[4];
1895 u8 res19[240];
1896 u32 scratchw1r[4];
1897 u8 res20[240];
1898 u32 scrtsr[8];
1899 u8 res21[224];
1900 u32 pex1liodnr;
1901 u32 pex2liodnr;
1902 u32 pex3liodnr;
1903 u32 pex4liodnr;
1904 u32 rio1liodnr;
1905 u32 rio2liodnr;
1906 u32 rio3liodnr;
1907 u32 rio4liodnr;
1908 u32 usb1liodnr;
1909 u32 usb2liodnr;
1910 u32 usb3liodnr;
1911 u32 usb4liodnr;
1912 u32 sdmmc1liodnr;
1913 u32 sdmmc2liodnr;
1914 u32 sdmmc3liodnr;
1915 u32 sdmmc4liodnr;
1916 u32 rio1maintliodnr;
1917 u32 rio2maintliodnr;
1918 u32 rio3maintliodnr;
1919 u32 rio4maintliodnr;
1920 u32 sata1liodnr;
1921 u32 sata2liodnr;
1922 u32 sata3liodnr;
1923 u32 sata4liodnr;
1924 u8 res22[20];
1925 u32 tdmliodnr;
1926 u32 qeliodnr;
1927 u8 res_57c[4];
1928 u32 dma1liodnr;
1929 u32 dma2liodnr;
1930 u32 dma3liodnr;
1931 u32 dma4liodnr;
1932 u8 res23[48];
1933 u8 res24[64];
1934 u32 pblsr;
1935 u32 pamubypenr;
1936 u32 dmacr1;
1937 u8 res25[4];
1938 u32 gensr1;
1939 u8 res26[12];
1940 u32 gencr1;
1941 u8 res27[12];
1942 u8 res28[4];
1943 u32 cgensrl;
1944 u8 res29[8];
1945 u8 res30[4];
1946 u32 cgencrl;
1947 u8 res31[184];
1948 u32 sriopstecr;
1949 u32 dcsrcr;
1950 u8 res31a[56];
1951 u32 tp_ityp[64];
1952 struct {
1953 u32 upper;
1954 u32 lower;
1955 } tp_cluster[16];
1956 u8 res32[1344];
1957 u32 pmuxcr;
1958 u8 res33[60];
1959 u32 iovselsr;
1960 u8 res34[28];
1961 u32 ddrclkdr;
1962 u8 res35;
1963 u32 elbcclkdr;
1964 u8 res36[20];
1965 u32 sdhcpcr;
1966 u8 res37[380];
1967} ccsr_gur_t;
1968
1969#define TP_ITYP_AV 0x00000001
1970#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1)
1971#define TP_ITYP_TYPE_OTHER 0x0
1972#define TP_ITYP_TYPE_PPC 0x1
1973#define TP_ITYP_TYPE_SC 0x2
1974#define TP_ITYP_TYPE_HA 0x3
1975#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3)
1976#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5)
1977
1978#define TP_CLUSTER_EOC 0x80000000
1979#define TP_CLUSTER_INIT_MASK 0x0000003f
1980#define TP_INIT_PER_CLUSTER 4
1981
1982#define FSL_CORENET_DCSR_SZ_MASK 0x00000003
1983#define FSL_CORENET_DCSR_SZ_4M 0x0
1984#define FSL_CORENET_DCSR_SZ_1G 0x3
1985
1986
1987
1988
1989
1990#define rmuliodnr rio1maintliodnr
1991
1992typedef struct ccsr_clk {
1993 struct {
1994 u32 clkcncsr;
1995 u8 res_004[0x0c];
1996 u32 clkcgnhwacsr;
1997 u8 res_014[0x0c];
1998 } clkcsr[12];
1999 u8 res_100[0x680];
2000 struct {
2001 u32 pllcngsr;
2002 u8 res10[0x1c];
2003 } pllcgsr[12];
2004 u8 res21[0x280];
2005 u32 pllpgsr;
2006 u8 res16[0x1c];
2007 u32 plldgsr;
2008 u8 res17[0x3dc];
2009} ccsr_clk_t;
2010
2011#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2012typedef struct ccsr_rcpm {
2013 u8 res_00[12];
2014 u32 tph10sr0;
2015 u8 res_10[12];
2016 u32 tph10setr0;
2017 u8 res_20[12];
2018 u32 tph10clrr0;
2019 u8 res_30[12];
2020 u32 tph10psr0;
2021 u8 res_40[12];
2022 u32 twaitsr0;
2023 u8 res_50[96];
2024 u32 pcph15sr;
2025 u32 pcph15setr;
2026 u32 pcph15clrr;
2027 u32 pcph15psr;
2028 u8 res_c0[16];
2029 u32 pcph20sr;
2030 u32 pcph20setr;
2031 u32 pcph20clrr;
2032 u32 pcph20psr;
2033 u32 pcpw20sr;
2034 u8 res_e0[12];
2035 u32 pcph30sr;
2036 u32 pcph30setr;
2037 u32 pcph30clrr;
2038 u32 pcph30psr;
2039 u8 res_100[32];
2040 u32 ippwrgatecr;
2041 u8 res_124[12];
2042 u32 powmgtcsr;
2043 u8 res_134[12];
2044 u32 ippdexpcr[4];
2045 u8 res_150[12];
2046 u32 tpmimr0;
2047 u8 res_160[12];
2048 u32 tpmcimr0;
2049 u8 res_170[12];
2050 u32 tpmmcmr0;
2051 u8 res_180[12];
2052 u32 tpmnmimr0;
2053 u8 res_190[12];
2054 u32 tmcpmaskcr0;
2055 u32 pctbenr;
2056 u32 pctbclkselr;
2057 u32 tbclkdivr;
2058 u8 res_1ac[4];
2059 u32 ttbhltcr[4];
2060 u32 clpcl10sr;
2061 u32 clpcl10setr;
2062 u32 clpcl10clrr;
2063 u32 clpcl10psr;
2064 u32 cddslpsetr;
2065 u32 cddslpclrr;
2066 u32 cdpwroksetr;
2067 u32 cdpwrokclrr;
2068 u32 cdpwrensr;
2069 u32 cddslsr;
2070 u8 res_1e8[8];
2071 u32 dslpcntcr[8];
2072 u8 res_300[3568];
2073} ccsr_rcpm_t;
2074
2075#define ctbenrl pctbenr
2076
2077#else
2078typedef struct ccsr_rcpm {
2079 u8 res1[4];
2080 u32 cdozsrl;
2081 u8 res2[4];
2082 u32 cdozcrl;
2083 u8 res3[4];
2084 u32 cnapsrl;
2085 u8 res4[4];
2086 u32 cnapcrl;
2087 u8 res5[4];
2088 u32 cdozpsrl;
2089 u8 res6[4];
2090 u32 cdozpcrl;
2091 u8 res7[4];
2092 u32 cwaitsrl;
2093 u8 res8[8];
2094 u32 powmgtcsr;
2095 u8 res9[12];
2096 u32 ippdexpcr0;
2097 u8 res10[12];
2098 u8 res11[4];
2099 u32 cpmimrl;
2100 u8 res12[4];
2101 u32 cpmcimrl;
2102 u8 res13[4];
2103 u32 cpmmcimrl;
2104 u8 res14[4];
2105 u32 cpmnmimrl;
2106 u8 res15[4];
2107 u32 ctbenrl;
2108 u8 res16[4];
2109 u32 ctbclkselrl;
2110 u8 res17[4];
2111 u32 ctbhltcrl;
2112 u8 res18[0xf68];
2113} ccsr_rcpm_t;
2114#endif
2115
2116#else
2117typedef struct ccsr_gur {
2118 u32 porpllsr;
2119#ifdef CONFIG_ARCH_MPC8536
2120#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
2121#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
2122#elif defined(CONFIG_ARCH_C29X)
2123#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2124#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
2125 & MPC85xx_PORDEVSR2_DDR_SPD_0) \
2126 >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
2127#else
2128#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
2129#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2130#else
2131#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
2132#endif
2133#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
2134#endif
2135#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
2136#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
2137#define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
2138#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
2139 u32 porbmsr;
2140#define MPC85xx_PORBMSR_HA 0x00070000
2141#define MPC85xx_PORBMSR_HA_SHIFT 16
2142#define MPC85xx_PORBMSR_ROMLOC_SHIFT 24
2143#define PORBMSR_ROMLOC_SPI 0x6
2144#define PORBMSR_ROMLOC_SDHC 0x7
2145#define PORBMSR_ROMLOC_NAND_2K 0x9
2146#define PORBMSR_ROMLOC_NOR 0xf
2147 u32 porimpscr;
2148 u32 pordevsr;
2149#if defined(CONFIG_ARCH_P1023)
2150#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
2151#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
2152#define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
2153#else
2154#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
2155#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
2156#endif
2157#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
2158#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
2159#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
2160#define MPC85xx_PORDEVSR_PCI1 0x00800000
2161#if defined(CONFIG_ARCH_P1022)
2162#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
2163#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
2164#elif defined(CONFIG_ARCH_P1023)
2165#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2166#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2167#else
2168#if defined(CONFIG_ARCH_P1010)
2169#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2170#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2171#elif defined(CONFIG_ARCH_BSC9132)
2172#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
2173#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
2174#elif defined(CONFIG_ARCH_C29X)
2175#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
2176#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2177#else
2178#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
2179#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
2180#endif
2181#endif
2182#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
2183#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
2184#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
2185#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
2186#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
2187#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
2188#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
2189#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
2190 u32 pordbgmsr;
2191 u32 pordevsr2;
2192#if defined(CONFIG_ARCH_C29X)
2193#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
2194#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
2195#endif
2196#define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000
2197
2198#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
2199 u8 res1[8];
2200 u32 gpporcr;
2201 u8 res2[12];
2202#if defined(CONFIG_ARCH_MPC8536)
2203 u32 gencfgr;
2204#define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
2205#else
2206 u32 gpiocr;
2207#endif
2208 u8 res3[12];
2209#if defined(CONFIG_ARCH_MPC8569)
2210 u32 plppar1;
2211 u32 plppar2;
2212 u32 plpdir1;
2213 u32 plpdir2;
2214#else
2215 u32 gpoutdr;
2216 u8 res4[12];
2217#endif
2218 u32 gpindr;
2219 u8 res5[12];
2220 u32 pmuxcr;
2221#if defined(CONFIG_ARCH_P1010)
2222#define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
2223#define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
2224#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
2225#define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000
2226#define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000
2227#define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000
2228#define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000
2229#define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000
2230#define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000
2231#define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000
2232#define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000
2233#define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000
2234#define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000
2235#define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000
2236#define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000
2237#define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000
2238#define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000
2239#define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000
2240#define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000
2241#define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
2242#define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000
2243#define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000
2244#define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000
2245#define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000
2246#define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000
2247#define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000
2248#define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000
2249#define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000
2250#define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400
2251#define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800
2252#define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00
2253#define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300
2254#define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200
2255#define MPC85xx_PMUXCR_LCLK_RES 0x00000040
2256#define MPC85xx_PMUXCR_LCLK_USB 0x00000080
2257#define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
2258#define MPC85xx_PMUXCR_SPI_RES 0x00000030
2259#define MPC85xx_PMUXCR_SPI_GPIO 0x00000020
2260#define MPC85xx_PMUXCR_CAN1_UART 0x00000004
2261#define MPC85xx_PMUXCR_CAN1_TDM 0x00000008
2262#define MPC85xx_PMUXCR_CAN1_RES 0x0000000C
2263#define MPC85xx_PMUXCR_CAN2_UART 0x00000001
2264#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
2265#define MPC85xx_PMUXCR_CAN2_RES 0x00000003
2266#endif
2267#if defined(CONFIG_ARCH_P1023)
2268#define MPC85xx_PMUXCR_TSEC1_1 0x10000000
2269#else
2270#define MPC85xx_PMUXCR_SD_DATA 0x80000000
2271#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
2272#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
2273#define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000
2274#define MPC85xx_PMUXCR_TDM_ENA 0x00800000
2275#define MPC85xx_PMUXCR_QE0 0x00008000
2276#define MPC85xx_PMUXCR_QE1 0x00004000
2277#define MPC85xx_PMUXCR_QE2 0x00002000
2278#define MPC85xx_PMUXCR_QE3 0x00001000
2279#define MPC85xx_PMUXCR_QE4 0x00000800
2280#define MPC85xx_PMUXCR_QE5 0x00000400
2281#define MPC85xx_PMUXCR_QE6 0x00000200
2282#define MPC85xx_PMUXCR_QE7 0x00000100
2283#define MPC85xx_PMUXCR_QE8 0x00000080
2284#define MPC85xx_PMUXCR_QE9 0x00000040
2285#define MPC85xx_PMUXCR_QE10 0x00000020
2286#define MPC85xx_PMUXCR_QE11 0x00000010
2287#define MPC85xx_PMUXCR_QE12 0x00000008
2288#endif
2289#if defined(CONFIG_ARCH_P1022)
2290#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
2291#define MPC85xx_PMUXCR_TDM 0x00014800
2292#define MPC85xx_PMUXCR_SPI_MASK 0x00600000
2293#define MPC85xx_PMUXCR_SPI 0x00000000
2294#endif
2295#if defined(CONFIG_ARCH_BSC9131)
2296#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
2297#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
2298#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
2299#define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000
2300#define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000
2301#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000
2302#define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000
2303#define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000
2304#define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000
2305#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000
2306#define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000
2307#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000
2308#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000
2309#define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000
2310#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000
2311#define MPC85xx_PMUXCR_SDHC_USIM 0x00010000
2312#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000
2313#define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000
2314#define MPC85xx_PMUXCR_SDHC_RESV 0x00004000
2315#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000
2316#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000
2317#define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000
2318#define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000
2319#define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000
2320#define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400
2321#define MPC85xx_PMUXCR_USB_RSVD 0x00000C00
2322#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800
2323#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100
2324#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200
2325#define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300
2326#define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040
2327#define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080
2328#define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0
2329#define MPC85xx_PMUXCR_SPI1_UART3 0x00000010
2330#define MPC85xx_PMUXCR_SPI1_SIM 0x00000020
2331#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030
2332#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004
2333#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008
2334#define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C
2335#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
2336#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
2337#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
2338#endif
2339#ifdef CONFIG_ARCH_BSC9132
2340#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
2341#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
2342#endif
2343#if defined(CONFIG_ARCH_C29X)
2344#define MPC85xx_PMUXCR_SPI_MASK 0x00000300
2345#define MPC85xx_PMUXCR_SPI 0x00000000
2346#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
2347#endif
2348 u32 pmuxcr2;
2349#if defined(CONFIG_ARCH_P1010)
2350#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
2351#define MPC85xx_PMUXCR2_UART_TDM 0x80000000
2352#define MPC85xx_PMUXCR2_UART_RES 0xC0000000
2353#define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000
2354#define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000
2355#define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000
2356#define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000
2357#define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000
2358#define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000
2359#define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000
2360#define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000
2361#define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000
2362#define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000
2363#define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000
2364#define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000
2365#define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000
2366#define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000
2367#define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000
2368#define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000
2369#define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000
2370#define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000
2371#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
2372#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
2373#endif
2374#if defined(CONFIG_ARCH_P1022)
2375#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
2376#define MPC85xx_PMUXCR2_USB 0x00150000
2377#endif
2378#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
2379#if defined(CONFIG_ARCH_BSC9131)
2380#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
2381#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
2382#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
2383#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000
2384#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000
2385#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000
2386#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000
2387#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000
2388#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000
2389#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000
2390#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000
2391#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000
2392#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000
2393#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000
2394#define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000
2395#define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000
2396#define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000
2397#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000
2398#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000
2399#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000
2400#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000
2401#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000
2402#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000
2403#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000
2404#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000
2405#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000
2406#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000
2407#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000
2408#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000
2409#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400
2410#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800
2411#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00
2412#define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100
2413#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300
2414#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040
2415#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0
2416#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010
2417#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020
2418#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030
2419#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
2420#define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
2421#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
2422#endif
2423 u32 pmuxcr3;
2424#if defined(CONFIG_ARCH_BSC9131)
2425#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
2426#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
2427#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
2428#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000
2429#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000
2430#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000
2431#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000
2432#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000
2433#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000
2434#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000
2435#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000
2436#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
2437#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
2438#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
2439#endif
2440#ifdef CONFIG_ARCH_BSC9132
2441#define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
2442#define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
2443#define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
2444#define MPC85xx_PMUXCR3_UART3_SEL 0x40000000
2445#endif
2446 u32 pmuxcr4;
2447#else
2448 u8 res6[8];
2449#endif
2450 u32 devdisr;
2451#define MPC85xx_DEVDISR_PCI1 0x80000000
2452#define MPC85xx_DEVDISR_PCI2 0x40000000
2453#define MPC85xx_DEVDISR_PCIE 0x20000000
2454#define MPC85xx_DEVDISR_LBC 0x08000000
2455#define MPC85xx_DEVDISR_PCIE2 0x04000000
2456#define MPC85xx_DEVDISR_PCIE3 0x02000000
2457#define MPC85xx_DEVDISR_SEC 0x01000000
2458#define MPC85xx_DEVDISR_SRIO 0x00080000
2459#define MPC85xx_DEVDISR_RMSG 0x00040000
2460#define MPC85xx_DEVDISR_DDR 0x00010000
2461#define MPC85xx_DEVDISR_CPU 0x00008000
2462#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
2463#define MPC85xx_DEVDISR_TB 0x00004000
2464#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
2465#define MPC85xx_DEVDISR_CPU1 0x00002000
2466#define MPC85xx_DEVDISR_TB1 0x00001000
2467#define MPC85xx_DEVDISR_DMA 0x00000400
2468#define MPC85xx_DEVDISR_TSEC1 0x00000080
2469#define MPC85xx_DEVDISR_TSEC2 0x00000040
2470#define MPC85xx_DEVDISR_TSEC3 0x00000020
2471#define MPC85xx_DEVDISR_TSEC4 0x00000010
2472#define MPC85xx_DEVDISR_I2C 0x00000004
2473#define MPC85xx_DEVDISR_DUART 0x00000002
2474 u8 res7[12];
2475 u32 powmgtcsr;
2476 u8 res8[12];
2477 u32 mcpsumr;
2478 u8 res9[12];
2479 u32 pvr;
2480 u32 svr;
2481 u8 res10[8];
2482 u32 rstcr;
2483#if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569)
2484 u8 res11a[76];
2485 par_io_t qe_par_io[7];
2486 u8 res11b[1600];
2487#elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
2488 u8 res11a[12];
2489 u32 iovselsr;
2490 u8 res11b[60];
2491 par_io_t qe_par_io[3];
2492 u8 res11c[1496];
2493#else
2494 u8 res11a[1868];
2495#endif
2496 u32 clkdvdr;
2497 u8 res12[1532];
2498 u32 clkocr;
2499 u8 res13[12];
2500 u32 ddrdllcr;
2501 u8 res14[12];
2502 u32 lbcdllcr;
2503#if defined(CONFIG_ARCH_BSC9131)
2504 u8 res15[12];
2505 u32 halt_req_mask;
2506#define HALTED_TO_HALT_REQ_MASK_0 0x80000000
2507 u8 res18[232];
2508#else
2509 u8 res15[248];
2510#endif
2511 u32 lbiuiplldcr0;
2512 u32 lbiuiplldcr1;
2513 u32 ddrioovcr;
2514 u32 tsec12ioovcr;
2515 u32 tsec34ioovcr;
2516 u8 res16[52];
2517 u32 sdhcdcr;
2518 u8 res17[61592];
2519} ccsr_gur_t;
2520#endif
2521
2522#define SDHCDCR_CD_INV 0x80000000
2523
2524#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2525#define MAX_SERDES 4
2526#define SRDS_MAX_LANES 8
2527#define SRDS_MAX_BANK 2
2528typedef struct serdes_corenet {
2529 struct {
2530 u32 rstctl;
2531#define SRDS_RSTCTL_RST 0x80000000
2532#define SRDS_RSTCTL_RSTDONE 0x40000000
2533#define SRDS_RSTCTL_RSTERR 0x20000000
2534#define SRDS_RSTCTL_SWRST 0x10000000
2535#define SRDS_RSTCTL_SDEN 0x00000020
2536#define SRDS_RSTCTL_SDRST_B 0x00000040
2537#define SRDS_RSTCTL_PLLRST_B 0x00000080
2538#define SRDS_RSTCTL_RSTERR_SHIFT 29
2539 u32 pllcr0;
2540#define SRDS_PLLCR0_POFF 0x80000000
2541#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2542#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2543#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2544#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2545#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2546#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2547#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
2548#define SRDS_PLLCR0_PLL_LCK 0x00800000
2549#define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000
2550#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
2551#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2552#define SRDS_PLLCR0_FRATE_SEL_4_9152 0x00030000
2553#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
2554#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
2555#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
2556#define SRDS_PLLCR0_FRATE_SEL_3_125 0x00090000
2557#define SRDS_PLLCR0_FRATE_SEL_3_0 0x000a0000
2558#define SRDS_PLLCR0_FRATE_SEL_3_072 0x000c0000
2559#define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0
2560#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4
2561 u32 pllcr1;
2562#define SRDS_PLLCR1_BCAP_EN 0x20000000
2563#define SRDS_PLLCR1_BCAP_OVD 0x10000000
2564#define SRDS_PLLCR1_PLL_FCAP 0x001F8000
2565#define SRDS_PLLCR1_PLL_FCAP_SHIFT 15
2566#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2567#define SRDS_PLLCR1_BYP_CAL 0x02000000
2568 u32 pllsr2;
2569#define SRDS_PLLSR2_BCAP_EN 0x00800000
2570#define SRDS_PLLSR2_BCAP_EN_SHIFT 23
2571#define SRDS_PLLSR2_FCAP 0x003F0000
2572#define SRDS_PLLSR2_FCAP_SHIFT 16
2573#define SRDS_PLLSR2_DCBIAS 0x000F0000
2574#define SRDS_PLLSR2_DCBIAS_SHIFT 16
2575 u32 pllcr3;
2576 u32 pllcr4;
2577 u8 res_18[0x20-0x18];
2578 } bank[2];
2579 u8 res_40[0x90-0x40];
2580 u32 srdstcalcr;
2581 u8 res_94[0xa0-0x94];
2582 u32 srdsrcalcr;
2583 u8 res_a4[0xb0-0xa4];
2584 u32 srdsgr0;
2585 u8 res_b4[0xe0-0xb4];
2586 u32 srdspccr0;
2587 u32 srdspccr1;
2588 u32 srdspccr2;
2589 u32 srdspccr3;
2590 u32 srdspccr4;
2591 u8 res_f4[0x100-0xf4];
2592 struct {
2593 u32 lnpssr;
2594 u8 res_104[0x120-0x104];
2595 } srdslnpssr[8];
2596 u8 res_200[0x800-0x200];
2597 struct {
2598 u32 gcr0;
2599 u32 gcr1;
2600 u32 gcr2;
2601 u32 res_80c;
2602 u32 recr0;
2603 u32 res_814;
2604 u32 tecr0;
2605 u32 res_81c;
2606 u32 ttlcr0;
2607 u8 res_824[0x840-0x824];
2608 } lane[8];
2609 u8 res_a00[0x1000-0xa00];
2610} serdes_corenet_t;
2611
2612#else
2613
2614#define SRDS_MAX_LANES 18
2615#define SRDS_MAX_BANK 3
2616typedef struct serdes_corenet {
2617 struct {
2618 u32 rstctl;
2619#define SRDS_RSTCTL_RST 0x80000000
2620#define SRDS_RSTCTL_RSTDONE 0x40000000
2621#define SRDS_RSTCTL_RSTERR 0x20000000
2622#define SRDS_RSTCTL_SDPD 0x00000020
2623 u32 pllcr0;
2624#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2625#define SRDS_PLLCR0_PVCOCNT_EN 0x02000000
2626#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2627#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2628#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2629#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2630#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2631#define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
2632#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2633#define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
2634 u32 pllcr1;
2635#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2636 u32 res[5];
2637 } bank[3];
2638 u32 res1[12];
2639 u32 srdstcalcr;
2640 u32 res2[3];
2641 u32 srdsrcalcr;
2642 u32 res3[3];
2643 u32 srdsgr0;
2644 u32 res4[11];
2645 u32 srdspccr0;
2646 u32 srdspccr1;
2647 u32 srdspccr2;
2648#define SRDS_PCCR2_RST_XGMII1 0x00800000
2649#define SRDS_PCCR2_RST_XGMII2 0x00400000
2650 u32 res5[197];
2651 struct serdes_lane {
2652 u32 gcr0;
2653#define SRDS_GCR0_RRST 0x00400000
2654#define SRDS_GCR0_1STLANE 0x00010000
2655#define SRDS_GCR0_UOTHL 0x00100000
2656 u32 gcr1;
2657#define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
2658#define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
2659#define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
2660#define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
2661#define SRDS_GCR1_OPAD_CTL 0x04000000
2662 u32 res1[4];
2663 u32 tecr0;
2664#define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
2665#define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
2666 u32 res3;
2667 u32 ttlcr0;
2668#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
2669#define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
2670#define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
2671#define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
2672#define SRDS_TTLCR0_PM_DIS 0x00004000
2673#define SRDS_TTLCR0_FREQOVD_EN 0x00000001
2674 u32 res4[7];
2675 } lane[24];
2676 u32 res6[384];
2677} serdes_corenet_t;
2678#endif
2679
2680enum {
2681 FSL_SRDS_B1_LANE_A = 0,
2682 FSL_SRDS_B1_LANE_B = 1,
2683 FSL_SRDS_B1_LANE_C = 2,
2684 FSL_SRDS_B1_LANE_D = 3,
2685 FSL_SRDS_B1_LANE_E = 4,
2686 FSL_SRDS_B1_LANE_F = 5,
2687 FSL_SRDS_B1_LANE_G = 6,
2688 FSL_SRDS_B1_LANE_H = 7,
2689 FSL_SRDS_B1_LANE_I = 8,
2690 FSL_SRDS_B1_LANE_J = 9,
2691 FSL_SRDS_B2_LANE_A = 16,
2692 FSL_SRDS_B2_LANE_B = 17,
2693 FSL_SRDS_B2_LANE_C = 18,
2694 FSL_SRDS_B2_LANE_D = 19,
2695 FSL_SRDS_B3_LANE_A = 20,
2696 FSL_SRDS_B3_LANE_B = 21,
2697 FSL_SRDS_B3_LANE_C = 22,
2698 FSL_SRDS_B3_LANE_D = 23,
2699};
2700
2701typedef struct ccsr_qman {
2702#ifdef CONFIG_SYS_FSL_QMAN_V3
2703 u8 res0[0x200];
2704#else
2705 struct {
2706 u32 qcsp_lio_cfg;
2707 u32 qcsp_io_cfg;
2708 u32 res;
2709 u32 qcsp_dd_cfg;
2710 } qcsp[32];
2711#endif
2712
2713 u8 res[0xbf8 - 0x200];
2714 u32 ip_rev_1;
2715 u32 ip_rev_2;
2716 u32 fqd_bare;
2717 u32 fqd_bar;
2718 u8 res1[0x8];
2719 u32 fqd_ar;
2720 u8 res2[0xc];
2721 u32 pfdr_bare;
2722 u32 pfdr_bar;
2723 u8 res3[0x8];
2724 u32 pfdr_ar;
2725 u8 res4[0x4c];
2726 u32 qcsp_bare;
2727 u32 qcsp_bar;
2728 u8 res5[0x78];
2729 u32 ci_sched_cfg;
2730 u32 srcidr;
2731 u32 liodnr;
2732 u8 res6[4];
2733 u32 ci_rlm_cfg;
2734 u32 ci_rlm_avg;
2735 u8 res7[0x2e8];
2736#ifdef CONFIG_SYS_FSL_QMAN_V3
2737 struct {
2738 u32 qcsp_lio_cfg;
2739 u32 qcsp_io_cfg;
2740 u32 res;
2741 u32 qcsp_dd_cfg;
2742 } qcsp[50];
2743#endif
2744} ccsr_qman_t;
2745
2746typedef struct ccsr_bman {
2747
2748 u8 res[0xbf8];
2749 u32 ip_rev_1;
2750 u32 ip_rev_2;
2751 u32 fbpr_bare;
2752 u32 fbpr_bar;
2753 u8 res1[0x8];
2754 u32 fbpr_ar;
2755 u8 res2[0xf0];
2756 u32 srcidr;
2757 u32 liodnr;
2758 u8 res7[0x2f4];
2759} ccsr_bman_t;
2760
2761typedef struct ccsr_pme {
2762 u8 res0[0x804];
2763 u32 liodnbr;
2764 u8 res1[0x1f8];
2765 u32 srcidr;
2766 u8 res2[8];
2767 u32 liodnr;
2768 u8 res3[0x1e8];
2769 u32 pm_ip_rev_1;
2770 u32 pm_ip_rev_2;
2771 u8 res4[0x400];
2772} ccsr_pme_t;
2773
2774struct ccsr_pamu {
2775 u32 ppbah;
2776 u32 ppbal;
2777 u32 pplah;
2778 u32 pplal;
2779 u32 spbah;
2780 u32 spbal;
2781 u32 splah;
2782 u32 splal;
2783 u32 obah;
2784 u32 obal;
2785 u32 olah;
2786 u32 olal;
2787};
2788
2789#ifdef CONFIG_SYS_FSL_RAID_ENGINE
2790struct ccsr_raide {
2791 u8 res0[0x543];
2792 u32 liodnbr;
2793 u8 res1[0xab8];
2794 struct {
2795 struct {
2796 u32 cfg0;
2797 u32 cfg1;
2798 u8 res1[0x3f8];
2799 } ring[2];
2800 u8 res[0x800];
2801 } jq[2];
2802};
2803#endif
2804
2805#ifdef CONFIG_SYS_DPAA_RMAN
2806struct ccsr_rman {
2807 u8 res0[0xf64];
2808 u32 mmliodnbr;
2809 u32 mmitar;
2810 u32 mmitdr;
2811 u8 res4[0x1f090];
2812};
2813#endif
2814
2815#ifdef CONFIG_SYS_PMAN
2816struct ccsr_pman {
2817 u8 res_00[0x40];
2818 u32 poes1;
2819 u32 poes2;
2820 u32 poeah;
2821 u32 poeal;
2822 u8 res_50[0x50];
2823 u32 pr1;
2824 u32 pr2;
2825 u8 res_a8[0x8];
2826 u32 pcap;
2827 u8 res_b4[0xc];
2828 u32 pc1;
2829 u32 pc2;
2830 u32 pc3;
2831 u32 pc4;
2832 u32 pc5;
2833 u32 pc6;
2834 u8 res_d8[0x8];
2835 u32 ppa1;
2836 u32 ppa2;
2837 u8 res_e8[0x8];
2838 u32 pics;
2839 u8 res_f4[0xf0c];
2840};
2841#endif
2842
2843#ifdef CONFIG_FSL_CORENET
2844#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
2845#ifdef CONFIG_SYS_PMAN
2846#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
2847#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
2848#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
2849#endif
2850#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
2851#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
2852#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
2853#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
2854#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
2855#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
2856
2857
2858#define CONFIG_SYS_OSPR_OFFSET 0x200
2859#define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
2860#else
2861#define CONFIG_SYS_SFP_OFFSET 0xE8000
2862#endif
2863#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
2864#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
2865#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
2866#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
2867#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
2868#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
2869#define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000
2870#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
2871#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
2872#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
2873#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
2874#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
2875#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
2876#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
2877#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
2878#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
2879#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
2880#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
2881#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
2882#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
2883 !defined(CONFIG_ARCH_B4420)
2884#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
2885#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
2886#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
2887#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
2888#else
2889#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
2890#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
2891#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
2892#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
2893#endif
2894#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
2895#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
2896#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
2897#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
2898#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
2899#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
2900#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
2901#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
2902#define CONFIG_SYS_SEC_MON_OFFSET 0x314000
2903#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
2904#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
2905#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
2906#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
2907#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
2908#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
2909#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
2910#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
2911#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
2912#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
2913#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
2914#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
2915#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
2916#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
2917#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
2918#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
2919#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
2920#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
2921#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
2922#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
2923#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
2924#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
2925#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
2926#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
2927#else
2928#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
2929#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
2930#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
2931#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
2932#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
2933#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
2934#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
2935#define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
2936#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
2937#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
2938#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
2939#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
2940#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
2941#else
2942#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
2943#endif
2944#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
2945#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
2946#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
2947#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
2948#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
2949#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
2950#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000
2951#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
2952#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000
2953#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
2954#ifdef CONFIG_TSECV2
2955#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
2956#elif defined(CONFIG_TSECV2_1)
2957#define CONFIG_SYS_TSEC1_OFFSET 0x10000
2958#else
2959#define CONFIG_SYS_TSEC1_OFFSET 0x24000
2960#endif
2961#define CONFIG_SYS_MDIO1_OFFSET 0x24000
2962#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
2963#if defined(CONFIG_ARCH_C29X)
2964#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
2965#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
2966#else
2967#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
2968#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000
2969#endif
2970#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
2971#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
2972#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000
2973#define CONFIG_SYS_SFP_OFFSET 0xE7000
2974#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
2975#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
2976#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
2977#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
2978#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
2979#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
2980#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
2981#endif
2982
2983#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
2984#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
2985#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
2986
2987#if defined(CONFIG_ARCH_BSC9132)
2988#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
2989#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
2990 (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
2991#endif
2992
2993#define CONFIG_SYS_FSL_CPC_ADDR \
2994 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
2995#define CONFIG_SYS_FSL_SCFG_ADDR \
2996 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
2997#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \
2998 (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
2999#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
3000 (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
3001#define CONFIG_SYS_FSL_QMAN_ADDR \
3002 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
3003#define CONFIG_SYS_FSL_BMAN_ADDR \
3004 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
3005#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
3006 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
3007#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
3008 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
3009#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
3010 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
3011#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
3012 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
3013#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
3014 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
3015#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
3016 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
3017#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
3018 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
3019#define CONFIG_SYS_MPC85xx_ECM_ADDR \
3020 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
3021#define CONFIG_SYS_FSL_DDR_ADDR \
3022 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
3023#define CONFIG_SYS_FSL_DDR2_ADDR \
3024 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
3025#define CONFIG_SYS_FSL_DDR3_ADDR \
3026 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
3027#define CONFIG_SYS_LBC_ADDR \
3028 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
3029#define CONFIG_SYS_IFC_ADDR \
3030 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
3031#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
3032 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
3033#define CONFIG_SYS_MPC85xx_PCIX_ADDR \
3034 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
3035#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
3036 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
3037#define CONFIG_SYS_MPC85xx_GPIO_ADDR \
3038 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
3039#define CONFIG_SYS_MPC85xx_SATA1_ADDR \
3040 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
3041#define CONFIG_SYS_MPC85xx_SATA2_ADDR \
3042 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
3043#define CONFIG_SYS_MPC85xx_L2_ADDR \
3044 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
3045#define CONFIG_SYS_MPC85xx_DMA_ADDR \
3046 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
3047#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
3048 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
3049#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
3050 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
3051#define CONFIG_SYS_MPC85xx_CPM_ADDR \
3052 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
3053#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
3054 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
3055#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
3056 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
3057#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
3058 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
3059#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
3060 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
3061#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
3062 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
3063#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
3064 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
3065#define CONFIG_SYS_MPC85xx_USB1_ADDR \
3066 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
3067#define CONFIG_SYS_MPC85xx_USB2_ADDR \
3068 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
3069#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
3070 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
3071#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
3072 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
3073#define CONFIG_SYS_FSL_SEC_ADDR \
3074 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
3075#define CONFIG_SYS_FSL_JR0_ADDR \
3076 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
3077#define CONFIG_SYS_FSL_FM1_ADDR \
3078 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
3079#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
3080 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
3081#define CONFIG_SYS_FSL_FM2_ADDR \
3082 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
3083#define CONFIG_SYS_FSL_SRIO_ADDR \
3084 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
3085#define CONFIG_SYS_PAMU_ADDR \
3086 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
3087
3088#define CONFIG_SYS_PCI1_ADDR \
3089 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
3090#define CONFIG_SYS_PCI2_ADDR \
3091 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
3092#define CONFIG_SYS_PCIE1_ADDR \
3093 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
3094#define CONFIG_SYS_PCIE2_ADDR \
3095 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
3096#define CONFIG_SYS_PCIE3_ADDR \
3097 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
3098#define CONFIG_SYS_PCIE4_ADDR \
3099 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
3100
3101#define CONFIG_SYS_SFP_ADDR \
3102 (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
3103
3104#define CONFIG_SYS_SEC_MON_ADDR \
3105 (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET)
3106
3107#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
3108#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
3109
3110#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
3111struct ccsr_cluster_l2 {
3112 u32 l2csr0;
3113 u32 l2csr1;
3114 u32 l2cfg0;
3115 u8 res_0c[500];
3116 u32 l2pir0;
3117 u8 res_204[4];
3118 u32 l2par0;
3119 u32 l2pwr0;
3120 u32 l2pir1;
3121 u8 res_214[4];
3122 u32 l2par1;
3123 u32 l2pwr1;
3124 u32 u2pir2;
3125 u8 res_224[4];
3126 u32 l2par2;
3127 u32 l2pwr2;
3128 u32 l2pir3;
3129 u8 res_234[4];
3130 u32 l2par3;
3131 u32 l2pwr3;
3132 u32 l2pir4;
3133 u8 res244[4];
3134 u32 l2par4;
3135 u32 l2pwr4;
3136 u32 l2pir5;
3137 u8 res_254[4];
3138 u32 l2par5;
3139 u32 l2pwr5;
3140 u32 l2pir6;
3141 u8 res_264[4];
3142 u32 l2par6;
3143 u32 l2pwr6;
3144 u32 l2pir7;
3145 u8 res274[4];
3146 u32 l2par7;
3147 u32 l2pwr7;
3148 u8 res_280[0xb80];
3149 u32 l2errinjhi;
3150 u32 l2errinjlo;
3151 u32 l2errinjctl;
3152 u8 res_e0c[20];
3153 u32 l2captdatahi;
3154 u32 l2captdatalo;
3155 u32 l2captecc;
3156 u8 res_e2c[20];
3157 u32 l2errdet;
3158 u32 l2errdis;
3159 u32 l2errinten;
3160 u32 l2errattr;
3161 u32 l2erreaddr;
3162 u32 l2erraddr;
3163 u32 l2errctl;
3164};
3165#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
3166 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
3167#endif
3168
3169#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
3170struct dcsr_dcfg_regs {
3171 u8 res_0[0x520];
3172 u32 ecccr1;
3173#define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
3174#define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
3175 u8 res_524[0x1000 - 0x524];
3176};
3177
3178#define CONFIG_SYS_MPC85xx_SCFG \
3179 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
3180#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
3181
3182struct ccsr_scfg {
3183 u32 dpslpcr;
3184 u32 usb1dpslpcsr;
3185 u32 usb2dpslpcsr;
3186 u32 fmclkdpslpcr;
3187 u32 res1[4];
3188 u32 esgmiiselcr;
3189 u32 res2;
3190 u32 pixclkcr;
3191 u32 res3[245];
3192 u32 qeioclkcr;
3193 u32 emiiocr;
3194 u32 sdhciovselcr;
3195 u32 qmifrstcr;
3196 u32 res4[60];
3197 u32 sparecr[8];
3198};
3199#endif
3200