LXR uboot/board/freescale/ls2080ardb/ddr.c

   1/*
   2 * Copyright 2015 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <fsl_ddr_sdram.h>
   9#include <fsl_ddr_dimm_params.h>
  10#include <asm/arch/soc.h>
  11#include "ddr.h"
  12
  13DECLARE_GLOBAL_DATA_PTR;
  14
  15void fsl_ddr_board_options(memctl_options_t *popts,
  16                                dimm_params_t *pdimm,
  17                                unsigned int ctrl_num)
  18{
  19#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  20        u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
  21#endif
  22        const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  23        ulong ddr_freq;
  24        int slot;
  25
  26        if (ctrl_num > 2) {
  27                printf("Not supported controller number %d\n", ctrl_num);
  28                return;
  29        }
  30
  31        for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
  32                if (pdimm[slot].n_ranks)
  33                        break;
  34        }
  35
  36        if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
  37                return;
  38
  39        /*
  40         * we use identical timing for all slots. If needed, change the code
  41         * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  42         */
  43        if (popts->registered_dimm_en)
  44                pbsp = rdimms[ctrl_num];
  45        else
  46                pbsp = udimms[ctrl_num];
  47
  48
  49        /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  50         * freqency and n_banks specified in board_specific_parameters table.
  51         */
  52        ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
  53        while (pbsp->datarate_mhz_high) {
  54                if (pbsp->n_ranks == pdimm[slot].n_ranks &&
  55                    (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
  56                        if (ddr_freq <= pbsp->datarate_mhz_high) {
  57                                popts->clk_adjust = pbsp->clk_adjust;
  58                                popts->wrlvl_start = pbsp->wrlvl_start;
  59                                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  60                                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  61                                goto found;
  62                        }
  63                        pbsp_highest = pbsp;
  64                }
  65                pbsp++;
  66        }
  67
  68        if (pbsp_highest) {
  69                printf("Error: board specific timing not found for data rate %lu MT/s\n"
  70                        "Trying to use the highest speed (%u) parameters\n",
  71                        ddr_freq, pbsp_highest->datarate_mhz_high);
  72                popts->clk_adjust = pbsp_highest->clk_adjust;
  73                popts->wrlvl_start = pbsp_highest->wrlvl_start;
  74                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  75                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  76        } else {
  77                panic("DIMM is not supported by this board");
  78        }
  79found:
  80        debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  81                "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
  82                pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  83                pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  84                pbsp->wrlvl_ctl_3);
  85#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  86        if (ctrl_num == CONFIG_DP_DDR_CTRL) {
  87                /* force DDR bus width to 32 bits */
  88                popts->data_bus_width = 1;
  89                popts->otf_burst_chop_en = 0;
  90                popts->burst_length = DDR_BL8;
  91                popts->bstopre = 0;     /* enable auto precharge */
  92                /*
  93                 * Layout optimization results byte mapping
  94                 * Byte 0 -> Byte ECC
  95                 * Byte 1 -> Byte 3
  96                 * Byte 2 -> Byte 2
  97                 * Byte 3 -> Byte 1
  98                 * Byte ECC -> Byte 0
  99                 */
 100                dq_mapping_0 = pdimm[slot].dq_mapping[0];
 101                dq_mapping_2 = pdimm[slot].dq_mapping[2];
 102                dq_mapping_3 = pdimm[slot].dq_mapping[3];
 103                pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
 104                pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
 105                pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
 106                pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
 107                pdimm[slot].dq_mapping[6] = dq_mapping_2;
 108                pdimm[slot].dq_mapping[7] = dq_mapping_3;
 109                pdimm[slot].dq_mapping[8] = dq_mapping_0;
 110                pdimm[slot].dq_mapping[9] = 0;
 111                pdimm[slot].dq_mapping[10] = 0;
 112                pdimm[slot].dq_mapping[11] = 0;
 113                pdimm[slot].dq_mapping[12] = 0;
 114                pdimm[slot].dq_mapping[13] = 0;
 115                pdimm[slot].dq_mapping[14] = 0;
 116                pdimm[slot].dq_mapping[15] = 0;
 117                pdimm[slot].dq_mapping[16] = 0;
 118                pdimm[slot].dq_mapping[17] = 0;
 119        }
 120#endif
 121        /* To work at higher than 1333MT/s */
 122        popts->half_strength_driver_enable = 0;
 123        /*
 124         * Write leveling override
 125         */
 126        popts->wrlvl_override = 1;
 127        popts->wrlvl_sample = 0x0;      /* 32 clocks */
 128
 129        /*
 130         * Rtt and Rtt_WR override
 131         */
 132        popts->rtt_override = 0;
 133
 134        /* Enable ZQ calibration */
 135        popts->zq_en = 1;
 136
 137        /* optimize cpo for erratum A-009942 */
 138        popts->cpo_sample = 0x6e;
 139
 140        if (ddr_freq < 2350) {
 141                if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
 142                        /* four chip-selects */
 143                        popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
 144                                          DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
 145                        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
 146                        popts->twot_en = 1;     /* enable 2T timing */
 147                } else {
 148                        popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
 149                                          DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
 150                        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
 151                                          DDR_CDR2_VREF_RANGE_2;
 152                }
 153        } else {
 154                popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
 155                                  DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
 156                popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
 157                                  DDR_CDR2_VREF_RANGE_2;
 158        }
 159}
 160
 161phys_size_t initdram(int board_type)
 162{
 163        phys_size_t dram_size;
 164
 165#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 166        return fsl_ddr_sdram_size();
 167#else
 168        puts("Initializing DDR....using SPD\n");
 169
 170        dram_size = fsl_ddr_sdram();
 171#endif
 172
 173        return dram_size;
 174}
 175
 176void dram_init_banksize(void)
 177{
 178#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 179        phys_size_t dp_ddr_size;
 180#endif
 181
 182        /*
 183         * gd->arch.secure_ram tracks the location of secure memory.
 184         * It was set as if the memory starts from 0.
 185         * The address needs to add the offset of its bank.
 186         */
 187        gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 188        if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
 189                gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
 190                gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
 191                gd->bd->bi_dram[1].size = gd->ram_size -
 192                                          CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
 193#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 194                gd->arch.secure_ram = gd->bd->bi_dram[1].start +
 195                                      gd->arch.secure_ram -
 196                                      CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
 197                gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 198#endif
 199        } else {
 200                gd->bd->bi_dram[0].size = gd->ram_size;
 201#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 202                gd->arch.secure_ram = gd->bd->bi_dram[0].start +
 203                                      gd->arch.secure_ram;
 204                gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 205#endif
 206        }
 207
 208#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 209        if (soc_has_dp_ddr()) {
 210                /* initialize DP-DDR here */
 211                puts("DP-DDR:  ");
 212                /*
 213                 * DDR controller use 0 as the base address for binding.
 214                 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
 215                 */
 216                dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
 217                                          CONFIG_DP_DDR_CTRL,
 218                                          CONFIG_DP_DDR_NUM_CTRLS,
 219                                          CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
 220                                          NULL, NULL, NULL);
 221                if (dp_ddr_size) {
 222                        gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
 223                        gd->bd->bi_dram[2].size = dp_ddr_size;
 224                } else {
 225                        puts("Not detected");
 226                }
 227        }
 228#endif
 229}
 230