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10#include <common.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/hardware.h>
13#include <asm/ti-common/keystone_net.h>
14
15DECLARE_GLOBAL_DATA_PTR;
16
17unsigned int external_clk[ext_clk_count] = {
18 [sys_clk] = 122880000,
19 [alt_core_clk] = 125000000,
20 [pa_clk] = 122880000,
21 [tetris_clk] = 125000000,
22 [ddr3a_clk] = 100000000,
23 [ddr3b_clk] = 100000000,
24};
25
26static struct pll_init_data core_pll_config[NUM_SPDS] = {
27 [SPD800] = CORE_PLL_799,
28 [SPD1000] = CORE_PLL_999,
29 [SPD1200] = CORE_PLL_1200,
30};
31
32s16 divn_val[16] = {
33 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
34};
35
36static struct pll_init_data tetris_pll_config[] = {
37 [SPD800] = TETRIS_PLL_800,
38 [SPD1000] = TETRIS_PLL_1000,
39 [SPD1200] = TETRIS_PLL_1200,
40 [SPD1350] = TETRIS_PLL_1350,
41 [SPD1400] = TETRIS_PLL_1400,
42};
43
44static struct pll_init_data pa_pll_config =
45 PASS_PLL_983;
46
47struct pll_init_data *get_pll_init_data(int pll)
48{
49 int speed;
50 struct pll_init_data *data;
51
52 switch (pll) {
53 case MAIN_PLL:
54 speed = get_max_dev_speed(speeds);
55 data = &core_pll_config[speed];
56 break;
57 case TETRIS_PLL:
58 speed = get_max_arm_speed(speeds);
59 data = &tetris_pll_config[speed];
60 break;
61 case PASS_PLL:
62 data = &pa_pll_config;
63 break;
64 default:
65 data = NULL;
66 }
67
68 return data;
69}
70
71#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
72struct eth_priv_t eth_priv_cfg[] = {
73 {
74 .int_name = "K2HK_EMAC",
75 .rx_flow = 22,
76 .phy_addr = 0,
77 .slave_port = 1,
78 .sgmii_link_type = SGMII_LINK_MAC_PHY,
79 .phy_if = PHY_INTERFACE_MODE_SGMII,
80 },
81 {
82 .int_name = "K2HK_EMAC1",
83 .rx_flow = 23,
84 .phy_addr = 1,
85 .slave_port = 2,
86 .sgmii_link_type = SGMII_LINK_MAC_PHY,
87 .phy_if = PHY_INTERFACE_MODE_SGMII,
88 },
89 {
90 .int_name = "K2HK_EMAC2",
91 .rx_flow = 24,
92 .phy_addr = 2,
93 .slave_port = 3,
94 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
95 .phy_if = PHY_INTERFACE_MODE_SGMII,
96 },
97 {
98 .int_name = "K2HK_EMAC3",
99 .rx_flow = 25,
100 .phy_addr = 3,
101 .slave_port = 4,
102 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
103 .phy_if = PHY_INTERFACE_MODE_SGMII,
104 },
105};
106
107int get_num_eth_ports(void)
108{
109 return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
110}
111#endif
112
113#ifdef CONFIG_BOARD_EARLY_INIT_F
114int board_early_init_f(void)
115{
116 init_plls();
117
118 return 0;
119}
120#endif
121
122#ifdef CONFIG_SPL_BUILD
123void spl_init_keystone_plls(void)
124{
125 init_plls();
126}
127#endif
128
