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25#include <config.h>
26#include <common.h>
27#include <malloc.h>
28#include <mmc.h>
29#include <part.h>
30#include <i2c.h>
31#include <twl4030.h>
32#include <twl6030.h>
33#include <palmas.h>
34#include <asm/io.h>
35#include <asm/arch/mmc_host_def.h>
36#if !defined(CONFIG_SOC_KEYSTONE)
37#include <asm/gpio.h>
38#include <asm/arch/sys_proto.h>
39#endif
40#include <dm.h>
41
42DECLARE_GLOBAL_DATA_PTR;
43
44
45#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
46 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
47#define OMAP_HSMMC_USE_GPIO
48#else
49#undef OMAP_HSMMC_USE_GPIO
50#endif
51
52
53#define SYSCTL_SRC (1 << 25)
54#define SYSCTL_SRD (1 << 26)
55
56struct omap_hsmmc_data {
57 struct hsmmc *base_addr;
58 struct mmc_config cfg;
59#ifdef OMAP_HSMMC_USE_GPIO
60#ifdef CONFIG_DM_MMC
61 struct gpio_desc cd_gpio;
62 struct gpio_desc wp_gpio;
63 bool cd_inverted;
64#else
65 int cd_gpio;
66 int wp_gpio;
67#endif
68#endif
69};
70
71
72#define MAX_RETRY_MS 1000
73
74static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
75static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
76 unsigned int siz);
77
78#if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC)
79static int omap_mmc_setup_gpio_in(int gpio, const char *label)
80{
81 int ret;
82
83#ifndef CONFIG_DM_GPIO
84 if (!gpio_is_valid(gpio))
85 return -1;
86#endif
87 ret = gpio_request(gpio, label);
88 if (ret)
89 return ret;
90
91 ret = gpio_direction_input(gpio);
92 if (ret)
93 return ret;
94
95 return gpio;
96}
97#endif
98
99static unsigned char mmc_board_init(struct mmc *mmc)
100{
101#if defined(CONFIG_OMAP34XX)
102 t2_t *t2_base = (t2_t *)T2_BASE;
103 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
104 u32 pbias_lite;
105
106 pbias_lite = readl(&t2_base->pbias_lite);
107 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
108#ifdef CONFIG_TARGET_OMAP3_CAIRO
109
110 pbias_lite &= ~PBIASLITEVMODE0;
111#endif
112 writel(pbias_lite, &t2_base->pbias_lite);
113
114 writel(pbias_lite | PBIASLITEPWRDNZ1 |
115 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
116 &t2_base->pbias_lite);
117
118 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
119 &t2_base->devconf0);
120
121 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
122 &t2_base->devconf1);
123
124
125 if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz))
126 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
127 &t2_base->ctl_prog_io1);
128
129 writel(readl(&prcm_base->fclken1_core) |
130 EN_MMC1 | EN_MMC2 | EN_MMC3,
131 &prcm_base->fclken1_core);
132
133 writel(readl(&prcm_base->iclken1_core) |
134 EN_MMC1 | EN_MMC2 | EN_MMC3,
135 &prcm_base->iclken1_core);
136#endif
137
138#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
139
140 if (mmc->block_dev.devnum == 0)
141 vmmc_pbias_config(LDO_VOLT_3V0);
142#endif
143
144 return 0;
145}
146
147void mmc_init_stream(struct hsmmc *mmc_base)
148{
149 ulong start;
150
151 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
152
153 writel(MMC_CMD0, &mmc_base->cmd);
154 start = get_timer(0);
155 while (!(readl(&mmc_base->stat) & CC_MASK)) {
156 if (get_timer(0) - start > MAX_RETRY_MS) {
157 printf("%s: timedout waiting for cc!\n", __func__);
158 return;
159 }
160 }
161 writel(CC_MASK, &mmc_base->stat)
162 ;
163 writel(MMC_CMD0, &mmc_base->cmd)
164 ;
165 start = get_timer(0);
166 while (!(readl(&mmc_base->stat) & CC_MASK)) {
167 if (get_timer(0) - start > MAX_RETRY_MS) {
168 printf("%s: timedout waiting for cc2!\n", __func__);
169 return;
170 }
171 }
172 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
173}
174
175static int omap_hsmmc_init_setup(struct mmc *mmc)
176{
177 struct hsmmc *mmc_base;
178 unsigned int reg_val;
179 unsigned int dsor;
180 ulong start;
181
182 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
183 mmc_board_init(mmc);
184
185 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
186 &mmc_base->sysconfig);
187 start = get_timer(0);
188 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
189 if (get_timer(0) - start > MAX_RETRY_MS) {
190 printf("%s: timedout waiting for cc2!\n", __func__);
191 return -ETIMEDOUT;
192 }
193 }
194 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
195 start = get_timer(0);
196 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
197 if (get_timer(0) - start > MAX_RETRY_MS) {
198 printf("%s: timedout waiting for softresetall!\n",
199 __func__);
200 return -ETIMEDOUT;
201 }
202 }
203 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
204 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
205 &mmc_base->capa);
206
207 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
208
209 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
210 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
211 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
212
213 dsor = 240;
214 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
215 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
216 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
217 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
218 start = get_timer(0);
219 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
220 if (get_timer(0) - start > MAX_RETRY_MS) {
221 printf("%s: timedout waiting for ics!\n", __func__);
222 return -ETIMEDOUT;
223 }
224 }
225 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
226
227 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
228
229 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
230 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
231 &mmc_base->ie);
232
233 mmc_init_stream(mmc_base);
234
235 return 0;
236}
237
238
239
240
241
242
243
244static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
245{
246 ulong start;
247
248 mmc_reg_out(&mmc_base->sysctl, bit, bit);
249
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263
264#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
265 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
266 if (!(readl(&mmc_base->sysctl) & bit)) {
267 start = get_timer(0);
268 while (!(readl(&mmc_base->sysctl) & bit)) {
269 if (get_timer(0) - start > MAX_RETRY_MS)
270 return;
271 }
272 }
273#endif
274 start = get_timer(0);
275 while ((readl(&mmc_base->sysctl) & bit) != 0) {
276 if (get_timer(0) - start > MAX_RETRY_MS) {
277 printf("%s: timedout waiting for sysctl %x to clear\n",
278 __func__, bit);
279 return;
280 }
281 }
282}
283
284static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
285 struct mmc_data *data)
286{
287 struct hsmmc *mmc_base;
288 unsigned int flags, mmc_stat;
289 ulong start;
290
291 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
292 start = get_timer(0);
293 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
294 if (get_timer(0) - start > MAX_RETRY_MS) {
295 printf("%s: timedout waiting on cmd inhibit to clear\n",
296 __func__);
297 return -ETIMEDOUT;
298 }
299 }
300 writel(0xFFFFFFFF, &mmc_base->stat);
301 start = get_timer(0);
302 while (readl(&mmc_base->stat)) {
303 if (get_timer(0) - start > MAX_RETRY_MS) {
304 printf("%s: timedout waiting for STAT (%x) to clear\n",
305 __func__, readl(&mmc_base->stat));
306 return -ETIMEDOUT;
307 }
308 }
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
325 udelay(50000);
326
327 if (!(cmd->resp_type & MMC_RSP_PRESENT))
328 flags = 0;
329 else if (cmd->resp_type & MMC_RSP_136)
330 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
331 else if (cmd->resp_type & MMC_RSP_BUSY)
332 flags = RSP_TYPE_LGHT48B;
333 else
334 flags = RSP_TYPE_LGHT48;
335
336
337 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
338 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
339
340 if (cmd->resp_type & MMC_RSP_CRC)
341 flags |= CCCE_CHECK;
342 if (cmd->resp_type & MMC_RSP_OPCODE)
343 flags |= CICE_CHECK;
344
345 if (data) {
346 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
347 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
348 flags |= (MSBS_MULTIBLK | BCE_ENABLE);
349 data->blocksize = 512;
350 writel(data->blocksize | (data->blocks << 16),
351 &mmc_base->blk);
352 } else
353 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
354
355 if (data->flags & MMC_DATA_READ)
356 flags |= (DP_DATA | DDIR_READ);
357 else
358 flags |= (DP_DATA | DDIR_WRITE);
359 }
360
361 writel(cmd->cmdarg, &mmc_base->arg);
362 udelay(20);
363 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
364
365 start = get_timer(0);
366 do {
367 mmc_stat = readl(&mmc_base->stat);
368 if (get_timer(0) - start > MAX_RETRY_MS) {
369 printf("%s : timeout: No status update\n", __func__);
370 return -ETIMEDOUT;
371 }
372 } while (!mmc_stat);
373
374 if ((mmc_stat & IE_CTO) != 0) {
375 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
376 return -ETIMEDOUT;
377 } else if ((mmc_stat & ERRI_MASK) != 0)
378 return -1;
379
380 if (mmc_stat & CC_MASK) {
381 writel(CC_MASK, &mmc_base->stat);
382 if (cmd->resp_type & MMC_RSP_PRESENT) {
383 if (cmd->resp_type & MMC_RSP_136) {
384
385 cmd->response[3] = readl(&mmc_base->rsp10);
386 cmd->response[2] = readl(&mmc_base->rsp32);
387 cmd->response[1] = readl(&mmc_base->rsp54);
388 cmd->response[0] = readl(&mmc_base->rsp76);
389 } else
390
391 cmd->response[0] = readl(&mmc_base->rsp10);
392 }
393 }
394
395 if (data && (data->flags & MMC_DATA_READ)) {
396 mmc_read_data(mmc_base, data->dest,
397 data->blocksize * data->blocks);
398 } else if (data && (data->flags & MMC_DATA_WRITE)) {
399 mmc_write_data(mmc_base, data->src,
400 data->blocksize * data->blocks);
401 }
402 return 0;
403}
404
405static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
406{
407 unsigned int *output_buf = (unsigned int *)buf;
408 unsigned int mmc_stat;
409 unsigned int count;
410
411
412
413
414 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
415 count /= 4;
416
417 while (size) {
418 ulong start = get_timer(0);
419 do {
420 mmc_stat = readl(&mmc_base->stat);
421 if (get_timer(0) - start > MAX_RETRY_MS) {
422 printf("%s: timedout waiting for status!\n",
423 __func__);
424 return -ETIMEDOUT;
425 }
426 } while (mmc_stat == 0);
427
428 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
429 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
430
431 if ((mmc_stat & ERRI_MASK) != 0)
432 return 1;
433
434 if (mmc_stat & BRR_MASK) {
435 unsigned int k;
436
437 writel(readl(&mmc_base->stat) | BRR_MASK,
438 &mmc_base->stat);
439 for (k = 0; k < count; k++) {
440 *output_buf = readl(&mmc_base->data);
441 output_buf++;
442 }
443 size -= (count*4);
444 }
445
446 if (mmc_stat & BWR_MASK)
447 writel(readl(&mmc_base->stat) | BWR_MASK,
448 &mmc_base->stat);
449
450 if (mmc_stat & TC_MASK) {
451 writel(readl(&mmc_base->stat) | TC_MASK,
452 &mmc_base->stat);
453 break;
454 }
455 }
456 return 0;
457}
458
459static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
460 unsigned int size)
461{
462 unsigned int *input_buf = (unsigned int *)buf;
463 unsigned int mmc_stat;
464 unsigned int count;
465
466
467
468
469 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
470 count /= 4;
471
472 while (size) {
473 ulong start = get_timer(0);
474 do {
475 mmc_stat = readl(&mmc_base->stat);
476 if (get_timer(0) - start > MAX_RETRY_MS) {
477 printf("%s: timedout waiting for status!\n",
478 __func__);
479 return -ETIMEDOUT;
480 }
481 } while (mmc_stat == 0);
482
483 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
484 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
485
486 if ((mmc_stat & ERRI_MASK) != 0)
487 return 1;
488
489 if (mmc_stat & BWR_MASK) {
490 unsigned int k;
491
492 writel(readl(&mmc_base->stat) | BWR_MASK,
493 &mmc_base->stat);
494 for (k = 0; k < count; k++) {
495 writel(*input_buf, &mmc_base->data);
496 input_buf++;
497 }
498 size -= (count*4);
499 }
500
501 if (mmc_stat & BRR_MASK)
502 writel(readl(&mmc_base->stat) | BRR_MASK,
503 &mmc_base->stat);
504
505 if (mmc_stat & TC_MASK) {
506 writel(readl(&mmc_base->stat) | TC_MASK,
507 &mmc_base->stat);
508 break;
509 }
510 }
511 return 0;
512}
513
514static void omap_hsmmc_set_ios(struct mmc *mmc)
515{
516 struct hsmmc *mmc_base;
517 unsigned int dsor = 0;
518 ulong start;
519
520 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
521
522 switch (mmc->bus_width) {
523 case 8:
524 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
525 &mmc_base->con);
526 break;
527
528 case 4:
529 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
530 &mmc_base->con);
531 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
532 &mmc_base->hctl);
533 break;
534
535 case 1:
536 default:
537 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
538 &mmc_base->con);
539 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
540 &mmc_base->hctl);
541 break;
542 }
543
544
545
546 if (mmc->clock != 0) {
547 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
548 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
549 dsor++;
550 }
551
552 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
553 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
554
555 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
556 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
557
558 start = get_timer(0);
559 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
560 if (get_timer(0) - start > MAX_RETRY_MS) {
561 printf("%s: timedout waiting for ics!\n", __func__);
562 return;
563 }
564 }
565 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
566}
567
568#ifdef OMAP_HSMMC_USE_GPIO
569#ifdef CONFIG_DM_MMC
570static int omap_hsmmc_getcd(struct mmc *mmc)
571{
572 struct omap_hsmmc_data *priv = mmc->priv;
573 int value;
574
575 value = dm_gpio_get_value(&priv->cd_gpio);
576
577 if (value < 0)
578 return 1;
579
580 if (priv->cd_inverted)
581 return !value;
582 return value;
583}
584
585static int omap_hsmmc_getwp(struct mmc *mmc)
586{
587 struct omap_hsmmc_data *priv = mmc->priv;
588 int value;
589
590 value = dm_gpio_get_value(&priv->wp_gpio);
591
592 if (value < 0)
593 return 0;
594 return value;
595}
596#else
597static int omap_hsmmc_getcd(struct mmc *mmc)
598{
599 struct omap_hsmmc_data *priv_data = mmc->priv;
600 int cd_gpio;
601
602
603 cd_gpio = priv_data->cd_gpio;
604 if (cd_gpio < 0)
605 return 1;
606
607
608 return !gpio_get_value(cd_gpio);
609}
610
611static int omap_hsmmc_getwp(struct mmc *mmc)
612{
613 struct omap_hsmmc_data *priv_data = mmc->priv;
614 int wp_gpio;
615
616
617 wp_gpio = priv_data->wp_gpio;
618 if (wp_gpio < 0)
619 return 0;
620
621
622 return gpio_get_value(wp_gpio);
623}
624#endif
625#endif
626
627static const struct mmc_ops omap_hsmmc_ops = {
628 .send_cmd = omap_hsmmc_send_cmd,
629 .set_ios = omap_hsmmc_set_ios,
630 .init = omap_hsmmc_init_setup,
631#ifdef OMAP_HSMMC_USE_GPIO
632 .getcd = omap_hsmmc_getcd,
633 .getwp = omap_hsmmc_getwp,
634#endif
635};
636
637#ifndef CONFIG_DM_MMC
638int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
639 int wp_gpio)
640{
641 struct mmc *mmc;
642 struct omap_hsmmc_data *priv_data;
643 struct mmc_config *cfg;
644 uint host_caps_val;
645
646 priv_data = malloc(sizeof(*priv_data));
647 if (priv_data == NULL)
648 return -1;
649
650 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
651
652 switch (dev_index) {
653 case 0:
654 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
655 break;
656#ifdef OMAP_HSMMC2_BASE
657 case 1:
658 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
659#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
660 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
661 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
662 defined(CONFIG_HSMMC2_8BIT)
663
664 host_caps_val |= MMC_MODE_8BIT;
665#endif
666 break;
667#endif
668#ifdef OMAP_HSMMC3_BASE
669 case 2:
670 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
671#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
672
673 host_caps_val |= MMC_MODE_8BIT;
674#endif
675 break;
676#endif
677 default:
678 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
679 return 1;
680 }
681#ifdef OMAP_HSMMC_USE_GPIO
682
683 priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
684 priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
685#endif
686
687 cfg = &priv_data->cfg;
688
689 cfg->name = "OMAP SD/MMC";
690 cfg->ops = &omap_hsmmc_ops;
691
692 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
693 cfg->host_caps = host_caps_val & ~host_caps_mask;
694
695 cfg->f_min = 400000;
696
697 if (f_max != 0)
698 cfg->f_max = f_max;
699 else {
700 if (cfg->host_caps & MMC_MODE_HS) {
701 if (cfg->host_caps & MMC_MODE_HS_52MHz)
702 cfg->f_max = 52000000;
703 else
704 cfg->f_max = 26000000;
705 } else
706 cfg->f_max = 20000000;
707 }
708
709 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
710
711#if defined(CONFIG_OMAP34XX)
712
713
714
715 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
716 cfg->b_max = 1;
717#endif
718 mmc = mmc_create(cfg, priv_data);
719 if (mmc == NULL)
720 return -1;
721
722 return 0;
723}
724#else
725static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
726{
727 struct omap_hsmmc_data *priv = dev_get_priv(dev);
728 const void *fdt = gd->fdt_blob;
729 int node = dev->of_offset;
730 struct mmc_config *cfg;
731 int val;
732
733 priv->base_addr = map_physmem(dev_get_addr(dev), sizeof(struct hsmmc *),
734 MAP_NOCACHE);
735 cfg = &priv->cfg;
736
737 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
738 val = fdtdec_get_int(fdt, node, "bus-width", -1);
739 if (val < 0) {
740 printf("error: bus-width property missing\n");
741 return -ENOENT;
742 }
743
744 switch (val) {
745 case 0x8:
746 cfg->host_caps |= MMC_MODE_8BIT;
747 case 0x4:
748 cfg->host_caps |= MMC_MODE_4BIT;
749 break;
750 default:
751 printf("error: invalid bus-width property\n");
752 return -ENOENT;
753 }
754
755 cfg->f_min = 400000;
756 cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
757 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
758 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
759
760#ifdef OMAP_HSMMC_USE_GPIO
761 priv->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
762#endif
763
764 return 0;
765}
766
767static int omap_hsmmc_probe(struct udevice *dev)
768{
769 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
770 struct omap_hsmmc_data *priv = dev_get_priv(dev);
771 struct mmc_config *cfg;
772 struct mmc *mmc;
773
774 cfg = &priv->cfg;
775 cfg->name = "OMAP SD/MMC";
776 cfg->ops = &omap_hsmmc_ops;
777
778 mmc = mmc_create(cfg, priv);
779 if (mmc == NULL)
780 return -1;
781
782#ifdef OMAP_HSMMC_USE_GPIO
783 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
784 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
785#endif
786
787 mmc->dev = dev;
788 upriv->mmc = mmc;
789
790 return 0;
791}
792
793static const struct udevice_id omap_hsmmc_ids[] = {
794 { .compatible = "ti,omap3-hsmmc" },
795 { .compatible = "ti,omap4-hsmmc" },
796 { .compatible = "ti,am33xx-hsmmc" },
797 { }
798};
799
800U_BOOT_DRIVER(omap_hsmmc) = {
801 .name = "omap_hsmmc",
802 .id = UCLASS_MMC,
803 .of_match = omap_hsmmc_ids,
804 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
805 .probe = omap_hsmmc_probe,
806 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
807};
808#endif
809