uboot/drivers/net/fm/fm.h
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   1/*
   2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#ifndef __FM_H__
   8#define __FM_H__
   9
  10#include <common.h>
  11#include <phy.h>
  12#include <fm_eth.h>
  13#include <fsl_fman.h>
  14
  15/* Port ID */
  16#define OH_PORT_ID_BASE         0x01
  17#define MAX_NUM_OH_PORT         7
  18#define RX_PORT_1G_BASE         0x08
  19#define MAX_NUM_RX_PORT_1G      CONFIG_SYS_NUM_FM1_DTSEC
  20#define RX_PORT_10G_BASE        0x10
  21#define RX_PORT_10G_BASE2       0x08
  22#define TX_PORT_1G_BASE         0x28
  23#define MAX_NUM_TX_PORT_1G      CONFIG_SYS_NUM_FM1_DTSEC
  24#define TX_PORT_10G_BASE        0x30
  25#define TX_PORT_10G_BASE2       0x28
  26#define MIIM_TIMEOUT    0xFFFF
  27
  28struct fm_muram {
  29        void *base;
  30        void *top;
  31        size_t size;
  32        void *alloc;
  33};
  34#define FM_MURAM_RES_SIZE       0x01000
  35
  36/* Rx/Tx buffer descriptor */
  37struct fm_port_bd {
  38        u16 status;
  39        u16 len;
  40        u32 res0;
  41        u16 res1;
  42        u16 buf_ptr_hi;
  43        u32 buf_ptr_lo;
  44};
  45
  46/* Common BD flags */
  47#define BD_LAST                 0x0800
  48
  49/* Rx BD status flags */
  50#define RxBD_EMPTY              0x8000
  51#define RxBD_LAST               BD_LAST
  52#define RxBD_FIRST              0x0400
  53#define RxBD_PHYS_ERR           0x0008
  54#define RxBD_SIZE_ERR           0x0004
  55#define RxBD_ERROR              (RxBD_PHYS_ERR | RxBD_SIZE_ERR)
  56
  57/* Tx BD status flags */
  58#define TxBD_READY              0x8000
  59#define TxBD_LAST               BD_LAST
  60
  61/* Rx/Tx queue descriptor */
  62struct fm_port_qd {
  63        u16 gen;
  64        u16 bd_ring_base_hi;
  65        u32 bd_ring_base_lo;
  66        u16 bd_ring_size;
  67        u16 offset_in;
  68        u16 offset_out;
  69        u16 res0;
  70        u32 res1[0x4];
  71};
  72
  73/* IM global parameter RAM */
  74struct fm_port_global_pram {
  75        u32 mode;       /* independent mode register */
  76        u32 rxqd_ptr;   /* Rx queue descriptor pointer */
  77        u32 txqd_ptr;   /* Tx queue descriptor pointer */
  78        u16 mrblr;      /* max Rx buffer length */
  79        u16 rxqd_bsy_cnt;       /* RxQD busy counter, should be cleared */
  80        u32 res0[0x4];
  81        struct fm_port_qd rxqd; /* Rx queue descriptor */
  82        struct fm_port_qd txqd; /* Tx queue descriptor */
  83        u32 res1[0x28];
  84};
  85
  86#define FM_PRAM_SIZE            sizeof(struct fm_port_global_pram)
  87#define FM_PRAM_ALIGN           256
  88#define PRAM_MODE_GLOBAL        0x20000000
  89#define PRAM_MODE_GRACEFUL_STOP 0x00800000
  90
  91#if defined(CONFIG_ARCH_P1023)
  92#define FM_FREE_POOL_SIZE       0x2000 /* 8K bytes */
  93#else
  94#define FM_FREE_POOL_SIZE       0x20000 /* 128K bytes */
  95#endif
  96#define FM_FREE_POOL_ALIGN      256
  97
  98void *fm_muram_alloc(int fm_idx, size_t size, ulong align);
  99void *fm_muram_base(int fm_idx);
 100int fm_init_common(int index, struct ccsr_fman *reg);
 101int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info);
 102phy_interface_t fman_port_enet_if(enum fm_port port);
 103void fman_disable_port(enum fm_port port);
 104void fman_enable_port(enum fm_port port);
 105
 106struct fsl_enet_mac {
 107        void *base; /* MAC controller registers base address */
 108        void *phyregs;
 109        int max_rx_len;
 110        void (*init_mac)(struct fsl_enet_mac *mac);
 111        void (*enable_mac)(struct fsl_enet_mac *mac);
 112        void (*disable_mac)(struct fsl_enet_mac *mac);
 113        void (*set_mac_addr)(struct fsl_enet_mac *mac, u8 *mac_addr);
 114        void (*set_if_mode)(struct fsl_enet_mac *mac, phy_interface_t type,
 115                                int speed);
 116};
 117
 118/* Fman ethernet private struct */
 119struct fm_eth {
 120        int fm_index;                   /* Fman index */
 121        u32 num;                        /* 0..n-1 for give type */
 122        struct fm_bmi_tx_port *tx_port;
 123        struct fm_bmi_rx_port *rx_port;
 124        enum fm_eth_type type;          /* 1G or 10G ethernet */
 125        phy_interface_t enet_if;
 126        struct fsl_enet_mac *mac;       /* MAC controller */
 127        struct mii_dev *bus;
 128        struct phy_device *phydev;
 129        int phyaddr;
 130        struct eth_device *dev;
 131        int max_rx_len;
 132        struct fm_port_global_pram *rx_pram; /* Rx parameter table */
 133        struct fm_port_global_pram *tx_pram; /* Tx parameter table */
 134        void *rx_bd_ring;               /* Rx BD ring base */
 135        void *cur_rxbd;                 /* current Rx BD */
 136        void *rx_buf;                   /* Rx buffer base */
 137        void *tx_bd_ring;               /* Tx BD ring base */
 138        void *cur_txbd;                 /* current Tx BD */
 139};
 140
 141#define RX_BD_RING_SIZE         8
 142#define TX_BD_RING_SIZE         8
 143#define MAX_RXBUF_LOG2          11
 144#define MAX_RXBUF_LEN           (1 << MAX_RXBUF_LOG2)
 145
 146#define PORT_IS_ENABLED(port)   (fm_port_to_index(port) == -1 ? \
 147        0 : fm_info[fm_port_to_index(port)].enabled)
 148
 149#endif /* __FM_H__ */
 150