1/* 2 * URB OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net> 6 * 7 * usb-ohci.h 8 */ 9 10/* 11 * e.g. PCI controllers need this 12 */ 13 14#include <asm/io.h> 15 16#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS 17# define ohci_readl(a) __swap_32(readl(a)) 18# define ohci_writel(v, a) writel(__swap_32(v), a) 19#else 20# define ohci_readl(a) readl(a) 21# define ohci_writel(v, a) writel(v, a) 22#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */ 23 24#if ARCH_DMA_MINALIGN > 16 25#define ED_ALIGNMENT ARCH_DMA_MINALIGN 26#else 27#define ED_ALIGNMENT 16 28#endif 29 30#if defined CONFIG_DM_USB && ARCH_DMA_MINALIGN > 32 31#define TD_ALIGNMENT ARCH_DMA_MINALIGN 32#else 33#define TD_ALIGNMENT 32 34#endif 35 36/* functions for doing board or CPU specific setup/cleanup */ 37int usb_board_stop(void); 38 39int usb_cpu_init(void); 40int usb_cpu_stop(void); 41int usb_cpu_init_fail(void); 42 43/* ED States */ 44#define ED_NEW 0x00 45#define ED_UNLINK 0x01 46#define ED_OPER 0x02 47#define ED_DEL 0x04 48#define ED_URB_DEL 0x08 49 50/* usb_ohci_ed */ 51struct ed { 52 __u32 hwINFO; 53 __u32 hwTailP; 54 __u32 hwHeadP; 55 __u32 hwNextED; 56 57 struct ed *ed_prev; 58 __u8 int_period; 59 __u8 int_branch; 60 __u8 int_load; 61 __u8 int_interval; 62 __u8 state; 63 __u8 type; 64 __u16 last_iso; 65 struct ed *ed_rm_list; 66 67 struct usb_device *usb_dev; 68 void *purb; 69 __u32 unused[2]; 70} __attribute__((aligned(ED_ALIGNMENT))); 71typedef struct ed ed_t; 72 73 74/* TD info field */ 75#define TD_CC 0xf0000000 76#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) 77#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) 78#define TD_EC 0x0C000000 79#define TD_T 0x03000000 80#define TD_T_DATA0 0x02000000 81#define TD_T_DATA1 0x03000000 82#define TD_T_TOGGLE 0x00000000 83#define TD_R 0x00040000 84#define TD_DI 0x00E00000 85#define TD_DI_SET(X) (((X) & 0x07)<< 21) 86#define TD_DP 0x00180000 87#define TD_DP_SETUP 0x00000000 88#define TD_DP_IN 0x00100000 89#define TD_DP_OUT 0x00080000 90 91#define TD_ISO 0x00010000 92#define TD_DEL 0x00020000 93 94/* CC Codes */ 95#define TD_CC_NOERROR 0x00 96#define TD_CC_CRC 0x01 97#define TD_CC_BITSTUFFING 0x02 98#define TD_CC_DATATOGGLEM 0x03 99#define TD_CC_STALL 0x04 100#define TD_DEVNOTRESP 0x05 101#define TD_PIDCHECKFAIL 0x06 102#define TD_UNEXPECTEDPID 0x07 103#define TD_DATAOVERRUN 0x08 104#define TD_DATAUNDERRUN 0x09 105#define TD_BUFFEROVERRUN 0x0C 106#define TD_BUFFERUNDERRUN 0x0D 107#define TD_NOTACCESSED 0x0F 108 109 110#define MAXPSW 1 111 112struct td { 113 __u32 hwINFO; 114 __u32 hwCBP; /* Current Buffer Pointer */ 115 __u32 hwNextTD; /* Next TD Pointer */ 116 __u32 hwBE; /* Memory Buffer End Pointer */ 117 118/* #ifndef CONFIG_MPC5200 /\* this seems wrong *\/ */ 119 __u16 hwPSW[MAXPSW]; 120/* #endif */ 121 __u8 unused; 122 __u8 index; 123 struct ed *ed; 124 struct td *next_dl_td; 125 struct usb_device *usb_dev; 126 int transfer_len; 127 __u32 data; 128 129 __u32 unused2[2]; 130} __attribute__((aligned(TD_ALIGNMENT))); 131typedef struct td td_t; 132 133#define OHCI_ED_SKIP (1 << 14) 134 135/* 136 * The HCCA (Host Controller Communications Area) is a 256 byte 137 * structure defined in the OHCI spec. that the host controller is 138 * told the base address of. It must be 256-byte aligned. 139 */ 140 141#define NUM_INTS 32 /* part of the OHCI standard */ 142struct ohci_hcca { 143 __u32 int_table[NUM_INTS]; /* Interrupt ED table */ 144#if defined(CONFIG_MPC5200) 145 __u16 pad1; /* set to 0 on each frame_no change */ 146 __u16 frame_no; /* current frame number */ 147#else 148 __u16 frame_no; /* current frame number */ 149 __u16 pad1; /* set to 0 on each frame_no change */ 150#endif 151 __u32 done_head; /* info returned for an interrupt */ 152 u8 reserved_for_hc[116]; 153} __attribute__((aligned(256))); 154 155 156/* 157 * Maximum number of root hub ports. 158 */ 159#ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 160# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!" 161#endif 162 163/* 164 * This is the structure of the OHCI controller's memory mapped I/O 165 * region. This is Memory Mapped I/O. You must use the ohci_readl() and 166 * ohci_writel() macros defined in this file to access these!! 167 */ 168struct ohci_regs { 169 /* control and status registers */ 170 __u32 revision; 171 __u32 control; 172 __u32 cmdstatus; 173 __u32 intrstatus; 174 __u32 intrenable; 175 __u32 intrdisable; 176 /* memory pointers */ 177 __u32 hcca; 178 __u32 ed_periodcurrent; 179 __u32 ed_controlhead; 180 __u32 ed_controlcurrent; 181 __u32 ed_bulkhead; 182 __u32 ed_bulkcurrent; 183 __u32 donehead; 184 /* frame counters */ 185 __u32 fminterval; 186 __u32 fmremaining; 187 __u32 fmnumber; 188 __u32 periodicstart; 189 __u32 lsthresh; 190 /* Root hub ports */ 191 struct ohci_roothub_regs { 192 __u32 a; 193 __u32 b; 194 __u32 status; 195 __u32 portstatus[CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS]; 196 } roothub; 197} __attribute__((aligned(32))); 198 199/* Some EHCI controls */ 200#define EHCI_USBCMD_OFF 0x20 201#define EHCI_USBCMD_HCRESET (1 << 1) 202 203/* OHCI CONTROL AND STATUS REGISTER MASKS */ 204 205/* 206 * HcControl (control) register masks 207 */ 208#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ 209#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ 210#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ 211#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ 212#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ 213#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ 214#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ 215#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ 216#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ 217 218/* pre-shifted values for HCFS */ 219# define OHCI_USB_RESET (0 << 6) 220# define OHCI_USB_RESUME (1 << 6) 221# define OHCI_USB_OPER (2 << 6) 222# define OHCI_USB_SUSPEND (3 << 6) 223 224/* 225 * HcCommandStatus (cmdstatus) register masks 226 */ 227#define OHCI_HCR (1 << 0) /* host controller reset */ 228#define OHCI_CLF (1 << 1) /* control list filled */ 229#define OHCI_BLF (1 << 2) /* bulk list filled */ 230#define OHCI_OCR (1 << 3) /* ownership change request */ 231#define OHCI_SOC (3 << 16) /* scheduling overrun count */ 232 233/* 234 * masks used with interrupt registers: 235 * HcInterruptStatus (intrstatus) 236 * HcInterruptEnable (intrenable) 237 * HcInterruptDisable (intrdisable) 238 */ 239#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ 240#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ 241#define OHCI_INTR_SF (1 << 2) /* start frame */ 242#define OHCI_INTR_RD (1 << 3) /* resume detect */ 243#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ 244#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ 245#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ 246#define OHCI_INTR_OC (1 << 30) /* ownership change */ 247#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ 248 249 250/* Virtual Root HUB */ 251struct virt_root_hub { 252 int devnum; /* Address of Root Hub endpoint */ 253 void *dev; /* was urb */ 254 void *int_addr; 255 int send; 256 int interval; 257}; 258 259/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ 260 261/* destination of request */ 262#define RH_INTERFACE 0x01 263#define RH_ENDPOINT 0x02 264#define RH_OTHER 0x03 265 266#define RH_CLASS 0x20 267#define RH_VENDOR 0x40 268 269/* Requests: bRequest << 8 | bmRequestType */ 270#define RH_GET_STATUS 0x0080 271#define RH_CLEAR_FEATURE 0x0100 272#define RH_SET_FEATURE 0x0300 273#define RH_SET_ADDRESS 0x0500 274#define RH_GET_DESCRIPTOR 0x0680 275#define RH_SET_DESCRIPTOR 0x0700 276#define RH_GET_CONFIGURATION 0x0880 277#define RH_SET_CONFIGURATION 0x0900 278#define RH_GET_STATE 0x0280 279#define RH_GET_INTERFACE 0x0A80 280#define RH_SET_INTERFACE 0x0B00 281#define RH_SYNC_FRAME 0x0C80 282/* Our Vendor Specific Request */ 283#define RH_SET_EP 0x2000 284 285 286/* Hub port features */ 287#define RH_PORT_CONNECTION 0x00 288#define RH_PORT_ENABLE 0x01 289#define RH_PORT_SUSPEND 0x02 290#define RH_PORT_OVER_CURRENT 0x03 291#define RH_PORT_RESET 0x04 292#define RH_PORT_POWER 0x08 293#define RH_PORT_LOW_SPEED 0x09 294 295#define RH_C_PORT_CONNECTION 0x10 296#define RH_C_PORT_ENABLE 0x11 297#define RH_C_PORT_SUSPEND 0x12 298#define RH_C_PORT_OVER_CURRENT 0x13 299#define RH_C_PORT_RESET 0x14 300 301/* Hub features */ 302#define RH_C_HUB_LOCAL_POWER 0x00 303#define RH_C_HUB_OVER_CURRENT 0x01 304 305#define RH_DEVICE_REMOTE_WAKEUP 0x00 306#define RH_ENDPOINT_STALL 0x01 307 308#define RH_ACK 0x01 309#define RH_REQ_ERR -1 310#define RH_NACK 0x00 311 312 313/* OHCI ROOT HUB REGISTER MASKS */ 314 315/* roothub.portstatus [i] bits */ 316#define RH_PS_CCS 0x00000001 /* current connect status */ 317#define RH_PS_PES 0x00000002 /* port enable status*/ 318#define RH_PS_PSS 0x00000004 /* port suspend status */ 319#define RH_PS_POCI 0x00000008 /* port over current indicator */ 320#define RH_PS_PRS 0x00000010 /* port reset status */ 321#define RH_PS_PPS 0x00000100 /* port power status */ 322#define RH_PS_LSDA 0x00000200 /* low speed device attached */ 323#define RH_PS_CSC 0x00010000 /* connect status change */ 324#define RH_PS_PESC 0x00020000 /* port enable status change */ 325#define RH_PS_PSSC 0x00040000 /* port suspend status change */ 326#define RH_PS_OCIC 0x00080000 /* over current indicator change */ 327#define RH_PS_PRSC 0x00100000 /* port reset status change */ 328 329/* roothub.status bits */ 330#define RH_HS_LPS 0x00000001 /* local power status */ 331#define RH_HS_OCI 0x00000002 /* over current indicator */ 332#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ 333#define RH_HS_LPSC 0x00010000 /* local power status change */ 334#define RH_HS_OCIC 0x00020000 /* over current indicator change */ 335#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ 336 337/* roothub.b masks */ 338#define RH_B_DR 0x0000ffff /* device removable flags */ 339#define RH_B_PPCM 0xffff0000 /* port power control mask */ 340 341/* roothub.a masks */ 342#define RH_A_NDP (0xff << 0) /* number of downstream ports */ 343#define RH_A_PSM (1 << 8) /* power switching mode */ 344#define RH_A_NPS (1 << 9) /* no power switching */ 345#define RH_A_DT (1 << 10) /* device type (mbz) */ 346#define RH_A_OCPM (1 << 11) /* over current protection mode */ 347#define RH_A_NOCP (1 << 12) /* no over current protection */ 348#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ 349 350/* urb */ 351#define N_URB_TD 48 352typedef struct 353{ 354 ed_t *ed; 355 __u16 length; /* number of tds associated with this request */ 356 __u16 td_cnt; /* number of tds already serviced */ 357 struct usb_device *dev; 358 int state; 359 unsigned long pipe; 360 void *transfer_buffer; 361 int transfer_buffer_length; 362 int interval; 363 int actual_length; 364 int finished; 365 td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ 366} urb_priv_t; 367#define URB_DEL 1 368 369#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ 370 371#define NUM_TD 64 /* we need more TDs than EDs */ 372 373#define NUM_INT_DEVS 8 /* num of ohci_dev structs for int endpoints */ 374 375typedef struct ohci_device { 376 ed_t ed[NUM_EDS] __aligned(ED_ALIGNMENT); 377 td_t tds[NUM_TD] __aligned(TD_ALIGNMENT); 378 int ed_cnt; 379 int devnum; 380} ohci_dev_t; 381 382/* 383 * This is the full ohci controller description 384 * 385 * Note how the "proper" USB information is just 386 * a subset of what the full implementation needs. (Linus) 387 */ 388 389 390typedef struct ohci { 391 /* this allocates EDs for all possible endpoints */ 392 struct ohci_device ohci_dev __aligned(TD_ALIGNMENT); 393 struct ohci_device int_dev[NUM_INT_DEVS] __aligned(TD_ALIGNMENT); 394 struct ohci_hcca *hcca; /* hcca */ 395 /*dma_addr_t hcca_dma;*/ 396 397 int irq; 398 int disabled; /* e.g. got a UE, we're hung */ 399 int sleeping; 400 unsigned long flags; /* for HC bugs */ 401 402 struct ohci_regs *regs; /* OHCI controller's memory */ 403 404 int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/ 405 ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ 406 ed_t *ed_bulktail; /* last endpoint of bulk list */ 407 ed_t *ed_controltail; /* last endpoint of control list */ 408 int intrstatus; 409 __u32 hc_control; /* copy of the hc control reg */ 410 struct usb_device *dev[32]; 411 struct virt_root_hub rh; 412 413 const char *slot_name; 414} ohci_t; 415 416#ifdef CONFIG_DM_USB 417extern struct dm_usb_ops ohci_usb_ops; 418 419int ohci_register(struct udevice *dev, struct ohci_regs *regs); 420int ohci_deregister(struct udevice *dev); 421#endif 422