1
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5
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10
11
12
13#define CONFIG_E300 1
14#define CONFIG_QE 1
15#define CONFIG_MPC832x 1
16#define CONFIG_MPC832XEMDS 1
17
18#define CONFIG_SYS_TEXT_BASE 0xFE000000
19
20
21
22
23#ifdef CONFIG_PCISLAVE
24#define CONFIG_83XX_PCICLK 66000000
25#else
26#define CONFIG_83XX_CLKIN 66000000
27#endif
28
29#ifndef CONFIG_SYS_CLK_FREQ
30#define CONFIG_SYS_CLK_FREQ 66000000
31#endif
32
33
34
35
36#define CONFIG_SYS_HRCW_LOW (\
37 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
38 HRCWL_DDR_TO_SCB_CLK_2X1 |\
39 HRCWL_VCO_1X2 |\
40 HRCWL_CSB_TO_CLKIN_2X1 |\
41 HRCWL_CORE_TO_CSB_2X1 |\
42 HRCWL_CE_PLL_VCO_DIV_2 |\
43 HRCWL_CE_PLL_DIV_1X1 |\
44 HRCWL_CE_TO_PLL_1X3)
45
46#ifdef CONFIG_PCISLAVE
47#define CONFIG_SYS_HRCW_HIGH (\
48 HRCWH_PCI_AGENT |\
49 HRCWH_PCI1_ARBITER_DISABLE |\
50 HRCWH_CORE_ENABLE |\
51 HRCWH_FROM_0XFFF00100 |\
52 HRCWH_BOOTSEQ_DISABLE |\
53 HRCWH_SW_WATCHDOG_DISABLE |\
54 HRCWH_ROM_LOC_LOCAL_16BIT |\
55 HRCWH_BIG_ENDIAN |\
56 HRCWH_LALE_NORMAL)
57#else
58#define CONFIG_SYS_HRCW_HIGH (\
59 HRCWH_PCI_HOST |\
60 HRCWH_PCI1_ARBITER_ENABLE |\
61 HRCWH_CORE_ENABLE |\
62 HRCWH_FROM_0X00000100 |\
63 HRCWH_BOOTSEQ_DISABLE |\
64 HRCWH_SW_WATCHDOG_DISABLE |\
65 HRCWH_ROM_LOC_LOCAL_16BIT |\
66 HRCWH_BIG_ENDIAN |\
67 HRCWH_LALE_NORMAL)
68#endif
69
70
71
72
73#define CONFIG_SYS_SICRL 0x00000000
74
75#define CONFIG_BOARD_EARLY_INIT_F
76#define CONFIG_BOARD_EARLY_INIT_R
77
78
79
80
81#define CONFIG_SYS_IMMR 0xE0000000
82
83
84
85
86#define CONFIG_SYS_DDR_BASE 0x00000000
87#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
88#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
89#define CONFIG_SYS_DDRCDR 0x73000002
90
91#undef CONFIG_SPD_EEPROM
92#if defined(CONFIG_SPD_EEPROM)
93
94
95#define SPD_EEPROM_ADDRESS 0x51
96#else
97
98
99#define CONFIG_SYS_DDR_SIZE 128
100#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
101 | CSCONFIG_AP \
102 | CSCONFIG_ODT_WR_CFG \
103 | CSCONFIG_ROW_BIT_13 \
104 | CSCONFIG_COL_BIT_10)
105
106#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
107 | (0 << TIMING_CFG0_WRT_SHIFT) \
108 | (0 << TIMING_CFG0_RRT_SHIFT) \
109 | (0 << TIMING_CFG0_WWT_SHIFT) \
110 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
111 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
112 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
113 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
114
115#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
116 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
117 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
118 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
119 | (13 << TIMING_CFG1_REFREC_SHIFT) \
120 | (3 << TIMING_CFG1_WRREC_SHIFT) \
121 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
122 | (2 << TIMING_CFG1_WRTORD_SHIFT))
123
124#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
125 | (31 << TIMING_CFG2_CPO_SHIFT) \
126 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
127 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
128 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
129 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
130 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
131
132#define CONFIG_SYS_DDR_TIMING_3 0x00000000
133#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
134
135#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
136 | (0x0232 << SDRAM_MODE_SD_SHIFT))
137
138#define CONFIG_SYS_DDR_MODE2 0x8000c000
139#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
140 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
141
142#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
143#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
144 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
145 | SDRAM_CFG_32_BE)
146
147#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
148#endif
149
150
151
152
153#undef CONFIG_SYS_DRAM_TEST
154#define CONFIG_SYS_MEMTEST_START 0x00000000
155#define CONFIG_SYS_MEMTEST_END 0x00100000
156
157
158
159
160#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
161
162#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
163#define CONFIG_SYS_RAMBOOT
164#else
165#undef CONFIG_SYS_RAMBOOT
166#endif
167
168
169#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
170#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
171
172
173
174
175#define CONFIG_SYS_INIT_RAM_LOCK 1
176#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
177#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
178#define CONFIG_SYS_GBL_DATA_OFFSET \
179 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
180
181
182
183
184#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
185#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
186#define CONFIG_SYS_LBC_LBCR 0x00000000
187
188
189
190
191#define CONFIG_SYS_FLASH_CFI
192#define CONFIG_FLASH_CFI_DRIVER
193#define CONFIG_SYS_FLASH_BASE 0xFE000000
194#define CONFIG_SYS_FLASH_SIZE 16
195#define CONFIG_SYS_FLASH_PROTECTION 1
196
197
198#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
199#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
200
201#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
202 | BR_PS_16 \
203 | BR_MS_GPCM \
204 | BR_V)
205#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
206 | OR_GPCM_XAM \
207 | OR_GPCM_CSNT \
208 | OR_GPCM_ACS_DIV2 \
209 | OR_GPCM_XACS \
210 | OR_GPCM_SCY_15 \
211 | OR_GPCM_TRLX_SET \
212 | OR_GPCM_EHTR_SET \
213 | OR_GPCM_EAD)
214
215
216#define CONFIG_SYS_MAX_FLASH_BANKS 1
217#define CONFIG_SYS_MAX_FLASH_SECT 128
218
219#undef CONFIG_SYS_FLASH_CHECKSUM
220
221
222
223
224#define CONFIG_SYS_BCSR 0xF8000000
225
226#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
227#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
228
229#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
230 | BR_PS_8 \
231 | BR_MS_GPCM \
232 | BR_V)
233#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
234 | OR_GPCM_XAM \
235 | OR_GPCM_CSNT \
236 | OR_GPCM_XACS \
237 | OR_GPCM_SCY_15 \
238 | OR_GPCM_TRLX_SET \
239 | OR_GPCM_EHTR_SET \
240 | OR_GPCM_EAD)
241
242
243
244
245
246
247#define CONFIG_SYS_PIB_BASE 0xF8008000
248#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
249#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE
250#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
251
252
253
254
255#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
256 | BR_PS_8 \
257 | BR_MS_GPCM \
258 | BR_V)
259
260#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
261 | OR_GPCM_XAM \
262 | OR_GPCM_CSNT \
263 | OR_GPCM_XACS \
264 | OR_GPCM_SCY_15 \
265 | OR_GPCM_TRLX_SET \
266 | OR_GPCM_EHTR_SET \
267 | OR_GPCM_EAD)
268
269
270
271
272
273#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
274 CONFIG_SYS_PIB_WINDOW_SIZE) \
275 | BR_PS_8 \
276 | BR_MS_GPCM \
277 | BR_V)
278
279#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
280 | OR_GPCM_XAM \
281 | OR_GPCM_CSNT \
282 | OR_GPCM_XACS \
283 | OR_GPCM_SCY_15 \
284 | OR_GPCM_TRLX_SET \
285 | OR_GPCM_EHTR_SET \
286 | OR_GPCM_EAD)
287
288
289
290
291
292#define CONFIG_CONS_INDEX 1
293#define CONFIG_SYS_NS16550_SERIAL
294#define CONFIG_SYS_NS16550_REG_SIZE 1
295#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
296
297#define CONFIG_SYS_BAUDRATE_TABLE \
298 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
299
300#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
301#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
302
303#define CONFIG_CMDLINE_EDITING 1
304#define CONFIG_AUTO_COMPLETE
305
306
307#define CONFIG_SYS_I2C
308#define CONFIG_SYS_I2C_FSL
309#define CONFIG_SYS_FSL_I2C_SPEED 400000
310#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
311#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
312#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
313
314
315
316
317#define CONFIG_RTC_DS1374
318#define CONFIG_SYS_I2C_RTC_ADDR 0x68
319
320
321
322
323
324#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
325#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
326#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
327#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
328#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
329#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
330#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
331#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
332#define CONFIG_SYS_PCI1_IO_SIZE 0x100000
333
334#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
335#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
336#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
337
338#ifdef CONFIG_PCI
339#define CONFIG_PCI_INDIRECT_BRIDGE
340
341#define CONFIG_83XX_PCI_STREAMING
342
343#undef CONFIG_EEPRO100
344#undef CONFIG_PCI_SCAN_SHOW
345#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
346
347#endif
348
349
350
351
352#define CONFIG_UEC_ETH
353#define CONFIG_ETHPRIME "UEC0"
354
355#define CONFIG_UEC_ETH1
356
357#ifdef CONFIG_UEC_ETH1
358#define CONFIG_SYS_UEC1_UCC_NUM 2
359#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
360#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
361#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
362#define CONFIG_SYS_UEC1_PHY_ADDR 3
363#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
364#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
365#endif
366
367#define CONFIG_UEC_ETH2
368
369#ifdef CONFIG_UEC_ETH2
370#define CONFIG_SYS_UEC2_UCC_NUM 3
371#define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
372#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
373#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
374#define CONFIG_SYS_UEC2_PHY_ADDR 4
375#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
376#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
377#endif
378
379
380
381
382#ifndef CONFIG_SYS_RAMBOOT
383 #define CONFIG_ENV_IS_IN_FLASH 1
384 #define CONFIG_ENV_ADDR \
385 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
386 #define CONFIG_ENV_SECT_SIZE 0x20000
387 #define CONFIG_ENV_SIZE 0x2000
388#else
389 #define CONFIG_SYS_NO_FLASH 1
390 #define CONFIG_ENV_IS_NOWHERE 1
391 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
392 #define CONFIG_ENV_SIZE 0x2000
393#endif
394
395#define CONFIG_LOADS_ECHO 1
396#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
397
398
399
400
401#define CONFIG_BOOTP_BOOTFILESIZE
402#define CONFIG_BOOTP_BOOTPATH
403#define CONFIG_BOOTP_GATEWAY
404#define CONFIG_BOOTP_HOSTNAME
405
406
407
408
409
410#if defined(CONFIG_PCI)
411 #define CONFIG_CMD_PCI
412#endif
413
414#undef CONFIG_WATCHDOG
415
416
417
418
419#define CONFIG_SYS_LONGHELP
420#define CONFIG_SYS_LOAD_ADDR 0x2000000
421
422#if defined(CONFIG_CMD_KGDB)
423 #define CONFIG_SYS_CBSIZE 1024
424#else
425 #define CONFIG_SYS_CBSIZE 256
426#endif
427
428
429#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
430#define CONFIG_SYS_MAXARGS 16
431
432#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
433
434
435
436
437
438
439
440#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
441#define CONFIG_SYS_BOOTM_LEN (64 << 20)
442
443
444
445
446#define CONFIG_SYS_HID0_INIT 0x000000000
447#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
448 HID0_ENABLE_INSTRUCTION_CACHE)
449#define CONFIG_SYS_HID2 HID2_HBE
450
451
452
453
454
455#define CONFIG_HIGH_BATS 1
456
457
458#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
459 | BATL_PP_RW \
460 | BATL_MEMCOHERENCE)
461#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
462 | BATU_BL_256M \
463 | BATU_VS \
464 | BATU_VP)
465#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
466#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
467
468
469#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
470 | BATL_PP_RW \
471 | BATL_CACHEINHIBIT \
472 | BATL_GUARDEDSTORAGE)
473#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
474 | BATU_BL_4M \
475 | BATU_VS \
476 | BATU_VP)
477#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
478#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
479
480
481#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
482 | BATL_PP_RW \
483 | BATL_CACHEINHIBIT \
484 | BATL_GUARDEDSTORAGE)
485#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
486 | BATU_BL_128K \
487 | BATU_VS \
488 | BATU_VP)
489#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
490#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
491
492
493#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
494 | BATL_PP_RW \
495 | BATL_MEMCOHERENCE)
496#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
497 | BATU_BL_32M \
498 | BATU_VS \
499 | BATU_VP)
500#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
501 | BATL_PP_RW \
502 | BATL_CACHEINHIBIT \
503 | BATL_GUARDEDSTORAGE)
504#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
505
506#define CONFIG_SYS_IBAT4L (0)
507#define CONFIG_SYS_IBAT4U (0)
508#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
509#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
510
511
512#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
513#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
514 | BATU_BL_128K \
515 | BATU_VS \
516 | BATU_VP)
517#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
518#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
519
520#ifdef CONFIG_PCI
521
522#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
523 | BATL_PP_RW \
524 | BATL_MEMCOHERENCE)
525#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
526 | BATU_BL_256M \
527 | BATU_VS \
528 | BATU_VP)
529#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
530#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
531
532#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
533 | BATL_PP_RW \
534 | BATL_CACHEINHIBIT \
535 | BATL_GUARDEDSTORAGE)
536#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
537 | BATU_BL_256M \
538 | BATU_VS \
539 | BATU_VP)
540#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
541#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
542#else
543#define CONFIG_SYS_IBAT6L (0)
544#define CONFIG_SYS_IBAT6U (0)
545#define CONFIG_SYS_IBAT7L (0)
546#define CONFIG_SYS_IBAT7U (0)
547#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
548#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
549#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
550#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
551#endif
552
553#if defined(CONFIG_CMD_KGDB)
554#define CONFIG_KGDB_BAUDRATE 230400
555#endif
556
557
558
559 #define CONFIG_ENV_OVERWRITE
560
561#if defined(CONFIG_UEC_ETH)
562#define CONFIG_HAS_ETH0
563#define CONFIG_HAS_ETH1
564#endif
565
566#define CONFIG_BAUDRATE 115200
567
568#define CONFIG_LOADADDR 800000
569
570#undef CONFIG_BOOTARGS
571
572#define CONFIG_EXTRA_ENV_SETTINGS \
573 "netdev=eth0\0" \
574 "consoledev=ttyS0\0" \
575 "ramdiskaddr=1000000\0" \
576 "ramdiskfile=ramfs.83xx\0" \
577 "fdtaddr=780000\0" \
578 "fdtfile=mpc832x_mds.dtb\0" \
579 ""
580
581#define CONFIG_NFSBOOTCOMMAND \
582 "setenv bootargs root=/dev/nfs rw " \
583 "nfsroot=$serverip:$rootpath " \
584 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
585 "$netdev:off " \
586 "console=$consoledev,$baudrate $othbootargs;" \
587 "tftp $loadaddr $bootfile;" \
588 "tftp $fdtaddr $fdtfile;" \
589 "bootm $loadaddr - $fdtaddr"
590
591#define CONFIG_RAMBOOTCOMMAND \
592 "setenv bootargs root=/dev/ram rw " \
593 "console=$consoledev,$baudrate $othbootargs;" \
594 "tftp $ramdiskaddr $ramdiskfile;" \
595 "tftp $loadaddr $bootfile;" \
596 "tftp $fdtaddr $fdtfile;" \
597 "bootm $loadaddr $ramdiskaddr $fdtaddr"
598
599#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
600
601#endif
602