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11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#include "../board/freescale/common/ics307_clk.h"
15
16#ifndef CONFIG_SYS_TEXT_BASE
17#define CONFIG_SYS_TEXT_BASE 0xeff40000
18#endif
19
20#ifndef CONFIG_RESET_VECTOR_ADDRESS
21#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
22#endif
23
24#ifndef CONFIG_SYS_MONITOR_BASE
25#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
26#endif
27
28
29#define CONFIG_MP 1
30
31#define CONFIG_FSL_ELBC 1
32#define CONFIG_PCIE1 1
33#define CONFIG_PCIE2 1
34#define CONFIG_PCIE3 1
35#define CONFIG_FSL_PCI_INIT 1
36#define CONFIG_PCI_INDIRECT_BRIDGE 1
37#define CONFIG_FSL_PCIE_RESET 1
38#define CONFIG_SYS_PCI_64BIT 1
39
40#define CONFIG_TSEC_ENET
41#define CONFIG_ENV_OVERWRITE
42
43#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
44#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
45#define CONFIG_ICS307_REFCLK_HZ 33333000
46
47
48
49
50#define CONFIG_L2_CACHE
51#define CONFIG_BTB
52
53#define CONFIG_ENABLE_36BIT_PHYS 1
54
55#ifdef CONFIG_PHYS_64BIT
56#define CONFIG_ADDR_MAP 1
57#define CONFIG_SYS_NUM_ADDR_MAP 16
58#endif
59
60#define CONFIG_SYS_MEMTEST_START 0x00000000
61#define CONFIG_SYS_MEMTEST_END 0x7fffffff
62#define CONFIG_PANIC_HANG
63
64
65
66
67#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
68#ifdef CONFIG_PHYS_64BIT
69#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
70#else
71#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
72#endif
73#define CONFIG_SYS_L2_SIZE (512 << 10)
74#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
75
76#define CONFIG_SYS_CCSRBAR 0xffe00000
77#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
78
79#if defined(CONFIG_NAND_SPL)
80#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
81#endif
82
83
84#define CONFIG_VERY_BIG_RAM
85#undef CONFIG_FSL_DDR_INTERACTIVE
86#define CONFIG_SPD_EEPROM
87#define CONFIG_DDR_SPD
88
89#define CONFIG_DDR_ECC
90#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
91#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
92
93#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
94#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
95
96#define CONFIG_DIMM_SLOTS_PER_CTLR 1
97#define CONFIG_CHIP_SELECTS_PER_CTRL 2
98
99
100#define CONFIG_SYS_SPD_BUS_NUM 1
101#define SPD_EEPROM_ADDRESS1 0x51
102#define SPD_EEPROM_ADDRESS2 0x52
103
104
105#define CONFIG_SYS_SDRAM_SIZE 512
106#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
107#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202
108#define CONFIG_SYS_DDR_TIMING_3 0x00020000
109#define CONFIG_SYS_DDR_TIMING_0 0x00260802
110#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
111#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
112#define CONFIG_SYS_DDR_MODE_1 0x00440462
113#define CONFIG_SYS_DDR_MODE_2 0x00000000
114#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
115#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
116#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
117#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
118#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
119#define CONFIG_SYS_DDR_CONTROL 0xc3000008
120#define CONFIG_SYS_DDR_CONTROL2 0x24400000
121
122#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
123#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
124#define CONFIG_SYS_DDR_SBE 0x00010000
125
126
127
128
129#ifndef CONFIG_SPD_EEPROM
130#error ("CONFIG_SPD_EEPROM is required")
131#endif
132
133#undef CONFIG_CLOCKS_IN_MHZ
134
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155
156
157
158#define CONFIG_SYS_FLASH_BASE 0xe0000000
159#ifdef CONFIG_PHYS_64BIT
160#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
161#else
162#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
163#endif
164
165#define CONFIG_FLASH_BR_PRELIM \
166 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
167#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
168
169#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
170#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
171
172#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
173#define CONFIG_SYS_FLASH_QUIET_TEST
174#define CONFIG_FLASH_SHOW_PROGRESS 45
175
176#define CONFIG_SYS_MAX_FLASH_BANKS 2
177#define CONFIG_SYS_MAX_FLASH_SECT 1024
178#undef CONFIG_SYS_FLASH_CHECKSUM
179#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
180#define CONFIG_SYS_FLASH_WRITE_TOUT 500
181
182#undef CONFIG_SYS_RAMBOOT
183
184#define CONFIG_FLASH_CFI_DRIVER
185#define CONFIG_SYS_FLASH_CFI
186#define CONFIG_SYS_FLASH_EMPTY_INFO
187#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
188
189#define CONFIG_BOARD_EARLY_INIT_R
190
191#define CONFIG_HWCONFIG
192#define CONFIG_FSL_PIXIS 1
193#define PIXIS_BASE 0xffdf0000
194#ifdef CONFIG_PHYS_64BIT
195#define PIXIS_BASE_PHYS 0xfffdf0000ull
196#else
197#define PIXIS_BASE_PHYS PIXIS_BASE
198#endif
199
200#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
201#define CONFIG_SYS_OR3_PRELIM 0xffffeff7
202
203#define PIXIS_ID 0x0
204#define PIXIS_VER 0x1
205#define PIXIS_PVER 0x2
206#define PIXIS_CSR 0x3
207#define PIXIS_RST 0x4
208#define PIXIS_PWR 0x5
209#define PIXIS_AUX 0x6
210#define PIXIS_SPD 0x7
211#define PIXIS_AUX2 0x8
212#define PIXIS_VCTL 0x10
213#define PIXIS_VSTAT 0x11
214#define PIXIS_VCFGEN0 0x12
215#define PIXIS_VCFGEN1 0x13
216#define PIXIS_VCORE0 0x14
217#define PIXIS_VBOOT 0x16
218#define PIXIS_VBOOT_LBMAP 0xc0
219#define PIXIS_VBOOT_LBMAP_NOR0 0x00
220#define PIXIS_VBOOT_LBMAP_PJET 0x01
221#define PIXIS_VBOOT_LBMAP_NAND 0x02
222#define PIXIS_VBOOT_LBMAP_NOR1 0x03
223#define PIXIS_VSPEED0 0x17
224#define PIXIS_VSPEED1 0x18
225#define PIXIS_VSPEED2 0x19
226#define PIXIS_VSYSCLK0 0x1C
227#define PIXIS_VSYSCLK1 0x1D
228#define PIXIS_VSYSCLK2 0x1E
229#define PIXIS_VDDRCLK0 0x1F
230#define PIXIS_VDDRCLK1 0x20
231#define PIXIS_VDDRCLK2 0x21
232#define PIXIS_VWATCH 0x24
233#define PIXIS_LED 0x25
234
235#define PIXIS_SPD_SYSCLK_MASK 0x7
236
237
238#define PIXIS_VCLKH 0x19
239#define PIXIS_VCLKL 0x1A
240#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
241#define PIXIS_VSPEED2_TSEC1SER 0x8
242#define PIXIS_VSPEED2_TSEC2SER 0x4
243#define PIXIS_VSPEED2_TSEC3SER 0x2
244#define PIXIS_VSPEED2_TSEC4SER 0x1
245#define PIXIS_VCFGEN1_TSEC1SER 0x20
246#define PIXIS_VCFGEN1_TSEC2SER 0x20
247#define PIXIS_VCFGEN1_TSEC3SER 0x20
248#define PIXIS_VCFGEN1_TSEC4SER 0x20
249#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
250 | PIXIS_VSPEED2_TSEC2SER \
251 | PIXIS_VSPEED2_TSEC3SER \
252 | PIXIS_VSPEED2_TSEC4SER)
253#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
254 | PIXIS_VCFGEN1_TSEC2SER \
255 | PIXIS_VCFGEN1_TSEC3SER \
256 | PIXIS_VCFGEN1_TSEC4SER)
257
258#define CONFIG_SYS_INIT_RAM_LOCK 1
259#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
260#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
261
262#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
263#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
264
265#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
266#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
267
268#ifndef CONFIG_NAND_SPL
269#define CONFIG_SYS_NAND_BASE 0xffa00000
270#ifdef CONFIG_PHYS_64BIT
271#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
272#else
273#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
274#endif
275#else
276#define CONFIG_SYS_NAND_BASE 0xfff00000
277#ifdef CONFIG_PHYS_64BIT
278#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
279#else
280#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
281#endif
282#endif
283
284#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
285 CONFIG_SYS_NAND_BASE + 0x40000, \
286 CONFIG_SYS_NAND_BASE + 0x80000,\
287 CONFIG_SYS_NAND_BASE + 0xC0000}
288#define CONFIG_SYS_MAX_NAND_DEVICE 4
289#define CONFIG_CMD_NAND 1
290#define CONFIG_NAND_FSL_ELBC 1
291#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
292#define CONFIG_SYS_NAND_MAX_OOBFREE 5
293#define CONFIG_SYS_NAND_MAX_ECCPOS 56
294
295
296#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
297#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
298#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
299#define CONFIG_SYS_NAND_U_BOOT_START \
300 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
301#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
302#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
303#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
304
305
306#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
307 | (2<<BR_DECC_SHIFT) \
308 | BR_PS_8 \
309 | BR_MS_FCM \
310 | BR_V)
311#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 \
312 | OR_FCM_PGS \
313 | OR_FCM_CSCT \
314 | OR_FCM_CST \
315 | OR_FCM_CHT \
316 | OR_FCM_SCY_1 \
317 | OR_FCM_TRLX \
318 | OR_FCM_EHTR)
319
320#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
321#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
322#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM
323#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM
324#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
325 | (2<<BR_DECC_SHIFT) \
326 | BR_PS_8 \
327 | BR_MS_FCM \
328 | BR_V)
329#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM
330#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
331 | (2<<BR_DECC_SHIFT) \
332 | BR_PS_8 \
333 | BR_MS_FCM \
334 | BR_V)
335#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM
336
337#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
338 | (2<<BR_DECC_SHIFT) \
339 | BR_PS_8 \
340 | BR_MS_FCM \
341 | BR_V)
342#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM
343
344
345
346
347
348#define CONFIG_CONS_INDEX 1
349#define CONFIG_SYS_NS16550_SERIAL
350#define CONFIG_SYS_NS16550_REG_SIZE 1
351#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
352#ifdef CONFIG_NAND_SPL
353#define CONFIG_NS16550_MIN_FUNCTIONS
354#endif
355
356#define CONFIG_SYS_BAUDRATE_TABLE \
357 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
358
359#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
360#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
361
362
363#define CONFIG_SYS_I2C
364#define CONFIG_SYS_I2C_FSL
365#define CONFIG_SYS_FSL_I2C_SPEED 400000
366#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
367#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
368#define CONFIG_SYS_FSL_I2C2_SPEED 400000
369#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
370#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
371#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
372#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
373
374
375
376
377#define CONFIG_ID_EEPROM
378#ifdef CONFIG_ID_EEPROM
379#define CONFIG_SYS_I2C_EEPROM_NXID
380#endif
381#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
382#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
383#define CONFIG_SYS_EEPROM_BUS_NUM 1
384
385
386
387
388
389
390
391#define CONFIG_SYS_PCIE3_NAME "ULI"
392#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
393#ifdef CONFIG_PHYS_64BIT
394#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
395#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
396#else
397#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
398#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
399#endif
400#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
401#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
402#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
403#ifdef CONFIG_PHYS_64BIT
404#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
405#else
406#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
407#endif
408#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
409
410
411#define CONFIG_SYS_PCIE2_NAME "Slot 1"
412#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
413#ifdef CONFIG_PHYS_64BIT
414#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
415#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
416#else
417#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
418#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
419#endif
420#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
421#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
422#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
423#ifdef CONFIG_PHYS_64BIT
424#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
425#else
426#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
427#endif
428#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
429
430
431#define CONFIG_SYS_PCIE1_NAME "Slot 2"
432#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
433#ifdef CONFIG_PHYS_64BIT
434#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
435#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
436#else
437#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
438#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
439#endif
440#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
441#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
442#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
443#ifdef CONFIG_PHYS_64BIT
444#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
445#else
446#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
447#endif
448#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
449
450#if defined(CONFIG_PCI)
451
452
453#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
454
455
456
457#if defined(CONFIG_VIDEO)
458#define CONFIG_BIOSEMU
459#define CONFIG_ATI_RADEON_FB
460#define CONFIG_VIDEO_LOGO
461#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
462#endif
463
464#undef CONFIG_EEPRO100
465#undef CONFIG_TULIP
466
467#ifndef CONFIG_PCI_PNP
468 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
469 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
470 #define PCI_IDSEL_NUMBER 0x11
471#endif
472
473#define CONFIG_PCI_SCAN_SHOW
474#define CONFIG_DOS_PARTITION
475#define CONFIG_SCSI_AHCI
476
477#ifdef CONFIG_SCSI_AHCI
478#define CONFIG_LIBATA
479#define CONFIG_SATA_ULI5288
480#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
481#define CONFIG_SYS_SCSI_MAX_LUN 1
482#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
483#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
484#endif
485
486#endif
487
488#if defined(CONFIG_TSEC_ENET)
489
490#define CONFIG_MII 1
491#define CONFIG_MII_DEFAULT_TSEC 1
492#define CONFIG_TSEC1 1
493#define CONFIG_TSEC1_NAME "eTSEC1"
494#define CONFIG_TSEC2 1
495#define CONFIG_TSEC2_NAME "eTSEC2"
496#define CONFIG_TSEC3 1
497#define CONFIG_TSEC3_NAME "eTSEC3"
498#define CONFIG_TSEC4 1
499#define CONFIG_TSEC4_NAME "eTSEC4"
500
501#define CONFIG_PIXIS_SGMII_CMD
502#define CONFIG_FSL_SGMII_RISER 1
503#define SGMII_RISER_PHY_OFFSET 0x1c
504
505#ifdef CONFIG_FSL_SGMII_RISER
506#define CONFIG_SYS_TBIPA_VALUE 0x10
507#endif
508
509#define TSEC1_PHY_ADDR 0
510#define TSEC2_PHY_ADDR 1
511#define TSEC3_PHY_ADDR 2
512#define TSEC4_PHY_ADDR 3
513
514#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
515#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
516#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
517#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
518
519#define TSEC1_PHYIDX 0
520#define TSEC2_PHYIDX 0
521#define TSEC3_PHYIDX 0
522#define TSEC4_PHYIDX 0
523
524#define CONFIG_ETHPRIME "eTSEC1"
525
526#define CONFIG_PHY_GIGE 1
527#endif
528
529
530
531
532
533#if defined(CONFIG_SYS_RAMBOOT)
534
535#else
536 #define CONFIG_ENV_IS_IN_FLASH 1
537 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
538 #define CONFIG_ENV_ADDR 0xfff80000
539 #else
540 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
541 #endif
542 #define CONFIG_ENV_SIZE 0x2000
543 #define CONFIG_ENV_SECT_SIZE 0x20000
544#endif
545
546#define CONFIG_LOADS_ECHO 1
547#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
548
549
550
551
552#define CONFIG_CMD_ERRATA
553#define CONFIG_CMD_IRQ
554#define CONFIG_CMD_REGINFO
555
556#if defined(CONFIG_PCI)
557#define CONFIG_CMD_PCI
558#define CONFIG_SCSI
559#endif
560
561
562
563
564#define CONFIG_USB_EHCI
565
566#ifdef CONFIG_USB_EHCI
567#define CONFIG_USB_EHCI_PCI
568#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
569#define CONFIG_PCI_EHCI_DEVICE 0
570#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
571#endif
572
573#undef CONFIG_WATCHDOG
574
575
576
577
578#define CONFIG_SYS_LONGHELP
579#define CONFIG_CMDLINE_EDITING
580#define CONFIG_AUTO_COMPLETE
581#define CONFIG_SYS_LOAD_ADDR 0x2000000
582#if defined(CONFIG_CMD_KGDB)
583#define CONFIG_SYS_CBSIZE 1024
584#else
585#define CONFIG_SYS_CBSIZE 256
586#endif
587#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
588#define CONFIG_SYS_MAXARGS 16
589#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
590
591
592
593
594
595
596#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
597#define CONFIG_SYS_BOOTM_LEN (64 << 20)
598
599#if defined(CONFIG_CMD_KGDB)
600#define CONFIG_KGDB_BAUDRATE 230400
601#endif
602
603
604
605
606#if defined(CONFIG_TSEC_ENET)
607#define CONFIG_HAS_ETH0
608#define CONFIG_HAS_ETH1
609#define CONFIG_HAS_ETH2
610#define CONFIG_HAS_ETH3
611#endif
612
613#define CONFIG_IPADDR 192.168.1.254
614
615#define CONFIG_HOSTNAME unknown
616#define CONFIG_ROOTPATH "/opt/nfsroot"
617#define CONFIG_BOOTFILE "uImage"
618#define CONFIG_UBOOTPATH u-boot.bin
619
620#define CONFIG_SERVERIP 192.168.1.1
621#define CONFIG_GATEWAYIP 192.168.1.1
622#define CONFIG_NETMASK 255.255.255.0
623
624
625#define CONFIG_LOADADDR 1000000
626
627#undef CONFIG_BOOTARGS
628
629#define CONFIG_BAUDRATE 115200
630
631#define CONFIG_EXTRA_ENV_SETTINGS \
632"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
633"netdev=eth0\0" \
634"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
635"tftpflash=tftpboot $loadaddr $uboot; " \
636 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
637 " +$filesize; " \
638 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
639 " +$filesize; " \
640 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
641 " $filesize; " \
642 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
643 " +$filesize; " \
644 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
645 " $filesize\0" \
646"consoledev=ttyS0\0" \
647"ramdiskaddr=2000000\0" \
648"ramdiskfile=8572ds/ramdisk.uboot\0" \
649"fdtaddr=1e00000\0" \
650"fdtfile=8572ds/mpc8572ds.dtb\0" \
651"bdev=sda3\0"
652
653#define CONFIG_HDBOOT \
654 "setenv bootargs root=/dev/$bdev rw " \
655 "console=$consoledev,$baudrate $othbootargs;" \
656 "tftp $loadaddr $bootfile;" \
657 "tftp $fdtaddr $fdtfile;" \
658 "bootm $loadaddr - $fdtaddr"
659
660#define CONFIG_NFSBOOTCOMMAND \
661 "setenv bootargs root=/dev/nfs rw " \
662 "nfsroot=$serverip:$rootpath " \
663 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
664 "console=$consoledev,$baudrate $othbootargs;" \
665 "tftp $loadaddr $bootfile;" \
666 "tftp $fdtaddr $fdtfile;" \
667 "bootm $loadaddr - $fdtaddr"
668
669#define CONFIG_RAMBOOTCOMMAND \
670 "setenv bootargs root=/dev/ram rw " \
671 "console=$consoledev,$baudrate $othbootargs;" \
672 "tftp $ramdiskaddr $ramdiskfile;" \
673 "tftp $loadaddr $bootfile;" \
674 "tftp $fdtaddr $fdtfile;" \
675 "bootm $loadaddr $ramdiskaddr $fdtaddr"
676
677#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
678
679#endif
680