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6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10
11
12
13#include <asm/config_mpc85xx.h>
14
15#ifdef CONFIG_RAMBOOT_PBL
16
17#ifndef CONFIG_SECURE_BOOT
18#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
19#else
20#define CONFIG_SYS_FSL_PBL_PBI \
21 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
22#endif
23
24#define CONFIG_SPL_FLUSH_IMAGE
25#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
26#define CONFIG_SYS_TEXT_BASE 0x30001000
27#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
28#define CONFIG_SPL_PAD_TO 0x40000
29#define CONFIG_SPL_MAX_SIZE 0x28000
30#ifdef CONFIG_SPL_BUILD
31#define CONFIG_SPL_SKIP_RELOCATE
32#define CONFIG_SPL_COMMON_INIT_DDR
33#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
34#define CONFIG_SYS_NO_FLASH
35#endif
36#define RESET_VECTOR_OFFSET 0x27FFC
37#define BOOT_PAGE_OFFSET 0x27000
38
39#ifdef CONFIG_NAND
40#ifdef CONFIG_SECURE_BOOT
41#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
42
43
44
45
46#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
47 CONFIG_U_BOOT_HDR_SIZE)
48#else
49#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
50#endif
51#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
52#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
53#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
54#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
55#ifdef CONFIG_TARGET_T1040RDB
56#define CONFIG_SYS_FSL_PBL_RCW \
57$(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
58#endif
59#ifdef CONFIG_TARGET_T1042RDB_PI
60#define CONFIG_SYS_FSL_PBL_RCW \
61$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
62#endif
63#ifdef CONFIG_TARGET_T1042RDB
64#define CONFIG_SYS_FSL_PBL_RCW \
65$(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
66#endif
67#ifdef CONFIG_TARGET_T1040D4RDB
68#define CONFIG_SYS_FSL_PBL_RCW \
69$(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
70#endif
71#ifdef CONFIG_TARGET_T1042D4RDB
72#define CONFIG_SYS_FSL_PBL_RCW \
73$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
74#endif
75#define CONFIG_SPL_NAND_BOOT
76#endif
77
78#ifdef CONFIG_SPIFLASH
79#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
80#define CONFIG_SPL_SPI_FLASH_MINIMAL
81#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
82#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
83#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
84#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
85#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
86#ifndef CONFIG_SPL_BUILD
87#define CONFIG_SYS_MPC85XX_NO_RESETVEC
88#endif
89#ifdef CONFIG_TARGET_T1040RDB
90#define CONFIG_SYS_FSL_PBL_RCW \
91$(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
92#endif
93#ifdef CONFIG_TARGET_T1042RDB_PI
94#define CONFIG_SYS_FSL_PBL_RCW \
95$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
96#endif
97#ifdef CONFIG_TARGET_T1042RDB
98#define CONFIG_SYS_FSL_PBL_RCW \
99$(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
100#endif
101#ifdef CONFIG_TARGET_T1040D4RDB
102#define CONFIG_SYS_FSL_PBL_RCW \
103$(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
104#endif
105#ifdef CONFIG_TARGET_T1042D4RDB
106#define CONFIG_SYS_FSL_PBL_RCW \
107$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
108#endif
109#define CONFIG_SPL_SPI_BOOT
110#endif
111
112#ifdef CONFIG_SDCARD
113#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
114#define CONFIG_SPL_MMC_MINIMAL
115#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
116#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
117#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
118#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
119#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
120#ifndef CONFIG_SPL_BUILD
121#define CONFIG_SYS_MPC85XX_NO_RESETVEC
122#endif
123#ifdef CONFIG_TARGET_T1040RDB
124#define CONFIG_SYS_FSL_PBL_RCW \
125$(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
126#endif
127#ifdef CONFIG_TARGET_T1042RDB_PI
128#define CONFIG_SYS_FSL_PBL_RCW \
129$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
130#endif
131#ifdef CONFIG_TARGET_T1042RDB
132#define CONFIG_SYS_FSL_PBL_RCW \
133$(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
134#endif
135#ifdef CONFIG_TARGET_T1040D4RDB
136#define CONFIG_SYS_FSL_PBL_RCW \
137$(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
138#endif
139#ifdef CONFIG_TARGET_T1042D4RDB
140#define CONFIG_SYS_FSL_PBL_RCW \
141$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
142#endif
143#define CONFIG_SPL_MMC_BOOT
144#endif
145
146#endif
147
148
149#define CONFIG_SYS_BOOK3E_HV
150#define CONFIG_MP
151
152
153#define CONFIG_DEEP_SLEEP
154#if defined(CONFIG_DEEP_SLEEP)
155#define CONFIG_BOARD_EARLY_INIT_F
156#endif
157
158#ifndef CONFIG_SYS_TEXT_BASE
159#define CONFIG_SYS_TEXT_BASE 0xeff40000
160#endif
161
162#ifndef CONFIG_RESET_VECTOR_ADDRESS
163#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
164#endif
165
166#define CONFIG_SYS_FSL_CPC
167#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
168#define CONFIG_FSL_IFC
169#define CONFIG_FSL_CAAM
170#define CONFIG_PCI_INDIRECT_BRIDGE
171#define CONFIG_PCIE1
172#define CONFIG_PCIE2
173#define CONFIG_PCIE3
174#define CONFIG_PCIE4
175
176#define CONFIG_FSL_PCI_INIT
177#define CONFIG_SYS_PCI_64BIT
178
179#define CONFIG_ENV_OVERWRITE
180
181#ifndef CONFIG_SYS_NO_FLASH
182#define CONFIG_FLASH_CFI_DRIVER
183#define CONFIG_SYS_FLASH_CFI
184#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
185#endif
186
187#if defined(CONFIG_SPIFLASH)
188#define CONFIG_SYS_EXTRA_ENV_RELOC
189#define CONFIG_ENV_IS_IN_SPI_FLASH
190#define CONFIG_ENV_SIZE 0x2000
191#define CONFIG_ENV_OFFSET 0x100000
192#define CONFIG_ENV_SECT_SIZE 0x10000
193#elif defined(CONFIG_SDCARD)
194#define CONFIG_SYS_EXTRA_ENV_RELOC
195#define CONFIG_ENV_IS_IN_MMC
196#define CONFIG_SYS_MMC_ENV_DEV 0
197#define CONFIG_ENV_SIZE 0x2000
198#define CONFIG_ENV_OFFSET (512 * 0x800)
199#elif defined(CONFIG_NAND)
200#ifdef CONFIG_SECURE_BOOT
201#define CONFIG_RAMBOOT_NAND
202#define CONFIG_BOOTSCRIPT_COPY_RAM
203#endif
204#define CONFIG_SYS_EXTRA_ENV_RELOC
205#define CONFIG_ENV_IS_IN_NAND
206#define CONFIG_ENV_SIZE 0x2000
207#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
208#else
209#define CONFIG_ENV_IS_IN_FLASH
210#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
211#define CONFIG_ENV_SIZE 0x2000
212#define CONFIG_ENV_SECT_SIZE 0x20000
213#endif
214
215#define CONFIG_SYS_CLK_FREQ 100000000
216#define CONFIG_DDR_CLK_FREQ 66666666
217
218
219
220
221#define CONFIG_SYS_CACHE_STASHING
222#define CONFIG_BACKSIDE_L2_CACHE
223#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
224#define CONFIG_BTB
225#define CONFIG_DDR_ECC
226#ifdef CONFIG_DDR_ECC
227#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
228#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
229#endif
230
231#define CONFIG_ENABLE_36BIT_PHYS
232
233#define CONFIG_ADDR_MAP
234#define CONFIG_SYS_NUM_ADDR_MAP 64
235
236#define CONFIG_SYS_MEMTEST_START 0x00200000
237#define CONFIG_SYS_MEMTEST_END 0x00400000
238#define CONFIG_SYS_ALT_MEMTEST
239#define CONFIG_PANIC_HANG
240
241
242
243
244#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
245
246
247
248
249
250#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
251#define CONFIG_SYS_L3_SIZE 256 << 10
252#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
253#ifdef CONFIG_RAMBOOT_PBL
254#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
255#endif
256#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
257#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
258#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
259#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
260
261#define CONFIG_SYS_DCSRBAR 0xf0000000
262#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
263
264
265
266
267#define CONFIG_VERY_BIG_RAM
268#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
269#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
270
271#define CONFIG_DIMM_SLOTS_PER_CTLR 1
272#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
273
274#define CONFIG_DDR_SPD
275
276#define CONFIG_SYS_SPD_BUS_NUM 0
277#define SPD_EEPROM_ADDRESS 0x51
278
279#define CONFIG_SYS_SDRAM_SIZE 4096
280
281
282
283
284#define CONFIG_SYS_FLASH_BASE 0xe8000000
285#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
286
287#define CONFIG_SYS_NOR_CSPR_EXT (0xf)
288#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
289 CSPR_PORT_SIZE_16 | \
290 CSPR_MSEL_NOR | \
291 CSPR_V)
292#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
293
294
295
296
297#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
298
299
300#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
301#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
302 FTIM0_NOR_TEADC(0x5) | \
303 FTIM0_NOR_TEAHC(0x5))
304#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
305 FTIM1_NOR_TRAD_NOR(0x1A) |\
306 FTIM1_NOR_TSEQRAD_NOR(0x13))
307#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
308 FTIM2_NOR_TCH(0x4) | \
309 FTIM2_NOR_TWPH(0x0E) | \
310 FTIM2_NOR_TWP(0x1c))
311#define CONFIG_SYS_NOR_FTIM3 0x0
312
313#define CONFIG_SYS_FLASH_QUIET_TEST
314#define CONFIG_FLASH_SHOW_PROGRESS 45
315
316#define CONFIG_SYS_MAX_FLASH_BANKS 2
317#define CONFIG_SYS_MAX_FLASH_SECT 1024
318#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
319#define CONFIG_SYS_FLASH_WRITE_TOUT 500
320
321#define CONFIG_SYS_FLASH_EMPTY_INFO
322#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
323
324
325#define CPLD_LBMAP_MASK 0x3F
326#define CPLD_BANK_SEL_MASK 0x07
327#define CPLD_BANK_OVERRIDE 0x40
328#define CPLD_LBMAP_ALTBANK 0x44
329#define CPLD_LBMAP_DFLTBANK 0x40
330#define CPLD_LBMAP_RESET 0xFF
331#define CPLD_LBMAP_SHIFT 0x03
332
333#if defined(CONFIG_TARGET_T1042RDB_PI)
334#define CPLD_DIU_SEL_DFP 0x80
335#elif defined(CONFIG_TARGET_T1042D4RDB)
336#define CPLD_DIU_SEL_DFP 0xc0
337#endif
338
339#if defined(CONFIG_TARGET_T1040D4RDB)
340#define CPLD_INT_MASK_ALL 0xFF
341#define CPLD_INT_MASK_THERM 0x80
342#define CPLD_INT_MASK_DVI_DFP 0x40
343#define CPLD_INT_MASK_QSGMII1 0x20
344#define CPLD_INT_MASK_QSGMII2 0x10
345#define CPLD_INT_MASK_SGMI1 0x08
346#define CPLD_INT_MASK_SGMI2 0x04
347#define CPLD_INT_MASK_TDMR1 0x02
348#define CPLD_INT_MASK_TDMR2 0x01
349#endif
350
351#define CONFIG_SYS_CPLD_BASE 0xffdf0000
352#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
353#define CONFIG_SYS_CSPR2_EXT (0xf)
354#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
355 | CSPR_PORT_SIZE_8 \
356 | CSPR_MSEL_GPCM \
357 | CSPR_V)
358#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
359#define CONFIG_SYS_CSOR2 0x0
360
361#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
362 FTIM0_GPCM_TEADC(0x0e) | \
363 FTIM0_GPCM_TEAHC(0x0e))
364#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
365 FTIM1_GPCM_TRAD(0x1f))
366#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
367 FTIM2_GPCM_TCH(0x8) | \
368 FTIM2_GPCM_TWP(0x1f))
369#define CONFIG_SYS_CS2_FTIM3 0x0
370
371
372#define CONFIG_NAND_FSL_IFC
373#define CONFIG_SYS_NAND_BASE 0xff800000
374#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
375
376#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
377#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
378 | CSPR_PORT_SIZE_8 \
379 | CSPR_MSEL_NAND \
380 | CSPR_V)
381#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
382
383#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
384 | CSOR_NAND_ECC_DEC_EN \
385 | CSOR_NAND_ECC_MODE_4 \
386 | CSOR_NAND_RAL_3 \
387 | CSOR_NAND_PGS_4K \
388 | CSOR_NAND_SPRZ_224 \
389 | CSOR_NAND_PB(64))
390
391#define CONFIG_SYS_NAND_ONFI_DETECTION
392
393
394#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
395 FTIM0_NAND_TWP(0x18) | \
396 FTIM0_NAND_TWCHT(0x07) | \
397 FTIM0_NAND_TWH(0x0a))
398#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
399 FTIM1_NAND_TWBE(0x39) | \
400 FTIM1_NAND_TRR(0x0e) | \
401 FTIM1_NAND_TRP(0x18))
402#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
403 FTIM2_NAND_TREH(0x0a) | \
404 FTIM2_NAND_TWHRE(0x1e))
405#define CONFIG_SYS_NAND_FTIM3 0x0
406
407#define CONFIG_SYS_NAND_DDR_LAW 11
408#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
409#define CONFIG_SYS_MAX_NAND_DEVICE 1
410#define CONFIG_CMD_NAND
411
412#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
413
414#if defined(CONFIG_NAND)
415#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
416#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
417#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
418#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
419#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
420#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
421#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
422#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
423#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
424#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
425#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
426#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
427#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
428#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
429#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
430#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
431#else
432#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
433#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
434#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
435#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
436#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
437#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
438#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
439#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
440#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
441#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
442#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
443#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
444#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
445#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
446#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
447#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
448#endif
449
450#ifdef CONFIG_SPL_BUILD
451#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
452#else
453#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
454#endif
455
456#if defined(CONFIG_RAMBOOT_PBL)
457#define CONFIG_SYS_RAMBOOT
458#endif
459
460#ifdef CONFIG_SYS_FSL_ERRATUM_A008044
461#if defined(CONFIG_NAND)
462#define CONFIG_A008044_WORKAROUND
463#endif
464#endif
465
466#define CONFIG_BOARD_EARLY_INIT_R
467#define CONFIG_MISC_INIT_R
468
469#define CONFIG_HWCONFIG
470
471
472#define CONFIG_L1_INIT_RAM
473#define CONFIG_SYS_INIT_RAM_LOCK
474#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
475#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
476#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
477
478#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
479 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
480 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
481#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
482
483#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
484 GENERATED_GBL_DATA_SIZE)
485#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
486
487#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
488#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
489
490
491
492
493
494#define CONFIG_CONS_INDEX 1
495#define CONFIG_SYS_NS16550_SERIAL
496#define CONFIG_SYS_NS16550_REG_SIZE 1
497#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
498
499#define CONFIG_SYS_BAUDRATE_TABLE \
500 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
501
502#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
503#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
504#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
505#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
506
507#if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
508
509#define CONFIG_FSL_DIU_FB
510
511#ifdef CONFIG_FSL_DIU_FB
512#define CONFIG_FSL_DIU_CH7301
513#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
514#define CONFIG_CMD_BMP
515#define CONFIG_VIDEO_LOGO
516#define CONFIG_VIDEO_BMP_LOGO
517#endif
518#endif
519
520
521#define CONFIG_SYS_I2C
522#define CONFIG_SYS_I2C_FSL
523#define CONFIG_SYS_FSL_I2C_SPEED 400000
524#define CONFIG_SYS_FSL_I2C2_SPEED 400000
525#define CONFIG_SYS_FSL_I2C3_SPEED 400000
526#define CONFIG_SYS_FSL_I2C4_SPEED 400000
527#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
528#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
529#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
530#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
531#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
532#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
533#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
534#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
535
536
537#define I2C_MUX_PCA_ADDR 0x70
538#define I2C_MUX_CH_DEFAULT 0x8
539
540#if defined(CONFIG_TARGET_T1042RDB_PI) || \
541 defined(CONFIG_TARGET_T1040D4RDB) || \
542 defined(CONFIG_TARGET_T1042D4RDB)
543
544#define CONFIG_SYS_I2C_LDI_ADDR 0x38
545#define CONFIG_SYS_I2C_DVI_ADDR 0x75
546
547
548
549
550#define RTC
551#define CONFIG_RTC_DS1337 1
552#define CONFIG_SYS_I2C_RTC_ADDR 0x68
553
554
555#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
556#endif
557
558
559
560
561#define CONFIG_SPI_FLASH_BAR
562#define CONFIG_SF_DEFAULT_SPEED 10000000
563#define CONFIG_SF_DEFAULT_MODE 0
564#define CONFIG_ENV_SPI_BUS 0
565#define CONFIG_ENV_SPI_CS 0
566#define CONFIG_ENV_SPI_MAX_HZ 10000000
567#define CONFIG_ENV_SPI_MODE 0
568
569
570
571
572
573
574#ifdef CONFIG_PCI
575
576#ifdef CONFIG_PCIE1
577#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
578#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
579#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
580#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
581#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
582#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
583#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
584#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
585#endif
586
587
588#ifdef CONFIG_PCIE2
589#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
590#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
591#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
592#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
593#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
594#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
595#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
596#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
597#endif
598
599
600#ifdef CONFIG_PCIE3
601#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
602#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
603#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
604#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000
605#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
606#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
607#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
608#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
609#endif
610
611
612#ifdef CONFIG_PCIE4
613#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
614#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
615#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
616#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000
617#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
618#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
619#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
620#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000
621#endif
622
623#define CONFIG_PCI_SCAN_SHOW
624#define CONFIG_DOS_PARTITION
625#endif
626
627
628#define CONFIG_FSL_SATA_V2
629#ifdef CONFIG_FSL_SATA_V2
630#define CONFIG_LIBATA
631#define CONFIG_FSL_SATA
632
633#define CONFIG_SYS_SATA_MAX_DEVICE 1
634#define CONFIG_SATA1
635#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
636#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
637
638#define CONFIG_LBA48
639#define CONFIG_CMD_SATA
640#define CONFIG_DOS_PARTITION
641#endif
642
643
644
645
646#define CONFIG_HAS_FSL_DR_USB
647
648#ifdef CONFIG_HAS_FSL_DR_USB
649#define CONFIG_USB_EHCI
650
651#ifdef CONFIG_USB_EHCI
652#define CONFIG_USB_EHCI_FSL
653#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
654#endif
655#endif
656
657#ifdef CONFIG_MMC
658#define CONFIG_FSL_ESDHC
659#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
660#define CONFIG_GENERIC_MMC
661#define CONFIG_DOS_PARTITION
662#endif
663
664
665#ifndef CONFIG_NOBQFMAN
666#define CONFIG_SYS_DPAA_QBMAN
667#define CONFIG_SYS_BMAN_NUM_PORTALS 10
668#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
669#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
670#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
671#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
672#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
673#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
674#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
675#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
676 CONFIG_SYS_BMAN_CENA_SIZE)
677#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
678#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
679#define CONFIG_SYS_QMAN_NUM_PORTALS 10
680#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
681#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
682#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
683#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
684#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
685#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
686#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
687#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
688 CONFIG_SYS_QMAN_CENA_SIZE)
689#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
690#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
691
692#define CONFIG_SYS_DPAA_FMAN
693#define CONFIG_SYS_DPAA_PME
694
695#define CONFIG_QE
696#define CONFIG_U_QE
697
698
699#if defined(CONFIG_SPIFLASH)
700
701
702
703
704#define CONFIG_SYS_QE_FW_IN_SPIFLASH
705#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
706#elif defined(CONFIG_SDCARD)
707
708
709
710
711
712#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
713#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
714#elif defined(CONFIG_NAND)
715#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
716#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
717#else
718#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
719#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
720#endif
721
722#if defined(CONFIG_SPIFLASH)
723#define CONFIG_SYS_QE_FW_ADDR 0x130000
724#elif defined(CONFIG_SDCARD)
725#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
726#elif defined(CONFIG_NAND)
727#define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
728#else
729#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
730#endif
731
732#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
733#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
734#endif
735
736#ifdef CONFIG_SYS_DPAA_FMAN
737#define CONFIG_FMAN_ENET
738#define CONFIG_PHY_VITESSE
739#define CONFIG_PHY_REALTEK
740#endif
741
742#ifdef CONFIG_FMAN_ENET
743#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
744#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
745#elif defined(CONFIG_TARGET_T1040D4RDB)
746#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
747#elif defined(CONFIG_TARGET_T1042D4RDB)
748#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
749#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
750#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
751#endif
752
753#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
754#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
755#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
756#else
757#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
758#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
759#endif
760
761
762#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
763#define CONFIG_VSC9953
764#define CONFIG_CMD_ETHSW
765#ifdef CONFIG_TARGET_T1040RDB
766#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
767#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
768#else
769#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
770#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
771#endif
772#endif
773
774#define CONFIG_MII
775#define CONFIG_ETHPRIME "FM1@DTSEC4"
776#define CONFIG_PHY_GIGE
777#endif
778
779
780
781
782#define CONFIG_LOADS_ECHO
783#define CONFIG_SYS_LOADS_BAUD_CHANGE
784
785
786
787
788#ifdef CONFIG_TARGET_T1042RDB_PI
789#define CONFIG_CMD_DATE
790#endif
791#define CONFIG_CMD_ERRATA
792#define CONFIG_CMD_IRQ
793#define CONFIG_CMD_REGINFO
794
795#ifdef CONFIG_PCI
796#define CONFIG_CMD_PCI
797#endif
798
799
800#ifdef CONFIG_FSL_CAAM
801#define CONFIG_CMD_HASH
802#define CONFIG_SHA_HW_ACCEL
803#endif
804
805
806
807
808#define CONFIG_SYS_LONGHELP
809#define CONFIG_CMDLINE_EDITING
810#define CONFIG_AUTO_COMPLETE
811#define CONFIG_SYS_LOAD_ADDR 0x2000000
812#ifdef CONFIG_CMD_KGDB
813#define CONFIG_SYS_CBSIZE 1024
814#else
815#define CONFIG_SYS_CBSIZE 256
816#endif
817#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
818#define CONFIG_SYS_MAXARGS 16
819#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
820
821
822
823
824
825
826#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
827#define CONFIG_SYS_BOOTM_LEN (64 << 20)
828
829#ifdef CONFIG_CMD_KGDB
830#define CONFIG_KGDB_BAUDRATE 230400
831#endif
832
833
834
835
836#ifndef CONFIG_SYS_NO_FLASH
837#define CONFIG_MTD_DEVICE
838#define CONFIG_MTD_PARTITIONS
839#define CONFIG_CMD_MTDPARTS
840#define CONFIG_FLASH_CFI_MTD
841#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
842 "spi0=spife110000.0"
843#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
844 "128k(dtb),96m(fs),-(user);"\
845 "fff800000.flash:2m(uboot),9m(kernel),"\
846 "128k(dtb),96m(fs),-(user);spife110000.0:" \
847 "2m(uboot),9m(kernel),128k(dtb),-(user)"
848#endif
849
850
851
852
853#define CONFIG_ROOTPATH "/opt/nfsroot"
854#define CONFIG_BOOTFILE "uImage"
855#define CONFIG_UBOOTPATH "u-boot.bin"
856
857
858#define CONFIG_LOADADDR 1000000
859
860
861#define CONFIG_BAUDRATE 115200
862
863#define __USB_PHY_TYPE utmi
864#define RAMDISKFILE "t104xrdb/ramdisk.uboot"
865
866#ifdef CONFIG_TARGET_T1040RDB
867#define FDTFILE "t1040rdb/t1040rdb.dtb"
868#elif defined(CONFIG_TARGET_T1042RDB_PI)
869#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
870#elif defined(CONFIG_TARGET_T1042RDB)
871#define FDTFILE "t1042rdb/t1042rdb.dtb"
872#elif defined(CONFIG_TARGET_T1040D4RDB)
873#define FDTFILE "t1042rdb/t1040d4rdb.dtb"
874#elif defined(CONFIG_TARGET_T1042D4RDB)
875#define FDTFILE "t1042rdb/t1042d4rdb.dtb"
876#endif
877
878#ifdef CONFIG_FSL_DIU_FB
879#define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
880#else
881#define DIU_ENVIRONMENT
882#endif
883
884#define CONFIG_EXTRA_ENV_SETTINGS \
885 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
886 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
887 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
888 "netdev=eth0\0" \
889 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
890 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
891 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
892 "tftpflash=tftpboot $loadaddr $uboot && " \
893 "protect off $ubootaddr +$filesize && " \
894 "erase $ubootaddr +$filesize && " \
895 "cp.b $loadaddr $ubootaddr $filesize && " \
896 "protect on $ubootaddr +$filesize && " \
897 "cmp.b $loadaddr $ubootaddr $filesize\0" \
898 "consoledev=ttyS0\0" \
899 "ramdiskaddr=2000000\0" \
900 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
901 "fdtaddr=1e00000\0" \
902 "fdtfile=" __stringify(FDTFILE) "\0" \
903 "bdev=sda3\0"
904
905#define CONFIG_LINUX \
906 "setenv bootargs root=/dev/ram rw " \
907 "console=$consoledev,$baudrate $othbootargs;" \
908 "setenv ramdiskaddr 0x02000000;" \
909 "setenv fdtaddr 0x00c00000;" \
910 "setenv loadaddr 0x1000000;" \
911 "bootm $loadaddr $ramdiskaddr $fdtaddr"
912
913#define CONFIG_HDBOOT \
914 "setenv bootargs root=/dev/$bdev rw " \
915 "console=$consoledev,$baudrate $othbootargs;" \
916 "tftp $loadaddr $bootfile;" \
917 "tftp $fdtaddr $fdtfile;" \
918 "bootm $loadaddr - $fdtaddr"
919
920#define CONFIG_NFSBOOTCOMMAND \
921 "setenv bootargs root=/dev/nfs rw " \
922 "nfsroot=$serverip:$rootpath " \
923 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
924 "console=$consoledev,$baudrate $othbootargs;" \
925 "tftp $loadaddr $bootfile;" \
926 "tftp $fdtaddr $fdtfile;" \
927 "bootm $loadaddr - $fdtaddr"
928
929#define CONFIG_RAMBOOTCOMMAND \
930 "setenv bootargs root=/dev/ram rw " \
931 "console=$consoledev,$baudrate $othbootargs;" \
932 "tftp $ramdiskaddr $ramdiskfile;" \
933 "tftp $loadaddr $bootfile;" \
934 "tftp $fdtaddr $fdtfile;" \
935 "bootm $loadaddr $ramdiskaddr $fdtaddr"
936
937#define CONFIG_BOOTCOMMAND CONFIG_LINUX
938
939#include <asm/fsl_secure_boot.h>
940
941#endif
942
