1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ 21#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */ 22 23#define CONFIG_SYS_TEXT_BASE 0x40000000 24 25#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 26#define CONFIG_SYS_SMC_RXBUFLEN 128 27#define CONFIG_SYS_MAXIDLE 10 28#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 29 30#define CONFIG_BOOTCOUNT_LIMIT 31 32 33#define CONFIG_BOARD_TYPES 1 /* support board types */ 34 35#define CONFIG_PREBOOT "echo;" \ 36 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 37 "echo" 38 39#undef CONFIG_BOOTARGS 40 41#define CONFIG_EXTRA_ENV_SETTINGS \ 42 "netdev=eth0\0" \ 43 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 44 "nfsroot=${serverip}:${rootpath}\0" \ 45 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 46 "addip=setenv bootargs ${bootargs} " \ 47 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 48 ":${hostname}:${netdev}:off panic=1\0" \ 49 "flash_nfs=run nfsargs addip;" \ 50 "bootm ${kernel_addr}\0" \ 51 "flash_self=run ramargs addip;" \ 52 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 53 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 54 "rootpath=/opt/eldk/ppc_8xx\0" \ 55 "hostname=TQM860L\0" \ 56 "bootfile=TQM860L/uImage\0" \ 57 "fdt_addr=40040000\0" \ 58 "kernel_addr=40060000\0" \ 59 "ramdisk_addr=40200000\0" \ 60 "u-boot=TQM860L/u-image.bin\0" \ 61 "load=tftp 200000 ${u-boot}\0" \ 62 "update=prot off 40000000 +${filesize};" \ 63 "era 40000000 +${filesize};" \ 64 "cp.b 200000 40000000 ${filesize};" \ 65 "sete filesize;save\0" \ 66 "" 67#define CONFIG_BOOTCOMMAND "run flash_self" 68 69#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 70#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 71 72#undef CONFIG_WATCHDOG /* watchdog disabled */ 73 74#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 75 76#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 77 78/* 79 * BOOTP options 80 */ 81#define CONFIG_BOOTP_SUBNETMASK 82#define CONFIG_BOOTP_GATEWAY 83#define CONFIG_BOOTP_HOSTNAME 84#define CONFIG_BOOTP_BOOTPATH 85#define CONFIG_BOOTP_BOOTFILESIZE 86 87#define CONFIG_MAC_PARTITION 88#define CONFIG_DOS_PARTITION 89 90#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 91 92/* 93 * Command line configuration. 94 */ 95#define CONFIG_CMD_DATE 96#define CONFIG_CMD_IDE 97#define CONFIG_CMD_JFFS2 98 99#define CONFIG_NETCONSOLE 100 101/* 102 * Miscellaneous configurable options 103 */ 104#define CONFIG_SYS_LONGHELP /* undef to save memory */ 105 106#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 107 108#if defined(CONFIG_CMD_KGDB) 109#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 110#else 111#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 112#endif 113#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 114#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 115#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 116 117#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 118#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 119 120#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 121 122/* 123 * Low Level Configuration Settings 124 * (address mappings, register initial values, etc.) 125 * You should know what you are doing if you make changes here. 126 */ 127/*----------------------------------------------------------------------- 128 * Internal Memory Mapped Register 129 */ 130#define CONFIG_SYS_IMMR 0xFFF00000 131 132/*----------------------------------------------------------------------- 133 * Definitions for initial stack pointer and data area (in DPRAM) 134 */ 135#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 136#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 137#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 138#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 139 140/*----------------------------------------------------------------------- 141 * Start addresses for the final memory configuration 142 * (Set up by the startup code) 143 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 144 */ 145#define CONFIG_SYS_SDRAM_BASE 0x00000000 146#define CONFIG_SYS_FLASH_BASE 0x40000000 147#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 148#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 149#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 150 151/* 152 * For booting Linux, the board info and command line data 153 * have to be in the first 8 MB of memory, since this is 154 * the maximum mapped by the Linux kernel during initialization. 155 */ 156#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 157 158/*----------------------------------------------------------------------- 159 * FLASH organization 160 */ 161 162/* use CFI flash driver */ 163#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 164#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 165#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 166#define CONFIG_SYS_FLASH_EMPTY_INFO 167#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 168#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 169#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 170 171#define CONFIG_ENV_IS_IN_FLASH 1 172#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 173#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 174 175/* Address and size of Redundant Environment Sector */ 176#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 177#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 178 179#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 180 181#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 182 183/*----------------------------------------------------------------------- 184 * Dynamic MTD partition support 185 */ 186#define CONFIG_CMD_MTDPARTS 187#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 188#define CONFIG_FLASH_CFI_MTD 189#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" 190 191#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ 192 "128k(dtb)," \ 193 "1664k(kernel)," \ 194 "2m(rootfs)," \ 195 "4m(data)" 196 197/*----------------------------------------------------------------------- 198 * Hardware Information Block 199 */ 200#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 201#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 202#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 203 204/*----------------------------------------------------------------------- 205 * Cache Configuration 206 */ 207#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 208#if defined(CONFIG_CMD_KGDB) 209#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 210#endif 211 212/*----------------------------------------------------------------------- 213 * SYPCR - System Protection Control 11-9 214 * SYPCR can only be written once after reset! 215 *----------------------------------------------------------------------- 216 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 217 */ 218#if defined(CONFIG_WATCHDOG) 219#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 220 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 221#else 222#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 223#endif 224 225/*----------------------------------------------------------------------- 226 * SIUMCR - SIU Module Configuration 11-6 227 *----------------------------------------------------------------------- 228 * PCMCIA config., multi-function pin tri-state 229 */ 230#ifndef CONFIG_CAN_DRIVER 231#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 232#else /* we must activate GPL5 in the SIUMCR for CAN */ 233#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 234#endif /* CONFIG_CAN_DRIVER */ 235 236/*----------------------------------------------------------------------- 237 * TBSCR - Time Base Status and Control 11-26 238 *----------------------------------------------------------------------- 239 * Clear Reference Interrupt Status, Timebase freezing enabled 240 */ 241#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 242 243/*----------------------------------------------------------------------- 244 * RTCSC - Real-Time Clock Status and Control Register 11-27 245 *----------------------------------------------------------------------- 246 */ 247#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 248 249/*----------------------------------------------------------------------- 250 * PISCR - Periodic Interrupt Status and Control 11-31 251 *----------------------------------------------------------------------- 252 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 253 */ 254#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 255 256/*----------------------------------------------------------------------- 257 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 258 *----------------------------------------------------------------------- 259 * Reset PLL lock status sticky bit, timer expired status bit and timer 260 * interrupt status bit 261 */ 262#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 263 264/*----------------------------------------------------------------------- 265 * SCCR - System Clock and reset Control Register 15-27 266 *----------------------------------------------------------------------- 267 * Set clock output, timebase and RTC source and divider, 268 * power management and some other internal clocks 269 */ 270#define SCCR_MASK SCCR_EBDF11 271#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 272 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 273 SCCR_DFALCD00) 274 275/*----------------------------------------------------------------------- 276 * PCMCIA stuff 277 *----------------------------------------------------------------------- 278 * 279 */ 280#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 281#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 282#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 283#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 284#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 285#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 286#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 287#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 288 289/*----------------------------------------------------------------------- 290 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 291 *----------------------------------------------------------------------- 292 */ 293 294#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 295#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 296 297#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 298#undef CONFIG_IDE_LED /* LED for ide not supported */ 299#undef CONFIG_IDE_RESET /* reset for ide not supported */ 300 301#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 302#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 303 304#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 305 306#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 307 308/* Offset for data I/O */ 309#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 310 311/* Offset for normal register accesses */ 312#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 313 314/* Offset for alternate registers */ 315#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 316 317/*----------------------------------------------------------------------- 318 * 319 *----------------------------------------------------------------------- 320 * 321 */ 322#define CONFIG_SYS_DER 0 323 324/* 325 * Init Memory Controller: 326 * 327 * BR0/1 and OR0/1 (FLASH) 328 */ 329 330#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 331#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 332 333/* used to re-map FLASH both when starting from SRAM or FLASH: 334 * restrict access enough to keep SRAM working (if any) 335 * but not too much to meddle with FLASH accesses 336 */ 337#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 338#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 339 340/* 341 * FLASH timing: 342 */ 343#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 344 OR_SCY_3_CLK | OR_EHTR | OR_BI) 345 346#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 347#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 348#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 349 350#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 351#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 352#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 353 354/* 355 * BR2/3 and OR2/3 (SDRAM) 356 * 357 */ 358#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 359#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 360#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 361 362/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 363#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 364 365#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 366#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 367 368#ifndef CONFIG_CAN_DRIVER 369#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 370#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 371#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 372#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 373#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 374#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 375#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 376 BR_PS_8 | BR_MS_UPMB | BR_V ) 377#endif /* CONFIG_CAN_DRIVER */ 378 379/* 380 * Memory Periodic Timer Prescaler 381 * 382 * The Divider for PTA (refresh timer) configuration is based on an 383 * example SDRAM configuration (64 MBit, one bank). The adjustment to 384 * the number of chip selects (NCS) and the actually needed refresh 385 * rate is done by setting MPTPR. 386 * 387 * PTA is calculated from 388 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 389 * 390 * gclk CPU clock (not bus clock!) 391 * Trefresh Refresh cycle * 4 (four word bursts used) 392 * 393 * 4096 Rows from SDRAM example configuration 394 * 1000 factor s -> ms 395 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 396 * 4 Number of refresh cycles per period 397 * 64 Refresh cycle in ms per number of rows 398 * -------------------------------------------- 399 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 400 * 401 * 50 MHz => 50.000.000 / Divider = 98 402 * 66 Mhz => 66.000.000 / Divider = 129 403 * 80 Mhz => 80.000.000 / Divider = 156 404 */ 405 406#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 407#define CONFIG_SYS_MAMR_PTA 98 408 409/* 410 * For 16 MBit, refresh rates could be 31.3 us 411 * (= 64 ms / 2K = 125 / quad bursts). 412 * For a simpler initialization, 15.6 us is used instead. 413 * 414 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 415 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 416 */ 417#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 418#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 419 420/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 421#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 422#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 423 424/* 425 * MAMR settings for SDRAM 426 */ 427 428/* 8 column SDRAM */ 429#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 430 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 431 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 432/* 9 column SDRAM */ 433#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 434 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 435 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 436 437#define CONFIG_SCC1_ENET 438#define CONFIG_FEC_ENET 439#define CONFIG_ETHPRIME "SCC" 440 441#define CONFIG_HWCONFIG 1 442 443#endif /* __CONFIG_H */ 444