LXR uboot/include/configs/cm

   1/*
   2 * (C) Copyright 2011 CompuLab, Ltd.
   3 * Mike Rapoport <mike@compulab.co.il>
   4 * Igor Grinberg <grinberg@compulab.co.il>
   5 *
   6 * Based on omap3_beagle.h
   7 * (C) Copyright 2006-2008
   8 * Texas Instruments.
   9 * Richard Woodruff <r-woodruff2@ti.com>
  10 * Syed Mohammed Khasim <x0khasim@ti.com>
  11 *
  12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
  13 *
  14 * SPDX-License-Identifier:     GPL-2.0+
  15 */
  16
  17#ifndef __CONFIG_H
  18#define __CONFIG_H
  19
  20#define CONFIG_SYS_CACHELINE_SIZE       64
  21
  22/*
  23 * High Level Configuration Options
  24 */
  25#define CONFIG_OMAP     /* in a TI OMAP core */
  26#define CONFIG_OMAP_GPIO
  27#define CONFIG_CM_T3X   /* working with CM-T35 and CM-T3730 */
  28/* Common ARM Erratas */
  29#define CONFIG_ARM_ERRATA_454179
  30#define CONFIG_ARM_ERRATA_430973
  31#define CONFIG_ARM_ERRATA_621766
  32
  33#define CONFIG_SDRC     /* The chip has SDRC controller */
  34
  35#include <asm/arch/cpu.h>               /* get chip and board defs */
  36#include <asm/arch/omap.h>
  37
  38/* Clock Defines */
  39#define V_OSCK                  26000000        /* Clock output from T2 */
  40#define V_SCLK                  (V_OSCK >> 1)
  41
  42#define CONFIG_MISC_INIT_R
  43
  44#define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  45#define CONFIG_SETUP_MEMORY_TAGS
  46#define CONFIG_INITRD_TAG
  47#define CONFIG_REVISION_TAG
  48#define CONFIG_SERIAL_TAG
  49
  50/*
  51 * Size of malloc() pool
  52 */
  53#define CONFIG_ENV_SIZE         (16 << 10)      /* 16 KiB */
  54                                        /* Sector */
  55#define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + (128 << 10))
  56
  57/*
  58 * Hardware drivers
  59 */
  60
  61/*
  62 * NS16550 Configuration
  63 */
  64#define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  65
  66#define CONFIG_SYS_NS16550_SERIAL
  67#define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  68#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  69
  70/*
  71 * select serial console configuration
  72 */
  73#define CONFIG_CONS_INDEX               3
  74#define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  75#define CONFIG_SERIAL3                  3       /* UART3 */
  76
  77/* allow to overwrite serial and ethaddr */
  78#define CONFIG_ENV_OVERWRITE
  79#define CONFIG_BAUDRATE                 115200
  80#define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  81                                        115200}
  82
  83#define CONFIG_GENERIC_MMC
  84#define CONFIG_OMAP_HSMMC
  85#define CONFIG_DOS_PARTITION
  86
  87/* USB */
  88#define CONFIG_USB_OMAP3
  89#define CONFIG_USB_EHCI
  90#define CONFIG_USB_EHCI_OMAP
  91#define CONFIG_USB_MUSB_UDC
  92#define CONFIG_TWL4030_USB
  93
  94/* USB device configuration */
  95#define CONFIG_USB_DEVICE
  96#define CONFIG_USB_TTY
  97
  98/* commands to include */
  99#define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands */
 100#define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 101#define CONFIG_MTD_PARTITIONS
 102#define MTDIDS_DEFAULT          "nand0=nand"
 103#define MTDPARTS_DEFAULT        "mtdparts=nand:512k(x-loader),"\
 104                                "1920k(u-boot),256k(u-boot-env),"\
 105                                "4m(kernel),-(fs)"
 106
 107#define CONFIG_CMD_NAND         /* NAND support                 */
 108
 109#define CONFIG_SYS_NO_FLASH
 110#define CONFIG_SYS_I2C
 111#define CONFIG_SYS_OMAP24_I2C_SPEED     100000
 112#define CONFIG_SYS_OMAP24_I2C_SLAVE     1
 113#define CONFIG_SYS_I2C_OMAP34XX
 114#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 115#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 116#define CONFIG_SYS_I2C_EEPROM_BUS       0
 117#define CONFIG_I2C_MULTI_BUS
 118
 119/*
 120 * TWL4030
 121 */
 122#define CONFIG_TWL4030_POWER
 123#define CONFIG_TWL4030_LED
 124
 125/*
 126 * Board NAND Info.
 127 */
 128#define CONFIG_NAND_OMAP_GPMC
 129#define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 130                                                        /* to access nand */
 131#define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 132                                                        /* to access nand at */
 133                                                        /* CS0 */
 134#define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 135                                                        /* devices */
 136
 137/* Environment information */
 138#define CONFIG_EXTRA_ENV_SETTINGS \
 139        "loadaddr=0x82000000\0" \
 140        "usbtty=cdc_acm\0" \
 141        "console=ttyO2,115200n8\0" \
 142        "mpurate=500\0" \
 143        "vram=12M\0" \
 144        "dvimode=1024x768MR-16@60\0" \
 145        "defaultdisplay=dvi\0" \
 146        "mmcdev=0\0" \
 147        "mmcroot=/dev/mmcblk0p2 rw\0" \
 148        "mmcrootfstype=ext4 rootwait\0" \
 149        "nandroot=/dev/mtdblock4 rw\0" \
 150        "nandrootfstype=ubifs\0" \
 151        "mmcargs=setenv bootargs console=${console} " \
 152                "mpurate=${mpurate} " \
 153                "vram=${vram} " \
 154                "omapfb.mode=dvi:${dvimode} " \
 155                "omapdss.def_disp=${defaultdisplay} " \
 156                "root=${mmcroot} " \
 157                "rootfstype=${mmcrootfstype}\0" \
 158        "nandargs=setenv bootargs console=${console} " \
 159                "mpurate=${mpurate} " \
 160                "vram=${vram} " \
 161                "omapfb.mode=dvi:${dvimode} " \
 162                "omapdss.def_disp=${defaultdisplay} " \
 163                "root=${nandroot} " \
 164                "rootfstype=${nandrootfstype}\0" \
 165        "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 166        "bootscript=echo Running bootscript from mmc ...; " \
 167                "source ${loadaddr}\0" \
 168        "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 169        "mmcboot=echo Booting from mmc ...; " \
 170                "run mmcargs; " \
 171                "bootm ${loadaddr}\0" \
 172        "nandboot=echo Booting from nand ...; " \
 173                "run nandargs; " \
 174                "nand read ${loadaddr} 2a0000 400000; " \
 175                "bootm ${loadaddr}\0" \
 176
 177#define CONFIG_BOOTCOMMAND \
 178        "mmc dev ${mmcdev}; if mmc rescan; then " \
 179                "if run loadbootscript; then " \
 180                        "run bootscript; " \
 181                "else " \
 182                        "if run loaduimage; then " \
 183                                "run mmcboot; " \
 184                        "else run nandboot; " \
 185                        "fi; " \
 186                "fi; " \
 187        "else run nandboot; fi"
 188
 189/*
 190 * Miscellaneous configurable options
 191 */
 192#define CONFIG_AUTO_COMPLETE
 193#define CONFIG_CMDLINE_EDITING
 194#define CONFIG_TIMESTAMP
 195#define CONFIG_SYS_AUTOLOAD             "no"
 196#define CONFIG_SYS_LONGHELP             /* undef to save memory */
 197#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 198/* Print Buffer Size */
 199#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 200                                        sizeof(CONFIG_SYS_PROMPT) + 16)
 201#define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 202/* Boot Argument Buffer Size */
 203#define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 204
 205#define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)     /* memtest */
 206                                                                /* works on */
 207#define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 208                                        0x01F00000) /* 31MB */
 209
 210#define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 211                                                        /* load address */
 212
 213/*
 214 * OMAP3 has 12 GP timers, they can be driven by the system clock
 215 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 216 * This rate is divided by a local divisor.
 217 */
 218#define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 219#define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 220
 221/*-----------------------------------------------------------------------
 222 * Physical Memory Map
 223 */
 224#define CONFIG_NR_DRAM_BANKS    1       /* CS1 is never populated */
 225#define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 226
 227/*-----------------------------------------------------------------------
 228 * FLASH and environment organization
 229 */
 230
 231/* **** PISMO SUPPORT *** */
 232/* Monitor at start of flash */
 233#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 234#define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 235
 236#define CONFIG_ENV_IS_IN_NAND
 237#define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 238#define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 239#define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 240
 241#if defined(CONFIG_CMD_NET)
 242#define CONFIG_SMC911X
 243#define CONFIG_SMC911X_32_BIT
 244#define CM_T3X_SMC911X_BASE     0x2C000000
 245#define SB_T35_SMC911X_BASE     (CM_T3X_SMC911X_BASE + (16 << 20))
 246#define CONFIG_SMC911X_BASE     CM_T3X_SMC911X_BASE
 247#endif /* (CONFIG_CMD_NET) */
 248
 249/* additions for new relocation code, must be added to all boards */
 250#define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 251#define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 252#define CONFIG_SYS_INIT_RAM_SIZE        0x800
 253#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR +     \
 254                                         CONFIG_SYS_INIT_RAM_SIZE -     \
 255                                         GENERATED_GBL_DATA_SIZE)
 256
 257/* Status LED */
 258#define CONFIG_STATUS_LED               /* Status LED enabled */
 259#define CONFIG_BOARD_SPECIFIC_LED
 260#define CONFIG_GPIO_LED
 261#define GREEN_LED_GPIO                  186 /* CM-T35 Green LED is GPIO186 */
 262#define GREEN_LED_DEV                   0
 263#define STATUS_LED_BIT                  GREEN_LED_GPIO
 264#define STATUS_LED_STATE                STATUS_LED_ON
 265#define STATUS_LED_PERIOD               (CONFIG_SYS_HZ / 2)
 266#define STATUS_LED_BOOT                 GREEN_LED_DEV
 267
 268#define CONFIG_SPLASHIMAGE_GUARD
 269
 270/* GPIO banks */
 271#ifdef CONFIG_STATUS_LED
 272#define CONFIG_OMAP3_GPIO_6     /* GPIO186 is in GPIO bank 6  */
 273#endif
 274
 275/* Display Configuration */
 276#define CONFIG_OMAP3_GPIO_2
 277#define CONFIG_OMAP3_GPIO_5
 278#define CONFIG_VIDEO_OMAP3
 279#define LCD_BPP         LCD_COLOR16
 280
 281#define CONFIG_SPLASH_SCREEN
 282#define CONFIG_SPLASH_SOURCE
 283#define CONFIG_CMD_BMP
 284#define CONFIG_BMP_16BPP
 285#define CONFIG_SCF0403_LCD
 286
 287#define CONFIG_OMAP3_SPI
 288
 289/* Defines for SPL */
 290#define CONFIG_SPL_FRAMEWORK
 291#define CONFIG_SPL_NAND_SIMPLE
 292
 293#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 294#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 295
 296#define CONFIG_SPL_BOARD_INIT
 297#define CONFIG_SPL_NAND_BASE
 298#define CONFIG_SPL_NAND_DRIVERS
 299#define CONFIG_SPL_NAND_ECC
 300#define CONFIG_SPL_OMAP3_ID_NAND
 301#define CONFIG_SPL_LDSCRIPT             "arch/arm/mach-omap2/u-boot-spl.lds"
 302
 303/* NAND boot config */
 304#define CONFIG_SYS_NAND_5_ADDR_CYCLE
 305#define CONFIG_SYS_NAND_PAGE_COUNT      64
 306#define CONFIG_SYS_NAND_PAGE_SIZE       2048
 307#define CONFIG_SYS_NAND_OOBSIZE         64
 308#define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 309#define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 310/*
 311 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
 312 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
 313 */
 314#define CONFIG_SYS_NAND_ECCPOS          { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
 315                                         10, 11, 12 }
 316#define CONFIG_SYS_NAND_ECCSIZE         512
 317#define CONFIG_SYS_NAND_ECCBYTES        3
 318#define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 319
 320#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 321#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 322
 323#define CONFIG_SPL_TEXT_BASE            0x40200800
 324#define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 325                                         CONFIG_SPL_TEXT_BASE)
 326
 327/*
 328 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
 329 * older x-loader implementations. And move the BSS area so that it
 330 * doesn't overlap with TEXT_BASE.
 331 */
 332#define CONFIG_SYS_TEXT_BASE            0x80008000
 333#define CONFIG_SPL_BSS_START_ADDR       0x80100000
 334#define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 335
 336#define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 337#define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 338
 339/* EEPROM */
 340#define CONFIG_CMD_EEPROM
 341#define CONFIG_ENV_EEPROM_IS_ON_I2C
 342#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 343#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 344#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 345#define CONFIG_SYS_EEPROM_SIZE                  256
 346
 347#define CONFIG_CMD_EEPROM_LAYOUT
 348#define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3"
 349
 350#endif /* __CONFIG_H */
 351