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11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14
15
16
17#define CONFIG_LWMON5 1
18#define CONFIG_440EPX 1
19#define CONFIG_440 1
20
21#define CONFIG_SYS_TEXT_BASE 0xFFF80000
22#define CONFIG_HOSTNAME lwmon5
23
24#define CONFIG_SYS_CLK_FREQ 33300000
25
26#define CONFIG_4xx_DCACHE
27
28#define CONFIG_BOARD_EARLY_INIT_F
29#define CONFIG_BOARD_EARLY_INIT_R
30#define CONFIG_BOARD_POSTCLK_INIT
31#define CONFIG_MISC_INIT_R
32#define CONFIG_BOARD_RESET
33
34
35
36
37
38#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
39#define CONFIG_SYS_MONITOR_LEN 0x80000
40#define CONFIG_SYS_MALLOC_LEN (1 << 20)
41
42#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
43#define CONFIG_SYS_SDRAM_BASE 0x00000000
44#define CONFIG_SYS_FLASH_BASE 0xf8000000
45#define CONFIG_SYS_LIME_BASE_0 0xc0000000
46#define CONFIG_SYS_LIME_BASE_1 0xc1000000
47#define CONFIG_SYS_LIME_BASE_2 0xc2000000
48#define CONFIG_SYS_LIME_BASE_3 0xc3000000
49#define CONFIG_SYS_FPGA_BASE_0 0xc4000000
50#define CONFIG_SYS_FPGA_BASE_1 0xc4200000
51#define CONFIG_SYS_OCM_BASE 0xe0010000
52#define CONFIG_SYS_PCI_BASE 0xe0000000
53#define CONFIG_SYS_PCI_MEMBASE 0x80000000
54#define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
55#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
56#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
57
58#define CONFIG_SYS_USB2D0_BASE 0xe0000100
59#define CONFIG_SYS_USB_DEVICE 0xe0000000
60#define CONFIG_SYS_USB_HOST 0xe0000400
61
62
63
64
65
66
67
68
69
70#define CONFIG_SYS_INIT_RAM_DCACHE 1
71#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000
72#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
73#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
74 GENERATED_GBL_DATA_SIZE)
75#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
76
77
78#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
79#define CONFIG_SYS_OCM_SIZE (16 << 10)
80
81#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
82
83
84#define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
85#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
86#define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
87#define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
88#define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000
89#define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000
90#define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001
91#define CONFIG_SYS_OCM_STATUS_OK 0x00009A00
92#define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
93#define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
94
95
96
97
98#define CONFIG_CONS_INDEX 2
99#define CONFIG_SYS_NS16550_SERIAL
100#define CONFIG_SYS_NS16550_REG_SIZE 1
101#define CONFIG_SYS_NS16550_CLK get_serial_clock()
102#undef CONFIG_SYS_EXT_SERIAL_CLOCK
103#define CONFIG_BAUDRATE 115200
104
105#define CONFIG_SYS_BAUDRATE_TABLE \
106 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
107
108
109
110
111#define CONFIG_ENV_IS_IN_FLASH
112
113
114
115
116#define CONFIG_SYS_FLASH_CFI
117#define CONFIG_FLASH_CFI_DRIVER
118
119#define CONFIG_SYS_FLASH0 0xFC000000
120#define CONFIG_SYS_FLASH1 0xF8000000
121#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
122
123#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
124#define CONFIG_SYS_MAX_FLASH_SECT 512
125
126#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
127#define CONFIG_SYS_FLASH_WRITE_TOUT 500
128
129#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
130#define CONFIG_SYS_FLASH_PROTECTION
131
132#define CONFIG_SYS_FLASH_EMPTY_INFO
133#define CONFIG_SYS_FLASH_QUIET_TEST
134
135#define CONFIG_ENV_SECT_SIZE 0x40000
136#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
137#define CONFIG_ENV_SIZE 0x2000
138
139
140#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
141#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
142
143
144
145
146#define CONFIG_SYS_MBYTES_SDRAM 256
147#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000
148#define CONFIG_DDR_DATA_EYE
149#define CONFIG_DDR_ECC
150
151
152#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
153 CONFIG_SYS_POST_CPU | \
154 CONFIG_SYS_POST_ECC | \
155 CONFIG_SYS_POST_ETHER | \
156 CONFIG_SYS_POST_FPU | \
157 CONFIG_SYS_POST_I2C | \
158 CONFIG_SYS_POST_MEMORY | \
159 CONFIG_SYS_POST_OCM | \
160 CONFIG_SYS_POST_RTC | \
161 CONFIG_SYS_POST_SPR | \
162 CONFIG_SYS_POST_UART | \
163 CONFIG_SYS_POST_SYSMON | \
164 CONFIG_SYS_POST_WATCHDOG | \
165 CONFIG_SYS_POST_DSP | \
166 CONFIG_SYS_POST_BSPEC1 | \
167 CONFIG_SYS_POST_BSPEC2 | \
168 CONFIG_SYS_POST_BSPEC3 | \
169 CONFIG_SYS_POST_BSPEC4 | \
170 CONFIG_SYS_POST_BSPEC5)
171
172
173#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
174 CONFIG_SYS_NS16550_COM2 }
175
176#define CONFIG_POST_UART { \
177 "UART test", \
178 "uart", \
179 "This test verifies the UART operation.", \
180 POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \
181 &uart_post_test, \
182 NULL, \
183 NULL, \
184 CONFIG_SYS_POST_UART \
185 }
186
187#define CONFIG_POST_WATCHDOG { \
188 "Watchdog timer test", \
189 "watchdog", \
190 "This test checks the watchdog timer.", \
191 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
192 &lwmon5_watchdog_post_test, \
193 NULL, \
194 NULL, \
195 CONFIG_SYS_POST_WATCHDOG \
196 }
197
198#define CONFIG_POST_BSPEC1 { \
199 "dsPIC init test", \
200 "dspic_init", \
201 "This test returns result of dsPIC READY test run earlier.", \
202 POST_RAM | POST_ALWAYS, \
203 &dspic_init_post_test, \
204 NULL, \
205 NULL, \
206 CONFIG_SYS_POST_BSPEC1 \
207 }
208
209#define CONFIG_POST_BSPEC2 { \
210 "dsPIC test", \
211 "dspic", \
212 "This test gets result of dsPIC POST and dsPIC version.", \
213 POST_RAM | POST_ALWAYS, \
214 &dspic_post_test, \
215 NULL, \
216 NULL, \
217 CONFIG_SYS_POST_BSPEC2 \
218 }
219
220#define CONFIG_POST_BSPEC3 { \
221 "FPGA test", \
222 "fpga", \
223 "This test checks FPGA registers and memory.", \
224 POST_RAM | POST_ALWAYS | POST_MANUAL, \
225 &fpga_post_test, \
226 NULL, \
227 NULL, \
228 CONFIG_SYS_POST_BSPEC3 \
229 }
230
231#define CONFIG_POST_BSPEC4 { \
232 "GDC test", \
233 "gdc", \
234 "This test checks GDC registers and memory.", \
235 POST_RAM | POST_ALWAYS | POST_MANUAL,\
236 &gdc_post_test, \
237 NULL, \
238 NULL, \
239 CONFIG_SYS_POST_BSPEC4 \
240 }
241
242#define CONFIG_POST_BSPEC5 { \
243 "SYSMON1 test", \
244 "sysmon1", \
245 "This test checks GPIO_62_EPX pin indicating power failure.", \
246 POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
247 &sysmon1_post_test, \
248 NULL, \
249 NULL, \
250 CONFIG_SYS_POST_BSPEC5 \
251 }
252
253#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000
254#define CONFIG_LOGBUFFER
255
256#define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
257#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
258
259
260
261
262#define CONFIG_SYS_I2C
263#define CONFIG_SYS_I2C_PPC4XX
264#define CONFIG_SYS_I2C_PPC4XX_CH0
265#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
266#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
267
268#define CONFIG_SYS_I2C_RTC_ADDR 0x51
269#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52
270#define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53
271#define CONFIG_SYS_I2C_DSPIC_ADDR 0x54
272#define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55
273#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56
274#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57
275
276#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
277#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
278
279
280#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
281#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
282
283#define CONFIG_RTC_PCF8563
284#define CONFIG_SYS_I2C_RTC_ADDR 0x51
285#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56
286#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57
287
288#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \
289 CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
290 CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
291 CONFIG_SYS_I2C_DSPIC_ADDR, \
292 CONFIG_SYS_I2C_DSPIC_2_ADDR, \
293 CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
294 CONFIG_SYS_I2C_DSPIC_IO_ADDR }
295
296
297#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
298
299#define CONFIG_POST_KEY_MAGIC "3C+3E"
300
301#define CONFIG_PREBOOT "setenv bootdelay 15"
302
303#undef CONFIG_BOOTARGS
304
305#define CONFIG_EXTRA_ENV_SETTINGS \
306 "hostname=lwmon5\0" \
307 "netdev=eth0\0" \
308 "unlock=yes\0" \
309 "logversion=2\0" \
310 "nfsargs=setenv bootargs root=/dev/nfs rw " \
311 "nfsroot=${serverip}:${rootpath}\0" \
312 "ramargs=setenv bootargs root=/dev/ram rw\0" \
313 "addip=setenv bootargs ${bootargs} " \
314 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
315 ":${hostname}:${netdev}:off panic=1\0" \
316 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
317 "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
318 "flash_nfs=run nfsargs addip addtty addmisc;" \
319 "bootm ${kernel_addr}\0" \
320 "flash_self=run ramargs addip addtty addmisc;" \
321 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
322 "net_nfs=tftp 200000 ${bootfile};" \
323 "run nfsargs addip addtty addmisc;bootm\0" \
324 "rootpath=/opt/eldk/ppc_4xxFP\0" \
325 "bootfile=/tftpboot/lwmon5/uImage\0" \
326 "kernel_addr=FC000000\0" \
327 "ramdisk_addr=FC180000\0" \
328 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
329 "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
330 "cp.b 200000 FFF80000 80000\0" \
331 "upd=run load update\0" \
332 "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
333 "autoscr 200000\0" \
334 ""
335#define CONFIG_BOOTCOMMAND "run flash_self"
336
337
338#define CONFIG_LOADS_ECHO 1
339#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
340
341#define CONFIG_PPC4xx_EMAC
342#define CONFIG_IBM_EMAC4_V4 1
343#define CONFIG_MII 1
344#define CONFIG_PHY_ADDR 3
345
346#define CONFIG_PHY_RESET 1
347#define CONFIG_PHY_RESET_DELAY 300
348
349#define CONFIG_HAS_ETH0
350#define CONFIG_SYS_RX_ETH_BUFFER 32
351
352#define CONFIG_HAS_ETH1 1
353#define CONFIG_PHY1_ADDR 1
354
355
356#define CONFIG_VIDEO_MB862xx
357#define CONFIG_VIDEO_MB862xx_ACCEL
358#define CONFIG_VIDEO_LOGO
359#define VIDEO_FB_16BPP_PIXEL_SWAP
360#define VIDEO_FB_16BPP_WORD_SWAP
361
362#define CONFIG_SPLASH_SCREEN
363
364
365
366
367#define CONFIG_USB_EHCI
368#define CONFIG_USB_EHCI_PPC4XX
369#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
370#define CONFIG_EHCI_MMIO_BIG_ENDIAN
371#define CONFIG_EHCI_DESC_BIG_ENDIAN
372#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
373
374
375#define CONFIG_MAC_PARTITION
376#define CONFIG_DOS_PARTITION
377#define CONFIG_ISO_PARTITION
378
379
380
381
382#define CONFIG_BOOTP_BOOTFILESIZE
383#define CONFIG_BOOTP_BOOTPATH
384#define CONFIG_BOOTP_GATEWAY
385#define CONFIG_BOOTP_HOSTNAME
386
387
388
389
390#define CONFIG_CMD_DATE
391#define CONFIG_CMD_DIAG
392#define CONFIG_CMD_EEPROM
393#define CONFIG_CMD_IRQ
394#define CONFIG_CMD_REGINFO
395#define CONFIG_CMD_SDRAM
396
397#ifdef CONFIG_VIDEO
398#define CONFIG_CMD_BMP
399#endif
400
401#ifdef CONFIG_440EPX
402#endif
403
404
405
406
407#define CONFIG_SUPPORT_VFAT
408
409#define CONFIG_SYS_LONGHELP
410
411#if defined(CONFIG_CMD_KGDB)
412#define CONFIG_SYS_CBSIZE 1024
413#else
414#define CONFIG_SYS_CBSIZE 256
415#endif
416#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
417#define CONFIG_SYS_MAXARGS 16
418#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
419
420#define CONFIG_SYS_MEMTEST_START 0x0400000
421#define CONFIG_SYS_MEMTEST_END 0x0C00000
422
423#define CONFIG_SYS_LOAD_ADDR 0x100000
424#define CONFIG_SYS_EXTBDINFO 1
425
426#define CONFIG_CMDLINE_EDITING 1
427#define CONFIG_MX_CYCLIC 1
428
429#ifndef DEBUG
430#define CONFIG_HW_WATCHDOG 1
431#endif
432#define CONFIG_WD_PERIOD 40000
433#define CONFIG_WD_MAX_RATE 66600
434
435
436
437
438
439
440#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
441#define CONFIG_SYS_BOOTM_LEN (16 << 20)
442
443
444
445
446#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
447
448
449#define CONFIG_SYS_EBC_PB0AP 0x03000280
450#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
451
452
453#define CONFIG_SYS_EBC_PB1AP 0x01004380
454#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
455
456
457#define CONFIG_SYS_EBC_PB2AP 0x01004400
458#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
459
460
461#define CONFIG_SYS_EBC_PB3AP 0x01004400
462#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
463
464#define CONFIG_SYS_EBC_CFG 0xb8400000
465
466
467
468
469
470#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
471#if 1
472
473#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
474#else
475
476#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
477#endif
478
479
480#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
481
482
483
484
485
486
487#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
488#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
489#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
490#else
491#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
492#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
493#endif
494
495
496
497
498#define CONFIG_SYS_GPIO_PHY1_RST 12
499#define CONFIG_SYS_GPIO_FLASH_WP 14
500#define CONFIG_SYS_GPIO_PHY0_RST 22
501#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49
502#define CONFIG_SYS_GPIO_DSPIC_READY 51
503#define CONFIG_SYS_GPIO_CAN_ENABLE 53
504#define CONFIG_SYS_GPIO_LSB_ENABLE 54
505#define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
506#define CONFIG_SYS_GPIO_HIGHSIDE 56
507#define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
508#define CONFIG_SYS_GPIO_BOARD_RESET 58
509#define CONFIG_SYS_GPIO_LIME_S 59
510#define CONFIG_SYS_GPIO_LIME_RST 60
511#define CONFIG_SYS_GPIO_SYSMON_STATUS 62
512#define CONFIG_SYS_GPIO_WATCHDOG 63
513
514#define GPIO49_VAL 1
515
516
517
518
519#define CONFIG_SYS_4xx_GPIO_TABLE { \
520{ \
521 \
522{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
523{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
524{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
525{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
526{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
527{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
528{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
529{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
530{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
531{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
532{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
533{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
534{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
535{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
536{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
537{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
538{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
539{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
540{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
541{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
542{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
543{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
544{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
545{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
546{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
547{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
548{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
549{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
550{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
551{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
552{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
553{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
554}, \
555{ \
556 \
557{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, \
558{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, \
559{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, \
560{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, \
561{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, \
562{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, \
563{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, \
564{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, \
565{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
566{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
567{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
568{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
569{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
570{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
571{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
572{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
573{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
574{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, \
575{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, \
576{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
577{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
578{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
579{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
580{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
581{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
582{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
583{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
584{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
585{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
586{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
587{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
588{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
589} \
590}
591
592#if defined(CONFIG_CMD_KGDB)
593#define CONFIG_KGDB_BAUDRATE 230400
594#endif
595
596#endif
597