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18#ifndef __CONFIG_H
19#define __CONFIG_H
20
21
22
23
24#ifdef CONFIG_CADDY2
25#define VME_CADDY2
26#endif
27
28
29
30
31#define CONFIG_E300 1
32#define CONFIG_MPC834x 1
33#define CONFIG_MPC8349 1
34#define CONFIG_VME8349 1
35
36#define CONFIG_SYS_TEXT_BASE 0xFFF00000
37
38#define CONFIG_MISC_INIT_R
39
40
41#undef CONFIG_MPC83XX_PCI2
42
43#define CONFIG_PCI_66M
44#ifdef CONFIG_PCI_66M
45#define CONFIG_83XX_CLKIN 66000000
46#else
47#define CONFIG_83XX_CLKIN 33000000
48#endif
49
50#ifndef CONFIG_SYS_CLK_FREQ
51#ifdef CONFIG_PCI_66M
52#define CONFIG_SYS_CLK_FREQ 66000000
53#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
54#else
55#define CONFIG_SYS_CLK_FREQ 33000000
56#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
57#endif
58#endif
59
60#define CONFIG_SYS_IMMR 0xE0000000
61
62#undef CONFIG_SYS_DRAM_TEST
63#define CONFIG_SYS_MEMTEST_START 0x00000000
64#define CONFIG_SYS_MEMTEST_END 0x00100000
65
66
67
68
69#define CONFIG_DDR_ECC
70#define CONFIG_DDR_ECC_CMD
71#define CONFIG_SPD_EEPROM
72#define SPD_EEPROM_ADDRESS 0x54
73#define CONFIG_SYS_READ_SPD vme8349_read_spd
74#define CONFIG_SYS_83XX_DDR_USES_CS0
75
76
77
78
79
80
81
82
83
84
85
86#undef CONFIG_DDR_32BIT
87
88#define CONFIG_SYS_DDR_BASE 0x00000000
89#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
90#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
91#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
92 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
93#define CONFIG_DDR_2T_TIMING
94#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
95 | DDRCDR_ODT \
96 | DDRCDR_Q_DRN)
97
98
99
100
101
102#define CONFIG_SYS_FLASH_CFI
103#define CONFIG_FLASH_CFI_DRIVER
104#ifdef VME_CADDY2
105#define CONFIG_SYS_FLASH_BASE 0xffc00000
106#define CONFIG_SYS_FLASH_SIZE 4
107#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
108 BR_PS_16 | \
109 BR_MS_GPCM | \
110 BR_V)
111
112#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
113 | OR_GPCM_XAM \
114 | OR_GPCM_CSNT \
115 | OR_GPCM_ACS_DIV2 \
116 | OR_GPCM_XACS \
117 | OR_GPCM_SCY_15 \
118 | OR_GPCM_TRLX_SET \
119 | OR_GPCM_EHTR_SET \
120 | OR_GPCM_EAD)
121
122#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
123#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
124#else
125#define CONFIG_SYS_FLASH_BASE 0xf8000000
126#define CONFIG_SYS_FLASH_SIZE 128
127#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
128 BR_PS_16 | \
129 BR_MS_GPCM | \
130 BR_V)
131
132#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
133 | OR_GPCM_XAM \
134 | OR_GPCM_CSNT \
135 | OR_GPCM_ACS_DIV2 \
136 | OR_GPCM_XACS \
137 | OR_GPCM_SCY_15 \
138 | OR_GPCM_TRLX_SET \
139 | OR_GPCM_EHTR_SET \
140 | OR_GPCM_EAD)
141
142#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
143#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
144#endif
145
146
147#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
148#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
149 | BR_PS_32 \
150 | BR_MS_GPCM \
151 | BR_V)
152
153#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
154 | OR_GPCM_SETA)
155
156#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
157#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
158
159#define CONFIG_SYS_MAX_FLASH_BANKS 1
160#define CONFIG_SYS_MAX_FLASH_SECT 1024
161
162#undef CONFIG_SYS_FLASH_CHECKSUM
163#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
164#define CONFIG_SYS_FLASH_WRITE_TOUT 500
165
166#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
167
168#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
169#define CONFIG_SYS_RAMBOOT
170#else
171#undef CONFIG_SYS_RAMBOOT
172#endif
173
174#define CONFIG_SYS_INIT_RAM_LOCK 1
175#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000
176#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
177
178#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
179 GENERATED_GBL_DATA_SIZE)
180#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
181
182#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
183#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
184
185
186
187
188
189
190
191#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
192#define CONFIG_SYS_LBC_LBCR 0x00000000
193
194#undef CONFIG_SYS_LB_SDRAM
195
196
197
198
199#define CONFIG_CONS_INDEX 1
200#define CONFIG_SYS_NS16550_SERIAL
201#define CONFIG_SYS_NS16550_REG_SIZE 1
202#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
203
204#define CONFIG_SYS_BAUDRATE_TABLE \
205 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
206
207#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
208#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
209
210#define CONFIG_CMDLINE_EDITING
211#define CONFIG_AUTO_COMPLETE
212
213
214#define CONFIG_SYS_I2C
215#define CONFIG_SYS_I2C_FSL
216#define CONFIG_SYS_FSL_I2C_SPEED 400000
217#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
218#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
219#define CONFIG_SYS_FSL_I2C2_SPEED 400000
220#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
221#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
222#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
223
224
225#define CONFIG_SYS_I2C_8574_ADDR2 0x20
226
227
228#define CONFIG_SYS_TSEC1_OFFSET 0x24000
229#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
230#define CONFIG_SYS_TSEC2_OFFSET 0x25000
231#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
232
233
234
235
236
237#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
238#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
239#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
240#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
241#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
242#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
243#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
244#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
245#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
246
247#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
248#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
249#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000
250#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
251#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
252#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000
253#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
254#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
255#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000
256
257#if defined(CONFIG_PCI)
258
259#define PCI_64BIT
260#define PCI_ONE_PCI1
261#if defined(PCI_64BIT)
262#undef PCI_ALL_PCI1
263#undef PCI_TWO_PCI1
264#undef PCI_ONE_PCI1
265#endif
266
267#ifndef VME_CADDY2
268#endif
269
270#undef CONFIG_EEPRO100
271#undef CONFIG_TULIP
272
273#if !defined(CONFIG_PCI_PNP)
274 #define PCI_ENET0_IOADDR 0xFIXME
275 #define PCI_ENET0_MEMADDR 0xFIXME
276 #define PCI_IDSEL_NUMBER 0xFIXME
277#endif
278
279#define CONFIG_PCI_SCAN_SHOW
280#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
281
282#endif
283
284
285
286
287#ifdef VME_CADDY2
288#else
289#define CONFIG_TSEC_ENET
290#endif
291
292#if defined(CONFIG_TSEC_ENET)
293
294#define CONFIG_GMII
295#define CONFIG_TSEC1
296#define CONFIG_TSEC1_NAME "TSEC0"
297#define CONFIG_TSEC2
298#define CONFIG_TSEC2_NAME "TSEC1"
299#define CONFIG_PHY_M88E1111
300#define TSEC1_PHY_ADDR 0x08
301#define TSEC2_PHY_ADDR 0x10
302#define TSEC1_PHYIDX 0
303#define TSEC2_PHYIDX 0
304#define TSEC1_FLAGS TSEC_GIGABIT
305#define TSEC2_FLAGS TSEC_GIGABIT
306
307
308#define CONFIG_ETHPRIME "TSEC0"
309
310#endif
311
312
313
314
315#ifndef CONFIG_SYS_RAMBOOT
316 #define CONFIG_ENV_IS_IN_FLASH
317 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
318 #define CONFIG_ENV_SECT_SIZE 0x20000
319 #define CONFIG_ENV_SIZE 0x2000
320
321
322#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
323#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
324
325#else
326 #define CONFIG_SYS_NO_FLASH
327 #define CONFIG_ENV_IS_NOWHERE
328 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
329 #define CONFIG_ENV_SIZE 0x2000
330#endif
331
332#define CONFIG_LOADS_ECHO
333#define CONFIG_SYS_LOADS_BAUD_CHANGE
334
335
336
337
338#define CONFIG_BOOTP_BOOTFILESIZE
339#define CONFIG_BOOTP_BOOTPATH
340#define CONFIG_BOOTP_GATEWAY
341#define CONFIG_BOOTP_HOSTNAME
342
343
344
345
346#define CONFIG_CMD_DATE
347#define CONFIG_SYS_RTC_BUS_NUM 0x01
348#define CONFIG_SYS_I2C_RTC_ADDR 0x32
349#define CONFIG_RTC_RX8025
350#define CONFIG_CMD_TSI148
351
352#if defined(CONFIG_PCI)
353 #define CONFIG_CMD_PCI
354#endif
355
356#if defined(CONFIG_SYS_RAMBOOT)
357 #undef CONFIG_CMD_ENV
358#endif
359
360
361#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
362
363#undef CONFIG_WATCHDOG
364
365
366
367
368#define CONFIG_SYS_LONGHELP
369#define CONFIG_SYS_LOAD_ADDR 0x2000000
370
371#if defined(CONFIG_CMD_KGDB)
372 #define CONFIG_SYS_CBSIZE 1024
373#else
374 #define CONFIG_SYS_CBSIZE 256
375#endif
376
377#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
378#define CONFIG_SYS_MAXARGS 16
379#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
380
381
382
383
384
385
386#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
387
388#define CONFIG_SYS_RCWH_PCIHOST 0x80000000
389
390#define CONFIG_SYS_HRCW_LOW (\
391 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
392 HRCWL_DDR_TO_SCB_CLK_1X1 |\
393 HRCWL_CSB_TO_CLKIN |\
394 HRCWL_VCO_1X2 |\
395 HRCWL_CORE_TO_CSB_2X1)
396
397#if defined(PCI_64BIT)
398#define CONFIG_SYS_HRCW_HIGH (\
399 HRCWH_PCI_HOST |\
400 HRCWH_64_BIT_PCI |\
401 HRCWH_PCI1_ARBITER_ENABLE |\
402 HRCWH_PCI2_ARBITER_DISABLE |\
403 HRCWH_CORE_ENABLE |\
404 HRCWH_FROM_0X00000100 |\
405 HRCWH_BOOTSEQ_DISABLE |\
406 HRCWH_SW_WATCHDOG_DISABLE |\
407 HRCWH_ROM_LOC_LOCAL_16BIT |\
408 HRCWH_TSEC1M_IN_GMII |\
409 HRCWH_TSEC2M_IN_GMII)
410#else
411#define CONFIG_SYS_HRCW_HIGH (\
412 HRCWH_PCI_HOST |\
413 HRCWH_32_BIT_PCI |\
414 HRCWH_PCI1_ARBITER_ENABLE |\
415 HRCWH_PCI2_ARBITER_ENABLE |\
416 HRCWH_CORE_ENABLE |\
417 HRCWH_FROM_0X00000100 |\
418 HRCWH_BOOTSEQ_DISABLE |\
419 HRCWH_SW_WATCHDOG_DISABLE |\
420 HRCWH_ROM_LOC_LOCAL_16BIT |\
421 HRCWH_TSEC1M_IN_GMII |\
422 HRCWH_TSEC2M_IN_GMII)
423#endif
424
425
426#define CONFIG_SYS_SICRH 0
427#define CONFIG_SYS_SICRL SICRL_LDP_A
428
429#define CONFIG_SYS_HID0_INIT 0x000000000
430#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
431 HID0_ENABLE_INSTRUCTION_CACHE)
432
433#define CONFIG_SYS_HID2 HID2_HBE
434
435#define CONFIG_SYS_GPIO1_PRELIM
436#define CONFIG_SYS_GPIO1_DIR 0x00100000
437#define CONFIG_SYS_GPIO1_DAT 0x00100000
438
439#define CONFIG_SYS_GPIO2_PRELIM
440#define CONFIG_SYS_GPIO2_DIR 0x78900000
441#define CONFIG_SYS_GPIO2_DAT 0x70100000
442
443#define CONFIG_HIGH_BATS
444
445
446#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
447 BATL_MEMCOHERENCE)
448#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
449 BATU_VS | BATU_VP)
450
451
452#ifdef CONFIG_PCI
453#define CONFIG_PCI_INDIRECT_BRIDGE
454#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
455 BATL_MEMCOHERENCE)
456#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
457 BATU_VS | BATU_VP)
458#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
459 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
460#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
461 BATU_VS | BATU_VP)
462#else
463#define CONFIG_SYS_IBAT1L (0)
464#define CONFIG_SYS_IBAT1U (0)
465#define CONFIG_SYS_IBAT2L (0)
466#define CONFIG_SYS_IBAT2U (0)
467#endif
468
469#ifdef CONFIG_MPC83XX_PCI2
470#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
471 BATL_MEMCOHERENCE)
472#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
473 BATU_VS | BATU_VP)
474#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
475 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
476#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
477 BATU_VS | BATU_VP)
478#else
479#define CONFIG_SYS_IBAT3L (0)
480#define CONFIG_SYS_IBAT3U (0)
481#define CONFIG_SYS_IBAT4L (0)
482#define CONFIG_SYS_IBAT4U (0)
483#endif
484
485
486#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
487 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
488#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
489 BATU_VS | BATU_VP)
490
491#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
492#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
493
494#if (CONFIG_SYS_DDR_SIZE == 512)
495#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
496 BATL_PP_RW | BATL_MEMCOHERENCE)
497#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
498 BATU_BL_256M | BATU_VS | BATU_VP)
499#else
500#define CONFIG_SYS_IBAT7L (0)
501#define CONFIG_SYS_IBAT7U (0)
502#endif
503
504#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
505#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
506#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
507#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
508#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
509#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
510#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
511#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
512#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
513#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
514#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
515#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
516#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
517#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
518#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
519#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
520
521#if defined(CONFIG_CMD_KGDB)
522#define CONFIG_KGDB_BAUDRATE 230400
523#endif
524
525
526
527
528#define CONFIG_ENV_OVERWRITE
529
530#if defined(CONFIG_TSEC_ENET)
531#define CONFIG_HAS_ETH0
532#define CONFIG_HAS_ETH1
533#endif
534
535#define CONFIG_HOSTNAME VME8349
536#define CONFIG_ROOTPATH "/tftpboot/rootfs"
537#define CONFIG_BOOTFILE "uImage"
538
539#define CONFIG_LOADADDR 800000
540
541#undef CONFIG_BOOTARGS
542
543#define CONFIG_BAUDRATE 9600
544
545#define CONFIG_EXTRA_ENV_SETTINGS \
546 "netdev=eth0\0" \
547 "hostname=vme8349\0" \
548 "nfsargs=setenv bootargs root=/dev/nfs rw " \
549 "nfsroot=${serverip}:${rootpath}\0" \
550 "ramargs=setenv bootargs root=/dev/ram rw\0" \
551 "addip=setenv bootargs ${bootargs} " \
552 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
553 ":${hostname}:${netdev}:off panic=1\0" \
554 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
555 "flash_nfs=run nfsargs addip addtty;" \
556 "bootm ${kernel_addr}\0" \
557 "flash_self=run ramargs addip addtty;" \
558 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
559 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
560 "bootm\0" \
561 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
562 "update=protect off fff00000 fff3ffff; " \
563 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
564 "upd=run load update\0" \
565 "fdtaddr=780000\0" \
566 "fdtfile=vme8349.dtb\0" \
567 ""
568
569#define CONFIG_NFSBOOTCOMMAND \
570 "setenv bootargs root=/dev/nfs rw " \
571 "nfsroot=$serverip:$rootpath " \
572 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
573 "$netdev:off " \
574 "console=$consoledev,$baudrate $othbootargs;" \
575 "tftp $loadaddr $bootfile;" \
576 "tftp $fdtaddr $fdtfile;" \
577 "bootm $loadaddr - $fdtaddr"
578
579#define CONFIG_RAMBOOTCOMMAND \
580 "setenv bootargs root=/dev/ram rw " \
581 "console=$consoledev,$baudrate $othbootargs;" \
582 "tftp $ramdiskaddr $ramdiskfile;" \
583 "tftp $loadaddr $bootfile;" \
584 "tftp $fdtaddr $fdtfile;" \
585 "bootm $loadaddr $ramdiskaddr $fdtaddr"
586
587#define CONFIG_BOOTCOMMAND "run flash_self"
588
589#ifndef __ASSEMBLY__
590int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
591 unsigned char *buffer, int len);
592#endif
593
594#endif
595