1/* 2 * Cirrus Logic EP93xx register definitions. 3 * 4 * Copyright (C) 2013 5 * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru> 6 * 7 * Copyright (C) 2009 8 * Matthias Kaehlcke <matthias@kaehlcke.net> 9 * 10 * Copyright (C) 2006 11 * Dominic Rath <Dominic.Rath@gmx.de> 12 * 13 * Copyright (C) 2004, 2005 14 * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com> 15 * 16 * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is 17 * 18 * Copyright (C) 2004 Ray Lehtiniemi 19 * Copyright (C) 2003 Cirrus Logic, Inc 20 * Copyright (C) 1999 ARM Limited. 21 * 22 * SPDX-License-Identifier: GPL-2.0+ 23 */ 24 25#define EP93XX_AHB_BASE 0x80000000 26#define EP93XX_APB_BASE 0x80800000 27 28/* 29 * 0x80000000 - 0x8000FFFF: DMA 30 */ 31#define DMA_OFFSET 0x000000 32#define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET) 33 34#ifndef __ASSEMBLY__ 35struct dma_channel { 36 uint32_t control; 37 uint32_t interrupt; 38 uint32_t ppalloc; 39 uint32_t status; 40 uint32_t reserved0; 41 uint32_t remain; 42 uint32_t reserved1[2]; 43 uint32_t maxcnt0; 44 uint32_t base0; 45 uint32_t current0; 46 uint32_t reserved2; 47 uint32_t maxcnt1; 48 uint32_t base1; 49 uint32_t current1; 50 uint32_t reserved3; 51}; 52 53struct dma_regs { 54 struct dma_channel m2p_channel_0; 55 struct dma_channel m2p_channel_1; 56 struct dma_channel m2p_channel_2; 57 struct dma_channel m2p_channel_3; 58 struct dma_channel m2m_channel_0; 59 struct dma_channel m2m_channel_1; 60 struct dma_channel reserved0[2]; 61 struct dma_channel m2p_channel_5; 62 struct dma_channel m2p_channel_4; 63 struct dma_channel m2p_channel_7; 64 struct dma_channel m2p_channel_6; 65 struct dma_channel m2p_channel_9; 66 struct dma_channel m2p_channel_8; 67 uint32_t channel_arbitration; 68 uint32_t reserved[15]; 69 uint32_t global_interrupt; 70}; 71#endif 72 73/* 74 * 0x80010000 - 0x8001FFFF: Ethernet MAC 75 */ 76#define MAC_OFFSET 0x010000 77#define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET) 78 79#ifndef __ASSEMBLY__ 80struct mac_queue { 81 uint32_t badd; 82 union { /* deal with half-word aligned registers */ 83 uint32_t blen; 84 union { 85 uint16_t filler; 86 uint16_t curlen; 87 }; 88 }; 89 uint32_t curadd; 90}; 91 92struct mac_regs { 93 uint32_t rxctl; 94 uint32_t txctl; 95 uint32_t testctl; 96 uint32_t reserved0; 97 uint32_t miicmd; 98 uint32_t miidata; 99 uint32_t miists; 100 uint32_t reserved1; 101 uint32_t selfctl; 102 uint32_t inten; 103 uint32_t intstsp; 104 uint32_t intstsc; 105 uint32_t reserved2[2]; 106 uint32_t diagad; 107 uint32_t diagdata; 108 uint32_t gt; 109 uint32_t fct; 110 uint32_t fcf; 111 uint32_t afp; 112 union { 113 struct { 114 uint32_t indad; 115 uint32_t indad_upper; 116 }; 117 uint32_t hashtbl; 118 }; 119 uint32_t reserved3[2]; 120 uint32_t giintsts; 121 uint32_t giintmsk; 122 uint32_t giintrosts; 123 uint32_t giintfrc; 124 uint32_t txcollcnt; 125 uint32_t rxmissnct; 126 uint32_t rxruntcnt; 127 uint32_t reserved4; 128 uint32_t bmctl; 129 uint32_t bmsts; 130 uint32_t rxbca; 131 uint32_t reserved5; 132 struct mac_queue rxdq; 133 uint32_t rxdqenq; 134 struct mac_queue rxstsq; 135 uint32_t rxstsqenq; 136 struct mac_queue txdq; 137 uint32_t txdqenq; 138 struct mac_queue txstsq; 139 uint32_t reserved6; 140 uint32_t rxbufthrshld; 141 uint32_t txbufthrshld; 142 uint32_t rxststhrshld; 143 uint32_t txststhrshld; 144 uint32_t rxdthrshld; 145 uint32_t txdthrshld; 146 uint32_t maxfrmlen; 147 uint32_t maxhdrlen; 148}; 149#endif 150 151#define SELFCTL_RWP (1 << 7) 152#define SELFCTL_GPO0 (1 << 5) 153#define SELFCTL_PUWE (1 << 4) 154#define SELFCTL_PDWE (1 << 3) 155#define SELFCTL_MIIL (1 << 2) 156#define SELFCTL_RESET (1 << 0) 157 158#define INTSTS_RWI (1 << 30) 159#define INTSTS_RXMI (1 << 29) 160#define INTSTS_RXBI (1 << 28) 161#define INTSTS_RXSQI (1 << 27) 162#define INTSTS_TXLEI (1 << 26) 163#define INTSTS_ECIE (1 << 25) 164#define INTSTS_TXUHI (1 << 24) 165#define INTSTS_MOI (1 << 18) 166#define INTSTS_TXCOI (1 << 17) 167#define INTSTS_RXROI (1 << 16) 168#define INTSTS_MIII (1 << 12) 169#define INTSTS_PHYI (1 << 11) 170#define INTSTS_TI (1 << 10) 171#define INTSTS_AHBE (1 << 8) 172#define INTSTS_OTHER (1 << 4) 173#define INTSTS_TXSQ (1 << 3) 174#define INTSTS_RXSQ (1 << 2) 175 176#define BMCTL_MT (1 << 13) 177#define BMCTL_TT (1 << 12) 178#define BMCTL_UNH (1 << 11) 179#define BMCTL_TXCHR (1 << 10) 180#define BMCTL_TXDIS (1 << 9) 181#define BMCTL_TXEN (1 << 8) 182#define BMCTL_EH2 (1 << 6) 183#define BMCTL_EH1 (1 << 5) 184#define BMCTL_EEOB (1 << 4) 185#define BMCTL_RXCHR (1 << 2) 186#define BMCTL_RXDIS (1 << 1) 187#define BMCTL_RXEN (1 << 0) 188 189#define BMSTS_TXACT (1 << 7) 190#define BMSTS_TP (1 << 4) 191#define BMSTS_RXACT (1 << 3) 192#define BMSTS_QID_MASK 0x07 193#define BMSTS_QID_RXDATA 0x00 194#define BMSTS_QID_TXDATA 0x01 195#define BMSTS_QID_RXSTS 0x02 196#define BMSTS_QID_TXSTS 0x03 197#define BMSTS_QID_RXDESC 0x04 198#define BMSTS_QID_TXDESC 0x05 199 200#define AFP_MASK 0x07 201#define AFP_IAPRIMARY 0x00 202#define AFP_IASECONDARY1 0x01 203#define AFP_IASECONDARY2 0x02 204#define AFP_IASECONDARY3 0x03 205#define AFP_TX 0x06 206#define AFP_HASH 0x07 207 208#define RXCTL_PAUSEA (1 << 20) 209#define RXCTL_RXFCE1 (1 << 19) 210#define RXCTL_RXFCE0 (1 << 18) 211#define RXCTL_BCRC (1 << 17) 212#define RXCTL_SRXON (1 << 16) 213#define RXCTL_RCRCA (1 << 13) 214#define RXCTL_RA (1 << 12) 215#define RXCTL_PA (1 << 11) 216#define RXCTL_BA (1 << 10) 217#define RXCTL_MA (1 << 9) 218#define RXCTL_IAHA (1 << 8) 219#define RXCTL_IA3 (1 << 3) 220#define RXCTL_IA2 (1 << 2) 221#define RXCTL_IA1 (1 << 1) 222#define RXCTL_IA0 (1 << 0) 223 224#define TXCTL_DEFDIS (1 << 7) 225#define TXCTL_MBE (1 << 6) 226#define TXCTL_ICRC (1 << 5) 227#define TXCTL_TPD (1 << 4) 228#define TXCTL_OCOLL (1 << 3) 229#define TXCTL_SP (1 << 2) 230#define TXCTL_PB (1 << 1) 231#define TXCTL_STXON (1 << 0) 232 233#define MIICMD_REGAD_MASK (0x001F) 234#define MIICMD_PHYAD_MASK (0x03E0) 235#define MIICMD_OPCODE_MASK (0xC000) 236#define MIICMD_PHYAD_8950 (0x0000) 237#define MIICMD_OPCODE_READ (0x8000) 238#define MIICMD_OPCODE_WRITE (0x4000) 239 240#define MIISTS_BUSY (1 << 0) 241 242/* 243 * 0x80020000 - 0x8002FFFF: USB OHCI 244 */ 245#define USB_OFFSET 0x020000 246#define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET) 247 248/* 249 * 0x80030000 - 0x8003FFFF: Raster engine 250 */ 251#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315)) 252#define RASTER_OFFSET 0x030000 253#define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET) 254#endif 255 256/* 257 * 0x80040000 - 0x8004FFFF: Graphics accelerator 258 */ 259#if defined(CONFIG_EP9315) 260#define GFX_OFFSET 0x040000 261#define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET) 262#endif 263 264/* 265 * 0x80050000 - 0x8005FFFF: Reserved 266 */ 267 268/* 269 * 0x80060000 - 0x8006FFFF: SDRAM controller 270 */ 271#define SDRAM_OFFSET 0x060000 272#define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET) 273 274#ifndef __ASSEMBLY__ 275struct sdram_regs { 276 uint32_t reserved; 277 uint32_t glconfig; 278 uint32_t refrshtimr; 279 uint32_t bootsts; 280 uint32_t devcfg0; 281 uint32_t devcfg1; 282 uint32_t devcfg2; 283 uint32_t devcfg3; 284}; 285#endif 286 287#define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2) 288#define SDRAM_DEVCFG_BANKCOUNT (1 << 3) 289#define SDRAM_DEVCFG_SROMLL (1 << 5) 290#define SDRAM_DEVCFG_CASLAT_2 0x00010000 291#define SDRAM_DEVCFG_RASTOCAS_2 0x00200000 292 293#define SDRAM_OFF_GLCONFIG 0x0004 294#define SDRAM_OFF_REFRSHTIMR 0x0008 295 296#define SDRAM_OFF_DEVCFG0 0x0010 297#define SDRAM_OFF_DEVCFG1 0x0014 298#define SDRAM_OFF_DEVCFG2 0x0018 299#define SDRAM_OFF_DEVCFG3 0x001C 300 301#define SDRAM_DEVCFG0_BASE 0xC0000000 302#define SDRAM_DEVCFG1_BASE 0xD0000000 303#define SDRAM_DEVCFG2_BASE 0xE0000000 304#define SDRAM_DEVCFG3_ASD0_BASE 0xF0000000 305#define SDRAM_DEVCFG3_ASD1_BASE 0x00000000 306 307#define GLCONFIG_INIT (1 << 0) 308#define GLCONFIG_MRS (1 << 1) 309#define GLCONFIG_SMEMBUSY (1 << 5) 310#define GLCONFIG_LCR (1 << 6) 311#define GLCONFIG_REARBEN (1 << 7) 312#define GLCONFIG_CLKSHUTDOWN (1 << 30) 313#define GLCONFIG_CKE (1 << 31) 314 315#define EP93XX_SDRAMCTRL 0x80060000 316#define EP93XX_SDRAMCTRL_GLOBALCFG_INIT 0x00000001 317#define EP93XX_SDRAMCTRL_GLOBALCFG_MRS 0x00000002 318#define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY 0x00000020 319#define EP93XX_SDRAMCTRL_GLOBALCFG_LCR 0x00000040 320#define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN 0x00000080 321#define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN 0x40000000 322#define EP93XX_SDRAMCTRL_GLOBALCFG_CKE 0x80000000 323 324#define EP93XX_SDRAMCTRL_REFRESH_MASK 0x0000FFFF 325 326#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32 0x00000002 327#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16 0x00000001 328#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8 0x00000000 329#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK 0x00000003 330#define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA 0x00000004 331 332#define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH 0x00000004 333#define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT 0x00000008 334#define EP93XX_SDRAMCTRL_DEVCFG_SROM512 0x00000010 335#define EP93XX_SDRAMCTRL_DEVCFG_SROMLL 0x00000020 336#define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE 0x00000040 337#define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR 0x00000080 338#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK 0x00070000 339#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 0x00010000 340#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3 0x00020000 341#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4 0x00030000 342#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5 0x00040000 343#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6 0x00050000 344#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7 0x00060000 345#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8 0x00070000 346#define EP93XX_SDRAMCTRL_DEVCFG_WBL 0x00080000 347#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK 0x00300000 348#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 0x00200000 349#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3 0x00300000 350#define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE 0x01000000 351 352/* 353 * 0x80070000 - 0x8007FFFF: Reserved 354 */ 355 356/* 357 * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA 358 */ 359#define SMC_OFFSET 0x080000 360#define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET) 361 362#ifndef __ASSEMBLY__ 363struct smc_regs { 364 uint32_t bcr0; 365 uint32_t bcr1; 366 uint32_t bcr2; 367 uint32_t bcr3; 368 uint32_t reserved0[2]; 369 uint32_t bcr6; 370 uint32_t bcr7; 371#if defined(CONFIG_EP9315) 372 uint32_t pcattribute; 373 uint32_t pccommon; 374 uint32_t pcio; 375 uint32_t reserved1[5]; 376 uint32_t pcmciactrl; 377#endif 378}; 379#endif 380 381#define EP93XX_OFF_SMCBCR0 0x00 382#define EP93XX_OFF_SMCBCR1 0x04 383#define EP93XX_OFF_SMCBCR2 0x08 384#define EP93XX_OFF_SMCBCR3 0x0C 385#define EP93XX_OFF_SMCBCR6 0x18 386#define EP93XX_OFF_SMCBCR7 0x1C 387 388#define SMC_BCR_IDCY_SHIFT 0 389#define SMC_BCR_WST1_SHIFT 5 390#define SMC_BCR_BLE (1 << 10) 391#define SMC_BCR_WST2_SHIFT 11 392#define SMC_BCR_MW_SHIFT 28 393 394/* 395 * 0x80090000 - 0x8009FFFF: Boot ROM 396 */ 397 398/* 399 * 0x800A0000 - 0x800AFFFF: IDE interface 400 */ 401 402/* 403 * 0x800B0000 - 0x800BFFFF: VIC1 404 */ 405 406/* 407 * 0x800C0000 - 0x800CFFFF: VIC2 408 */ 409 410/* 411 * 0x800D0000 - 0x800FFFFF: Reserved 412 */ 413 414/* 415 * 0x80800000 - 0x8080FFFF: Reserved 416 */ 417 418/* 419 * 0x80810000 - 0x8081FFFF: Timers 420 */ 421#define TIMER_OFFSET 0x010000 422#define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET) 423 424#ifndef __ASSEMBLY__ 425struct timer { 426 uint32_t load; 427 uint32_t value; 428 uint32_t control; 429 uint32_t clear; 430}; 431 432struct timer4 { 433 uint32_t value_low; 434 uint32_t value_high; 435}; 436 437struct timer_regs { 438 struct timer timer1; 439 uint32_t reserved0[4]; 440 struct timer timer2; 441 uint32_t reserved1[12]; 442 struct timer4 timer4; 443 uint32_t reserved2[6]; 444 struct timer timer3; 445}; 446#endif 447 448/* 449 * 0x80820000 - 0x8082FFFF: I2S 450 */ 451#define I2S_OFFSET 0x020000 452#define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET) 453 454/* 455 * 0x80830000 - 0x8083FFFF: Security 456 */ 457#define SECURITY_OFFSET 0x030000 458#define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET) 459 460#define EXTENSIONID (SECURITY_BASE + 0x2714) 461 462/* 463 * 0x80840000 - 0x8084FFFF: GPIO 464 */ 465#define GPIO_OFFSET 0x040000 466#define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET) 467 468#ifndef __ASSEMBLY__ 469struct gpio_int { 470 uint32_t inttype1; 471 uint32_t inttype2; 472 uint32_t eoi; 473 uint32_t inten; 474 uint32_t intsts; 475 uint32_t rawintsts; 476 uint32_t db; 477}; 478 479struct gpio_regs { 480 uint32_t padr; 481 uint32_t pbdr; 482 uint32_t pcdr; 483 uint32_t pddr; 484 uint32_t paddr; 485 uint32_t pbddr; 486 uint32_t pcddr; 487 uint32_t pdddr; 488 uint32_t pedr; 489 uint32_t peddr; 490 uint32_t reserved0[2]; 491 uint32_t pfdr; 492 uint32_t pfddr; 493 uint32_t pgdr; 494 uint32_t pgddr; 495 uint32_t phdr; 496 uint32_t phddr; 497 uint32_t reserved1; 498 uint32_t finttype1; 499 uint32_t finttype2; 500 uint32_t reserved2; 501 struct gpio_int pfint; 502 uint32_t reserved3[10]; 503 struct gpio_int paint; 504 struct gpio_int pbint; 505 uint32_t eedrive; 506}; 507#endif 508 509#define EP93XX_LED_DATA 0x80840020 510#define EP93XX_LED_GREEN_ON 0x0001 511#define EP93XX_LED_RED_ON 0x0002 512 513#define EP93XX_LED_DDR 0x80840024 514#define EP93XX_LED_GREEN_ENABLE 0x0001 515#define EP93XX_LED_RED_ENABLE 0x00020000 516 517/* 518 * 0x80850000 - 0x8087FFFF: Reserved 519 */ 520 521/* 522 * 0x80880000 - 0x8088FFFF: AAC 523 */ 524#define AAC_OFFSET 0x080000 525#define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET) 526 527/* 528 * 0x80890000 - 0x8089FFFF: Reserved 529 */ 530 531/* 532 * 0x808A0000 - 0x808AFFFF: SPI 533 */ 534#define SPI_OFFSET 0x0A0000 535#define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET) 536 537/* 538 * 0x808B0000 - 0x808BFFFF: IrDA 539 */ 540#define IRDA_OFFSET 0x0B0000 541#define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET) 542 543/* 544 * 0x808C0000 - 0x808CFFFF: UART1 545 */ 546#define UART1_OFFSET 0x0C0000 547#define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET) 548 549/* 550 * 0x808D0000 - 0x808DFFFF: UART2 551 */ 552#define UART2_OFFSET 0x0D0000 553#define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET) 554 555/* 556 * 0x808E0000 - 0x808EFFFF: UART3 557 */ 558#define UART3_OFFSET 0x0E0000 559#define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET) 560 561/* 562 * 0x808F0000 - 0x808FFFFF: Key Matrix 563 */ 564#define KEY_OFFSET 0x0F0000 565#define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET) 566 567/* 568 * 0x80900000 - 0x8090FFFF: Touchscreen 569 */ 570#define TOUCH_OFFSET 0x900000 571#define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET) 572 573/* 574 * 0x80910000 - 0x8091FFFF: Pulse Width Modulation 575 */ 576#define PWM_OFFSET 0x910000 577#define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET) 578 579/* 580 * 0x80920000 - 0x8092FFFF: Real time clock 581 */ 582#define RTC_OFFSET 0x920000 583#define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET) 584 585/* 586 * 0x80930000 - 0x8093FFFF: Syscon 587 */ 588#define SYSCON_OFFSET 0x930000 589#define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET) 590 591/* Security */ 592#define SECURITY_EXTENSIONID 0x80832714 593 594#ifndef __ASSEMBLY__ 595struct syscon_regs { 596 uint32_t pwrsts; 597 uint32_t pwrcnt; 598 uint32_t halt; 599 uint32_t stby; 600 uint32_t reserved0[2]; 601 uint32_t teoi; 602 uint32_t stfclr; 603 uint32_t clkset1; 604 uint32_t clkset2; 605 uint32_t reserved1[6]; 606 uint32_t scratch0; 607 uint32_t scratch1; 608 uint32_t reserved2[2]; 609 uint32_t apbwait; 610 uint32_t bustmstrarb; 611 uint32_t bootmodeclr; 612 uint32_t reserved3[9]; 613 uint32_t devicecfg; 614 uint32_t vidclkdiv; 615 uint32_t mirclkdiv; 616 uint32_t i2sclkdiv; 617 uint32_t keytchclkdiv; 618 uint32_t chipid; 619 uint32_t reserved4; 620 uint32_t syscfg; 621 uint32_t reserved5[8]; 622 uint32_t sysswlock; 623}; 624#else 625#define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040) 626#endif 627 628#define SYSCON_OFF_CLKSET1 0x0020 629#define SYSCON_OFF_SYSCFG 0x009c 630 631#define SYSCON_PWRCNT_UART_BAUD (1 << 29) 632#define SYSCON_PWRCNT_USH_EN (1 << 28) 633 634#define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0 635#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5 636#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT 11 637#define SYSCON_CLKSET_PLL_PS_SHIFT 16 638#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18 639#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20 640#define SYSCON_CLKSET1_NBYP1 (1 << 23) 641#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25 642 643#define SYSCON_CLKSET2_PLL2_EN (1 << 18) 644#define SYSCON_CLKSET2_NBYP2 (1 << 19) 645#define SYSCON_CLKSET2_USB_DIV_SHIFT 28 646 647#define SYSCON_CHIPID_REV_MASK 0xF0000000 648#define SYSCON_DEVICECFG_SWRST (1 << 31) 649 650#define SYSCON_SYSCFG_LASDO 0x00000020 651 652/* 653 * 0x80930000 - 0x8093FFFF: Watchdog Timer 654 */ 655#define WATCHDOG_OFFSET 0x940000 656#define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET) 657 658/* 659 * 0x80950000 - 0x9000FFFF: Reserved 660 */ 661 662/* 663 * During low_level init we store memory layout in memory at specific location 664 */ 665#define UBOOT_MEMORYCNF_BANK_SIZE 0x2000 666#define UBOOT_MEMORYCNF_BANK_MASK 0x2004 667#define UBOOT_MEMORYCNF_BANK_COUNT 0x2008 668