1/* 2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef _LPC32XX_UART_H 8#define _LPC32XX_UART_H 9 10#include <asm/types.h> 11 12/* 14-clock UART Registers */ 13struct hsuart_regs { 14 union { 15 u32 rx; /* Receiver FIFO */ 16 u32 tx; /* Transmitter FIFO */ 17 }; 18 u32 level; /* FIFO Level Register */ 19 u32 iir; /* Interrupt ID Register */ 20 u32 ctrl; /* Control Register */ 21 u32 rate; /* Rate Control Register */ 22}; 23 24/* 14-clock UART Receiver FIFO Register bits */ 25#define HSUART_RX_BREAK (1 << 10) 26#define HSUART_RX_ERROR (1 << 9) 27#define HSUART_RX_EMPTY (1 << 8) 28#define HSUART_RX_DATA (0xff << 0) 29 30/* 14-clock UART Level Register bits */ 31#define HSUART_LEVEL_TX (0xff << 8) 32#define HSUART_LEVEL_RX (0xff << 0) 33 34/* 14-clock UART Interrupt Identification Register bits */ 35#define HSUART_IIR_TX_INT_SET (1 << 6) 36#define HSUART_IIR_RX_OE (1 << 5) 37#define HSUART_IIR_BRK (1 << 4) 38#define HSUART_IIR_FE (1 << 3) 39#define HSUART_IIR_RX_TIMEOUT (1 << 2) 40#define HSUART_IIR_RX_TRIG (1 << 1) 41#define HSUART_IIR_TX (1 << 0) 42 43/* 14-clock UART Control Register bits */ 44#define HSUART_CTRL_HRTS_INV (1 << 21) 45#define HSUART_CTRL_HRTS_TRIG_48 (0x3 << 19) 46#define HSUART_CTRL_HRTS_TRIG_32 (0x2 << 19) 47#define HSUART_CTRL_HRTS_TRIG_16 (0x1 << 19) 48#define HSUART_CTRL_HRTS_TRIG_8 (0x0 << 19) 49#define HSUART_CTRL_HRTS_EN (1 << 18) 50#define HSUART_CTRL_TMO_16 (0x3 << 16) 51#define HSUART_CTRL_TMO_8 (0x2 << 16) 52#define HSUART_CTRL_TMO_4 (0x1 << 16) 53#define HSUART_CTRL_TMO_DISABLED (0x0 << 16) 54#define HSUART_CTRL_HCTS_INV (1 << 15) 55#define HSUART_CTRL_HCTS_EN (1 << 14) 56#define HSUART_CTRL_HSU_OFFSET(n) ((n) << 9) 57#define HSUART_CTRL_HSU_BREAK (1 << 8) 58#define HSUART_CTRL_HSU_ERR_INT_EN (1 << 7) 59#define HSUART_CTRL_HSU_RX_INT_EN (1 << 6) 60#define HSUART_CTRL_HSU_TX_INT_EN (1 << 5) 61#define HSUART_CTRL_HSU_RX_TRIG_48 (0x5 << 2) 62#define HSUART_CTRL_HSU_RX_TRIG_32 (0x4 << 2) 63#define HSUART_CTRL_HSU_RX_TRIG_16 (0x3 << 2) 64#define HSUART_CTRL_HSU_RX_TRIG_8 (0x2 << 2) 65#define HSUART_CTRL_HSU_RX_TRIG_4 (0x1 << 2) 66#define HSUART_CTRL_HSU_RX_TRIG_1 (0x0 << 2) 67#define HSUART_CTRL_HSU_TX_TRIG_16 (0x3 << 0) 68#define HSUART_CTRL_HSU_TX_TRIG_8 (0x2 << 0) 69#define HSUART_CTRL_HSU_TX_TRIG_4 (0x1 << 0) 70#define HSUART_CTRL_HSU_TX_TRIG_0 (0x0 << 0) 71 72/* UART Control Registers */ 73struct uart_ctrl_regs { 74 u32 ctrl; /* Control Register */ 75 u32 clkmode; /* Clock Mode Register */ 76 u32 loop; /* Loopback Control Register */ 77}; 78 79/* UART Control Register bits */ 80#define UART_CTRL_UART3_MD_CTRL (1 << 11) 81#define UART_CTRL_HDPX_INV (1 << 10) 82#define UART_CTRL_HDPX_EN (1 << 9) 83#define UART_CTRL_UART6_IRDA (1 << 5) 84#define UART_CTRL_IR_TX6_INV (1 << 4) 85#define UART_CTRL_IR_RX6_INV (1 << 3) 86#define UART_CTRL_IR_RX_LENGTH (1 << 2) 87#define UART_CTRL_IR_TX_LENGTH (1 << 1) 88#define UART_CTRL_UART5_USB_MODE (1 << 0) 89 90/* UART Clock Mode Register bits */ 91#define UART_CLKMODE_STATX(n) (1 << ((n) + 16)) 92#define UART_CLKMODE_STAT (1 << 14) 93#define UART_CLKMODE_MASK(n) (0x3 << (2 * (n) - 2)) 94#define UART_CLKMODE_AUTO(n) (0x2 << (2 * (n) - 2)) 95#define UART_CLKMODE_ON(n) (0x1 << (2 * (n) - 2)) 96#define UART_CLKMODE_OFF(n) (0x0 << (2 * (n) - 2)) 97 98/* UART Loopback Control Register bits */ 99#define UART_LOOPBACK(n) (1 << ((n) - 1)) 100 101#endif /* _LPC32XX_UART_H */ 102