LXR uboot/arch/arm/include/asm/arch-mx6/mxc

   1/*
   2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
   3 */
   4
   5/*
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9#ifndef __MXC_HDMI_H__
  10#define __MXC_HDMI_H__
  11
  12#ifdef CONFIG_IMX_HDMI
  13void imx_enable_hdmi_phy(void);
  14void imx_setup_hdmi(void);
  15#endif
  16
  17/*
  18 * Hdmi controller registers
  19 */
  20struct hdmi_regs {
  21        /*Identification Registers */
  22        u8 design_id;                   /* 0x000 */
  23        u8 revision_id;                 /* 0x001 */
  24        u8 product_id0;                 /* 0x002 */
  25        u8 product_id1;                 /* 0x003 */
  26        u8 config0_id;                  /* 0x004 */
  27        u8 config1_id;                  /* 0x005 */
  28        u8 config2_id;                  /* 0x006 */
  29        u8 config3_id;                  /* 0x007 */
  30        u8 reserved1[0xf8];
  31        /* Interrupt Registers */
  32        u8 ih_fc_stat0;                 /* 0x100 */
  33        u8 ih_fc_stat1;                 /* 0x101 */
  34        u8 ih_fc_stat2;                 /* 0x102 */
  35        u8 ih_as_stat0;                 /* 0x103 */
  36        u8 ih_phy_stat0;                /* 0x104 */
  37        u8 ih_i2cm_stat0;               /* 0x105 */
  38        u8 ih_cec_stat0;                /* 0x106 */
  39        u8 ih_vp_stat0;                 /* 0x107 */
  40        u8 ih_i2cmphy_stat0;            /* 0x108 */
  41        u8 ih_ahbdmaaud_stat0;          /* 0x109 */
  42        u8 reserved2[0x76];
  43        u8 ih_mute_fc_stat0;            /* 0x180 */
  44        u8 ih_mute_fc_stat1;            /* 0x181 */
  45        u8 ih_mute_fc_stat2;            /* 0x182 */
  46        u8 ih_mute_as_stat0;            /* 0x183 */
  47        u8 ih_mute_phy_stat0;           /* 0x184 */
  48        u8 ih_mute_i2cm_stat0;          /* 0x185 */
  49        u8 ih_mute_cec_stat0;           /* 0x186 */
  50        u8 ih_mute_vp_stat0;            /* 0x187 */
  51        u8 ih_mute_i2cmphy_stat0;       /* 0x188 */
  52        u8 ih_mute_ahbdmaaud_stat0;     /* 0x189 */
  53        u8 reserved3[0x75];
  54        u8 ih_mute;                     /* 0x1ff */
  55        /* Video Sample Registers */
  56        u8 tx_invid0;                   /* 0x200 */
  57        u8 tx_instuffing;               /* 0x201 */
  58        u8 tx_gydata0;                  /* 0x202 */
  59        u8 tx_gydata1;                  /* 0x203 */
  60        u8 tx_rcrdata0;                 /* 0x204 */
  61        u8 tx_rcrdata1;                 /* 0x205 */
  62        u8 tx_bcbdata0;                 /* 0x206 */
  63        u8 tx_bcbdata1;                 /* 0x207 */
  64        u8 reserved4[0x5f8];
  65        /* Video Packetizer Registers */
  66        u8 vp_status;                   /* 0x800 */
  67        u8 vp_pr_cd;                    /* 0x801 */
  68        u8 vp_stuff;                    /* 0x802 */
  69        u8 vp_remap;                    /* 0x803 */
  70        u8 vp_conf;                     /* 0x804 */
  71        u8 vp_stat;                     /* 0x805 */
  72        u8 vp_int;                      /* 0x806 */
  73        u8 vp_mask;                     /* 0x807 */
  74        u8 vp_pol;                      /* 0x808 */
  75        u8 reserved5[0x7f7];
  76        /* Frame Composer Registers */
  77        u8 fc_invidconf;                /* 0x1000 */
  78        u8 fc_inhactv0;                 /* 0x1001 */
  79        u8 fc_inhactv1;                 /* 0x1002 */
  80        u8 fc_inhblank0;                /* 0x1003 */
  81        u8 fc_inhblank1;                /* 0x1004 */
  82        u8 fc_invactv0;                 /* 0x1005 */
  83        u8 fc_invactv1;                 /* 0x1006 */
  84        u8 fc_invblank;                 /* 0x1007 */
  85        u8 fc_hsyncindelay0;            /* 0x1008 */
  86        u8 fc_hsyncindelay1;            /* 0x1009 */
  87        u8 fc_hsyncinwidth0;            /* 0x100a */
  88        u8 fc_hsyncinwidth1;            /* 0x100b */
  89        u8 fc_vsyncindelay;             /* 0x100c */
  90        u8 fc_vsyncinwidth;             /* 0x100d */
  91        u8 fc_infreq0;                  /* 0x100e */
  92        u8 fc_infreq1;                  /* 0x100f */
  93        u8 fc_infreq2;                  /* 0x1010 */
  94        u8 fc_ctrldur;                  /* 0x1011 */
  95        u8 fc_exctrldur;                /* 0x1012 */
  96        u8 fc_exctrlspac;               /* 0x1013 */
  97        u8 fc_ch0pream;                 /* 0x1014 */
  98        u8 fc_ch1pream;                 /* 0x1015 */
  99        u8 fc_ch2pream;                 /* 0x1016 */
 100        u8 fc_aviconf3;                 /* 0x1017 */
 101        u8 fc_gcp;                      /* 0x1018 */
 102        u8 fc_aviconf0;                 /* 0x1019 */
 103        u8 fc_aviconf1;                 /* 0x101a */
 104        u8 fc_aviconf2;                 /* 0x101b */
 105        u8 fc_avivid;                   /* 0x101c */
 106        u8 fc_avietb0;                  /* 0x101d */
 107        u8 fc_avietb1;                  /* 0x101e */
 108        u8 fc_avisbb0;                  /* 0x101f */
 109        u8 fc_avisbb1;                  /* 0x1020 */
 110        u8 fc_avielb0;                  /* 0x1021 */
 111        u8 fc_avielb1;                  /* 0x1022 */
 112        u8 fc_avisrb0;                  /* 0x1023 */
 113        u8 fc_avisrb1;                  /* 0x1024 */
 114        u8 fc_audiconf0;                /* 0x1025 */
 115        u8 fc_audiconf1;                /* 0x1026 */
 116        u8 fc_audiconf2;                /* 0x1027 */
 117        u8 fc_audiconf3;                /* 0x1028 */
 118        u8 fc_vsdieeeid0;               /* 0x1029 */
 119        u8 fc_vsdsize;                  /* 0x102a */
 120        u8 reserved6[5];
 121        u8 fc_vsdieeeid1;               /* 0x1030 */
 122        u8 fc_vsdieeeid2;               /* 0x1031 */
 123        u8 fc_vsdpayload0;              /* 0x1032 */
 124        u8 fc_vsdpayload1;              /* 0x1033 */
 125        u8 fc_vsdpayload2;              /* 0x1034 */
 126        u8 fc_vsdpayload3;              /* 0x1035 */
 127        u8 fc_vsdpayload4;              /* 0x1036 */
 128        u8 fc_vsdpayload5;              /* 0x1037 */
 129        u8 fc_vsdpayload6;              /* 0x1038 */
 130        u8 fc_vsdpayload7;              /* 0x1039 */
 131        u8 fc_vsdpayload8;              /* 0x103a */
 132        u8 fc_vsdpayload9;              /* 0x103b */
 133        u8 fc_vsdpayload10;             /* 0x103c */
 134        u8 fc_vsdpayload11;             /* 0x103d */
 135        u8 fc_vsdpayload12;             /* 0x103e */
 136        u8 fc_vsdpayload13;             /* 0x103f */
 137        u8 fc_vsdpayload14;             /* 0x1040 */
 138        u8 fc_vsdpayload15;             /* 0x1041 */
 139        u8 fc_vsdpayload16;             /* 0x1042 */
 140        u8 fc_vsdpayload17;             /* 0x1043 */
 141        u8 fc_vsdpayload18;             /* 0x1044 */
 142        u8 fc_vsdpayload19;             /* 0x1045 */
 143        u8 fc_vsdpayload20;             /* 0x1046 */
 144        u8 fc_vsdpayload21;             /* 0x1047 */
 145        u8 fc_vsdpayload22;             /* 0x1048 */
 146        u8 fc_vsdpayload23;             /* 0x1049 */
 147        u8 fc_spdvendorname0;           /* 0x104a */
 148        u8 fc_spdvendorname1;           /* 0x104b */
 149        u8 fc_spdvendorname2;           /* 0x104c */
 150        u8 fc_spdvendorname3;           /* 0x104d */
 151        u8 fc_spdvendorname4;           /* 0x104e */
 152        u8 fc_spdvendorname5;           /* 0x104f */
 153        u8 fc_spdvendorname6;           /* 0x1050 */
 154        u8 fc_spdvendorname7;           /* 0x1051 */
 155        u8 fc_sdpproductname0;          /* 0x1052 */
 156        u8 fc_sdpproductname1;          /* 0x1053 */
 157        u8 fc_sdpproductname2;          /* 0x1054 */
 158        u8 fc_sdpproductname3;          /* 0x1055 */
 159        u8 fc_sdpproductname4;          /* 0x1056 */
 160        u8 fc_sdpproductname5;          /* 0x1057 */
 161        u8 fc_sdpproductname6;          /* 0x1058 */
 162        u8 fc_sdpproductname7;          /* 0x1059 */
 163        u8 fc_sdpproductname8;          /* 0x105a */
 164        u8 fc_sdpproductname9;          /* 0x105b */
 165        u8 fc_sdpproductname10;         /* 0x105c */
 166        u8 fc_sdpproductname11;         /* 0x105d */
 167        u8 fc_sdpproductname12;         /* 0x105e */
 168        u8 fc_sdpproductname13;         /* 0x105f */
 169        u8 fc_sdpproductname14;         /* 0x1060 */
 170        u8 fc_spdproductname15;         /* 0x1061 */
 171        u8 fc_spddeviceinf;             /* 0x1062 */
 172        u8 fc_audsconf;                 /* 0x1063 */
 173        u8 fc_audsstat;                 /* 0x1064 */
 174        u8 reserved7[0xb];
 175        u8 fc_datach0fill;              /* 0x1070 */
 176        u8 fc_datach1fill;              /* 0x1071 */
 177        u8 fc_datach2fill;              /* 0x1072 */
 178        u8 fc_ctrlqhigh;                /* 0x1073 */
 179        u8 fc_ctrlqlow;                 /* 0x1074 */
 180        u8 fc_acp0;                     /* 0x1075 */
 181        u8 fc_acp28;                    /* 0x1076 */
 182        u8 fc_acp27;                    /* 0x1077 */
 183        u8 fc_acp26;                    /* 0x1078 */
 184        u8 fc_acp25;                    /* 0x1079 */
 185        u8 fc_acp24;                    /* 0x107a */
 186        u8 fc_acp23;                    /* 0x107b */
 187        u8 fc_acp22;                    /* 0x107c */
 188        u8 fc_acp21;                    /* 0x107d */
 189        u8 fc_acp20;                    /* 0x107e */
 190        u8 fc_acp19;                    /* 0x107f */
 191        u8 fc_acp18;                    /* 0x1080 */
 192        u8 fc_acp17;                    /* 0x1081 */
 193        u8 fc_acp16;                    /* 0x1082 */
 194        u8 fc_acp15;                    /* 0x1083 */
 195        u8 fc_acp14;                    /* 0x1084 */
 196        u8 fc_acp13;                    /* 0x1085 */
 197        u8 fc_acp12;                    /* 0x1086 */
 198        u8 fc_acp11;                    /* 0x1087 */
 199        u8 fc_acp10;                    /* 0x1088 */
 200        u8 fc_acp9;                     /* 0x1089 */
 201        u8 fc_acp8;                     /* 0x108a */
 202        u8 fc_acp7;                     /* 0x108b */
 203        u8 fc_acp6;                     /* 0x108c */
 204        u8 fc_acp5;                     /* 0x108d */
 205        u8 fc_acp4;                     /* 0x108e */
 206        u8 fc_acp3;                     /* 0x108f */
 207        u8 fc_acp2;                     /* 0x1090 */
 208        u8 fc_acp1;                     /* 0x1091 */
 209        u8 fc_iscr1_0;                  /* 0x1092 */
 210        u8 fc_iscr1_16;                 /* 0x1093 */
 211        u8 fc_iscr1_15;                 /* 0x1094 */
 212        u8 fc_iscr1_14;                 /* 0x1095 */
 213        u8 fc_iscr1_13;                 /* 0x1096 */
 214        u8 fc_iscr1_12;                 /* 0x1097 */
 215        u8 fc_iscr1_11;                 /* 0x1098 */
 216        u8 fc_iscr1_10;                 /* 0x1099 */
 217        u8 fc_iscr1_9;                  /* 0x109a */
 218        u8 fc_iscr1_8;                  /* 0x109b */
 219        u8 fc_iscr1_7;                  /* 0x109c */
 220        u8 fc_iscr1_6;                  /* 0x109d */
 221        u8 fc_iscr1_5;                  /* 0x109e */
 222        u8 fc_iscr1_4;                  /* 0x109f */
 223        u8 fc_iscr1_3;                  /* 0x10a0 */
 224        u8 fc_iscr1_2;                  /* 0x10a1 */
 225        u8 fc_iscr1_1;                  /* 0x10a2 */
 226        u8 fc_iscr2_15;                 /* 0x10a3 */
 227        u8 fc_iscr2_14;                 /* 0x10a4 */
 228        u8 fc_iscr2_13;                 /* 0x10a5 */
 229        u8 fc_iscr2_12;                 /* 0x10a6 */
 230        u8 fc_iscr2_11;                 /* 0x10a7 */
 231        u8 fc_iscr2_10;                 /* 0x10a8 */
 232        u8 fc_iscr2_9;                  /* 0x10a9 */
 233        u8 fc_iscr2_8;                  /* 0x10aa */
 234        u8 fc_iscr2_7;                  /* 0x10ab */
 235        u8 fc_iscr2_6;                  /* 0x10ac */
 236        u8 fc_iscr2_5;                  /* 0x10ad */
 237        u8 fc_iscr2_4;                  /* 0x10ae */
 238        u8 fc_iscr2_3;                  /* 0x10af */
 239        u8 fc_iscr2_2;                  /* 0x10b0 */
 240        u8 fc_iscr2_1;                  /* 0x10b1 */
 241        u8 fc_iscr2_0;                  /* 0x10b2 */
 242        u8 fc_datauto0;                 /* 0x10b3 */
 243        u8 fc_datauto1;                 /* 0x10b4 */
 244        u8 fc_datauto2;                 /* 0x10b5 */
 245        u8 fc_datman;                   /* 0x10b6 */
 246        u8 fc_datauto3;                 /* 0x10b7 */
 247        u8 fc_rdrb0;                    /* 0x10b8 */
 248        u8 fc_rdrb1;                    /* 0x10b9 */
 249        u8 fc_rdrb2;                    /* 0x10ba */
 250        u8 fc_rdrb3;                    /* 0x10bb */
 251        u8 fc_rdrb4;                    /* 0x10bc */
 252        u8 fc_rdrb5;                    /* 0x10bd */
 253        u8 fc_rdrb6;                    /* 0x10be */
 254        u8 fc_rdrb7;                    /* 0x10bf */
 255        u8 reserved8[0x10];
 256        u8 fc_stat0;                    /* 0x10d0 */
 257        u8 fc_int0;                     /* 0x10d1 */
 258        u8 fc_mask0;                    /* 0x10d2 */
 259        u8 fc_pol0;                     /* 0x10d3 */
 260        u8 fc_stat1;                    /* 0x10d4 */
 261        u8 fc_int1;                     /* 0x10d5 */
 262        u8 fc_mask1;                    /* 0x10d6 */
 263        u8 fc_pol1;                     /* 0x10d7 */
 264        u8 fc_stat2;                    /* 0x10d8 */
 265        u8 fc_int2;                     /* 0x10d9 */
 266        u8 fc_mask2;                    /* 0x10da */
 267        u8 fc_pol2;                     /* 0x10db */
 268        u8 reserved9[0x4];
 269        u8 fc_prconf;                   /* 0x10e0 */
 270        u8 reserved10[0x1f];
 271        u8 fc_gmd_stat;                 /* 0x1100 */
 272        u8 fc_gmd_en;                   /* 0x1101 */
 273        u8 fc_gmd_up;                   /* 0x1102 */
 274        u8 fc_gmd_conf;                 /* 0x1103 */
 275        u8 fc_gmd_hb;                   /* 0x1104 */
 276        u8 fc_gmd_pb0;                  /* 0x1105 */
 277        u8 fc_gmd_pb1;                  /* 0x1106 */
 278        u8 fc_gmd_pb2;                  /* 0x1107 */
 279        u8 fc_gmd_pb3;                  /* 0x1108 */
 280        u8 fc_gmd_pb4;                  /* 0x1109 */
 281        u8 fc_gmd_pb5;                  /* 0x110a */
 282        u8 fc_gmd_pb6;                  /* 0x110b */
 283        u8 fc_gmd_pb7;                  /* 0x110c */
 284        u8 fc_gmd_pb8;                  /* 0x110d */
 285        u8 fc_gmd_pb9;                  /* 0x110e */
 286        u8 fc_gmd_pb10;                 /* 0x110f */
 287        u8 fc_gmd_pb11;                 /* 0x1110 */
 288        u8 fc_gmd_pb12;                 /* 0x1111 */
 289        u8 fc_gmd_pb13;                 /* 0x1112 */
 290        u8 fc_gmd_pb14;                 /* 0x1113 */
 291        u8 fc_gmd_pb15;                 /* 0x1114 */
 292        u8 fc_gmd_pb16;                 /* 0x1115 */
 293        u8 fc_gmd_pb17;                 /* 0x1116 */
 294        u8 fc_gmd_pb18;                 /* 0x1117 */
 295        u8 fc_gmd_pb19;                 /* 0x1118 */
 296        u8 fc_gmd_pb20;                 /* 0x1119 */
 297        u8 fc_gmd_pb21;                 /* 0x111a */
 298        u8 fc_gmd_pb22;                 /* 0x111b */
 299        u8 fc_gmd_pb23;                 /* 0x111c */
 300        u8 fc_gmd_pb24;                 /* 0x111d */
 301        u8 fc_gmd_pb25;                 /* 0x111e */
 302        u8 fc_gmd_pb26;                 /* 0x111f */
 303        u8 fc_gmd_pb27;                 /* 0x1120 */
 304        u8 reserved11[0xdf];
 305        u8 fc_dbgforce;                 /* 0x1200 */
 306        u8 fc_dbgaud0ch0;               /* 0x1201 */
 307        u8 fc_dbgaud1ch0;               /* 0x1202 */
 308        u8 fc_dbgaud2ch0;               /* 0x1203 */
 309        u8 fc_dbgaud0ch1;               /* 0x1204 */
 310        u8 fc_dbgaud1ch1;               /* 0x1205 */
 311        u8 fc_dbgaud2ch1;               /* 0x1206 */
 312        u8 fc_dbgaud0ch2;               /* 0x1207 */
 313        u8 fc_dbgaud1ch2;               /* 0x1208 */
 314        u8 fc_dbgaud2ch2;               /* 0x1209 */
 315        u8 fc_dbgaud0ch3;               /* 0x120a */
 316        u8 fc_dbgaud1ch3;               /* 0x120b */
 317        u8 fc_dbgaud2ch3;               /* 0x120c */
 318        u8 fc_dbgaud0ch4;               /* 0x120d */
 319        u8 fc_dbgaud1ch4;               /* 0x120e */
 320        u8 fc_dbgaud2ch4;               /* 0x120f */
 321        u8 fc_dbgaud0ch5;               /* 0x1210 */
 322        u8 fc_dbgaud1ch5;               /* 0x1211 */
 323        u8 fc_dbgaud2ch5;               /* 0x1212 */
 324        u8 fc_dbgaud0ch6;               /* 0x1213 */
 325        u8 fc_dbgaud1ch6;               /* 0x1214 */
 326        u8 fc_dbgaud2ch6;               /* 0x1215 */
 327        u8 fc_dbgaud0ch7;               /* 0x1216 */
 328        u8 fc_dbgaud1ch7;               /* 0x1217 */
 329        u8 fc_dbgaud2ch7;               /* 0x1218 */
 330        u8 fc_dbgtmds0;                 /* 0x1219 */
 331        u8 fc_dbgtmds1;                 /* 0x121a */
 332        u8 fc_dbgtmds2;                 /* 0x121b */
 333        u8 reserved12[0x1de4];
 334        /* Hdmi Source Phy Registers */
 335        u8 phy_conf0;                   /* 0x3000 */
 336        u8 phy_tst0;                    /* 0x3001 */
 337        u8 phy_tst1;                    /* 0x3002 */
 338        u8 phy_tst2;                    /* 0x3003 */
 339        u8 phy_stat0;                   /* 0x3004 */
 340        u8 phy_int0;                    /* 0x3005 */
 341        u8 phy_mask0;                   /* 0x3006 */
 342        u8 phy_pol0;                    /* 0x3007 */
 343        u8 reserved13[0x18];
 344        /* Hdmi Master Phy Registers */
 345        u8 phy_i2cm_slave_addr;         /* 0x3020 */
 346        u8 phy_i2cm_address_addr;       /* 0x3021 */
 347        u8 phy_i2cm_datao_1_addr;       /* 0x3022 */
 348        u8 phy_i2cm_datao_0_addr;       /* 0x3023 */
 349        u8 phy_i2cm_datai_1_addr;       /* 0x3024 */
 350        u8 phy_i2cm_datai_0_addr;       /* 0x3025 */
 351        u8 phy_i2cm_operation_addr;     /* 0x3026 */
 352        u8 phy_i2cm_int_addr;           /* 0x3027 */
 353        u8 phy_i2cm_ctlint_addr;        /* 0x3028 */
 354        u8 phy_i2cm_div_addr;           /* 0x3029 */
 355        u8 phy_i2cm_softrstz_addr;      /* 0x302a */
 356        u8 phy_i2cm_ss_scl_hcnt_1_addr; /* 0x302b */
 357        u8 phy_i2cm_ss_scl_hcnt_0_addr; /* 0x302c */
 358        u8 phy_i2cm_ss_scl_lcnt_1_addr; /* 0x302d */
 359        u8 phy_i2cm_ss_scl_lcnt_0_addr; /* 0x302e */
 360        u8 phy_i2cm_fs_scl_hcnt_1_addr; /* 0x302f */
 361        u8 phy_i2cm_fs_scl_hcnt_0_addr; /* 0x3030 */
 362        u8 phy_i2cm_fs_scl_lcnt_1_addr; /* 0x3031 */
 363        u8 phy_i2cm_fs_scl_lcnt_0_addr; /* 0x3032 */
 364        u8 reserved14[0xcd];
 365        /* Audio Sampler Registers */
 366        u8 aud_conf0;                   /* 0x3100 */
 367        u8 aud_conf1;                   /* 0x3101 */
 368        u8 aud_int;                     /* 0x3102 */
 369        u8 aud_conf2;                   /* 0x3103 */
 370        u8 reserved15[0xfc];
 371        u8 aud_n1;                      /* 0x3200 */
 372        u8 aud_n2;                      /* 0x3201 */
 373        u8 aud_n3;                      /* 0x3202 */
 374        u8 aud_cts1;                    /* 0x3203 */
 375        u8 aud_cts2;                    /* 0x3204 */
 376        u8 aud_cts3;                    /* 0x3205 */
 377        u8 aud_inputclkfs;              /* 0x3206 */
 378        u8 reserved16[0xfb];
 379        u8 aud_spdifint;                /* 0x3302 */
 380        u8 reserved17[0xfd];
 381        u8 aud_conf0_hbr;               /* 0x3400 */
 382        u8 aud_hbr_status;              /* 0x3401 */
 383        u8 aud_hbr_int;                 /* 0x3402 */
 384        u8 aud_hbr_pol;                 /* 0x3403 */
 385        u8 aud_hbr_mask;                /* 0x3404 */
 386        u8 reserved18[0xfb];
 387        /*
 388         * Generic Parallel Audio Interface Registers
 389         * Not used as GPAUD interface is not enabled in hw
 390         */
 391        u8 gp_conf0;                    /* 0x3500 */
 392        u8 gp_conf1;                    /* 0x3501 */
 393        u8 gp_conf2;                    /* 0x3502 */
 394        u8 gp_stat;                     /* 0x3503 */
 395        u8 gp_int;                      /* 0x3504 */
 396        u8 gp_mask;                     /* 0x3505 */
 397        u8 gp_pol;                      /* 0x3506 */
 398        u8 reserved19[0xf9];
 399        /* Audio DMA Registers */
 400        u8 ahb_dma_conf0;               /* 0x3600 */
 401        u8 ahb_dma_start;               /* 0x3601 */
 402        u8 ahb_dma_stop;                /* 0x3602 */
 403        u8 ahb_dma_thrsld;              /* 0x3603 */
 404        u8 ahb_dma_straddr0;            /* 0x3604 */
 405        u8 ahb_dma_straddr1;            /* 0x3605 */
 406        u8 ahb_dma_straddr2;            /* 0x3606 */
 407        u8 ahb_dma_straddr3;            /* 0x3607 */
 408        u8 ahb_dma_stpaddr0;            /* 0x3608 */
 409        u8 ahb_dma_stpaddr1;            /* 0x3609 */
 410        u8 ahb_dma_stpaddr2;            /* 0x360a */
 411        u8 ahb_dma_stpaddr3;            /* 0x360b */
 412        u8 ahb_dma_bstaddr0;            /* 0x360c */
 413        u8 ahb_dma_bstaddr1;            /* 0x360d */
 414        u8 ahb_dma_bstaddr2;            /* 0x360e */
 415        u8 ahb_dma_bstaddr3;            /* 0x360f */
 416        u8 ahb_dma_mblength0;           /* 0x3610 */
 417        u8 ahb_dma_mblength1;           /* 0x3611 */
 418        u8 ahb_dma_stat;                /* 0x3612 */
 419        u8 ahb_dma_int;                 /* 0x3613 */
 420        u8 ahb_dma_mask;                /* 0x3614 */
 421        u8 ahb_dma_pol;                 /* 0x3615 */
 422        u8 ahb_dma_conf1;               /* 0x3616 */
 423        u8 ahb_dma_buffstat;            /* 0x3617 */
 424        u8 ahb_dma_buffint;             /* 0x3618 */
 425        u8 ahb_dma_buffmask;            /* 0x3619 */
 426        u8 ahb_dma_buffpol;             /* 0x361a */
 427        u8 reserved20[0x9e5];
 428        /* Main Controller Registers */
 429        u8 mc_sfrdiv;                   /* 0x4000 */
 430        u8 mc_clkdis;                   /* 0x4001 */
 431        u8 mc_swrstz;                   /* 0x4002 */
 432        u8 mc_opctrl;                   /* 0x4003 */
 433        u8 mc_flowctrl;                 /* 0x4004 */
 434        u8 mc_phyrstz;                  /* 0x4005 */
 435        u8 mc_lockonclock;              /* 0x4006 */
 436        u8 mc_heacphy_rst;              /* 0x4007 */
 437        u8 reserved21[0xf8];
 438        /* Colorspace Converter Registers */
 439        u8 csc_cfg;                     /* 0x4100 */
 440        u8 csc_scale;                   /* 0x4101 */
 441        u8 csc_coef_a1_msb;             /* 0x4102 */
 442        u8 csc_coef_a1_lsb;             /* 0x4103 */
 443        u8 csc_coef_a2_msb;             /* 0x4104 */
 444        u8 csc_coef_a2_lsb;             /* 0x4105 */
 445        u8 csc_coef_a3_msb;             /* 0x4106 */
 446        u8 csc_coef_a3_lsb;             /* 0x4107 */
 447        u8 csc_coef_a4_msb;             /* 0x4108 */
 448        u8 csc_coef_a4_lsb;             /* 0x4109 */
 449        u8 csc_coef_b1_msb;             /* 0x410a */
 450        u8 csc_coef_b1_lsb;             /* 0x410b */
 451        u8 csc_coef_b2_msb;             /* 0x410c */
 452        u8 csc_coef_b2_lsb;             /* 0x410d */
 453        u8 csc_coef_b3_msb;             /* 0x410e */
 454        u8 csc_coef_b3_lsb;             /* 0x410f */
 455        u8 csc_coef_b4_msb;             /* 0x4110 */
 456        u8 csc_coef_b4_lsb;             /* 0x4111 */
 457        u8 csc_coef_c1_msb;             /* 0x4112 */
 458        u8 csc_coef_c1_lsb;             /* 0x4113 */
 459        u8 csc_coef_c2_msb;             /* 0x4114 */
 460        u8 csc_coef_c2_lsb;             /* 0x4115 */
 461        u8 csc_coef_c3_msb;             /* 0x4116 */
 462        u8 csc_coef_c3_lsb;             /* 0x4117 */
 463        u8 csc_coef_c4_msb;             /* 0x4118 */
 464        u8 csc_coef_c4_lsb;             /* 0x4119 */
 465        u8 reserved22[0xee6];
 466        /* HDCP Encryption Engine Registers */
 467        u8 a_hdcpcfg0;                  /* 0x5000 */
 468        u8 a_hdcpcfg1;                  /* 0x5001 */
 469        u8 a_hdcpobs0;                  /* 0x5002 */
 470        u8 a_hdcpobs1;                  /* 0x5003 */
 471        u8 a_hdcpobs2;                  /* 0x5004 */
 472        u8 a_hdcpobs3;                  /* 0x5005 */
 473        u8 a_apiintclr;                 /* 0x5006 */
 474        u8 a_apiintstat;                /* 0x5007 */
 475        u8 a_apiintmsk;                 /* 0x5008 */
 476        u8 a_vidpolcfg;                 /* 0x5009 */
 477        u8 a_oesswcfg;                  /* 0x500a */
 478        u8 a_timer1setup0;              /* 0x500b */
 479        u8 a_timer1setup1;              /* 0x500c */
 480        u8 a_timer2setup0;              /* 0x500d */
 481        u8 a_timer2setup1;              /* 0x500e */
 482        u8 a_100mscfg;                  /* 0x500f */
 483        u8 a_2scfg0;                    /* 0x5010 */
 484        u8 a_2scfg1;                    /* 0x5011 */
 485        u8 a_5scfg0;                    /* 0x5012 */
 486        u8 a_5scfg1;                    /* 0x5013 */
 487        u8 a_srmverlsb;                 /* 0x5014 */
 488        u8 a_srmvermsb;                 /* 0x5015 */
 489        u8 a_srmctrl;                   /* 0x5016 */
 490        u8 a_sfrsetup;                  /* 0x5017 */
 491        u8 a_i2chsetup;                 /* 0x5018 */
 492        u8 a_intsetup;                  /* 0x5019 */
 493        u8 a_presetup;                  /* 0x501a */
 494        u8 reserved23[0x5];
 495        u8 a_srm_base;                  /* 0x5020 */
 496        u8 reserved24[0x2cdf];
 497        /* CEC Engine Registers */
 498        u8 cec_ctrl;                    /* 0x7d00 */
 499        u8 cec_stat;                    /* 0x7d01 */
 500        u8 cec_mask;                    /* 0x7d02 */
 501        u8 cec_polarity;                /* 0x7d03 */
 502        u8 cec_int;                     /* 0x7d04 */
 503        u8 cec_addr_l;                  /* 0x7d05 */
 504        u8 cec_addr_h;                  /* 0x7d06 */
 505        u8 cec_tx_cnt;                  /* 0x7d07 */
 506        u8 cec_rx_cnt;                  /* 0x7d08 */
 507        u8 reserved25[0x7];
 508        u8 cec_tx_data0;                /* 0x7d10 */
 509        u8 cec_tx_data1;                /* 0x7d11 */
 510        u8 cec_tx_data2;                /* 0x7d12 */
 511        u8 cec_tx_data3;                /* 0x7d13 */
 512        u8 cec_tx_data4;                /* 0x7d14 */
 513        u8 cec_tx_data5;                /* 0x7d15 */
 514        u8 cec_tx_data6;                /* 0x7d16 */
 515        u8 cec_tx_data7;                /* 0x7d17 */
 516        u8 cec_tx_data8;                /* 0x7d18 */
 517        u8 cec_tx_data9;                /* 0x7d19 */
 518        u8 cec_tx_data10;               /* 0x7d1a */
 519        u8 cec_tx_data11;               /* 0x7d1b */
 520        u8 cec_tx_data12;               /* 0x7d1c */
 521        u8 cec_tx_data13;               /* 0x7d1d */
 522        u8 cec_tx_data14;               /* 0x7d1e */
 523        u8 cec_tx_data15;               /* 0x7d1f */
 524        u8 cec_rx_data0;                /* 0x7d20 */
 525        u8 cec_rx_data1;                /* 0x7d21 */
 526        u8 cec_rx_data2;                /* 0x7d22 */
 527        u8 cec_rx_data3;                /* 0x7d23 */
 528        u8 cec_rx_data4;                /* 0x7d24 */
 529        u8 cec_rx_data5;                /* 0x7d25 */
 530        u8 cec_rx_data6;                /* 0x7d26 */
 531        u8 cec_rx_data7;                /* 0x7d27 */
 532        u8 cec_rx_data8;                /* 0x7d28 */
 533        u8 cec_rx_data9;                /* 0x7d29 */
 534        u8 cec_rx_data10;               /* 0x7d2a */
 535        u8 cec_rx_data11;               /* 0x7d2b */
 536        u8 cec_rx_data12;               /* 0x7d2c */
 537        u8 cec_rx_data13;               /* 0x7d2d */
 538        u8 cec_rx_data14;               /* 0x7d2e */
 539        u8 cec_rx_data15;               /* 0x7d2f */
 540        u8 cec_lock;                    /* 0x7d30 */
 541        u8 cec_wkupctrl;                /* 0x7d31 */
 542        u8 reserved26[0xce];
 543        /* I2C Master Registers (E-DDC) */
 544        u8 i2cm_slave;                  /* 0x7e00 */
 545        u8 i2cmess;                     /* 0x7e01 */
 546        u8 i2cm_datao;                  /* 0x7e02 */
 547        u8 i2cm_datai;                  /* 0x7e03 */
 548        u8 i2cm_operation;              /* 0x7e04 */
 549        u8 i2cm_int;                    /* 0x7e05 */
 550        u8 i2cm_ctlint;                 /* 0x7e06 */
 551        u8 i2cm_div;                    /* 0x7e07 */
 552        u8 i2cm_segaddr;                /* 0x7e08 */
 553        u8 i2cm_softrstz;               /* 0x7e09 */
 554        u8 i2cm_segptr;                 /* 0x7e0a */
 555        u8 i2cm_ss_scl_hcnt_1_addr;     /* 0x7e0b */
 556        u8 i2cm_ss_scl_hcnt_0_addr;     /* 0x7e0c */
 557        u8 i2cm_ss_scl_lcnt_1_addr;     /* 0x7e0d */
 558        u8 i2cm_ss_scl_lcnt_0_addr;     /* 0x7e0e */
 559        u8 i2cm_fs_scl_hcnt_1_addr;     /* 0x7e0f */
 560        u8 i2cm_fs_scl_hcnt_0_addr;     /* 0x7e10 */
 561        u8 i2cm_fs_scl_lcnt_1_addr;     /* 0x7e11 */
 562        u8 i2cm_fs_scl_lcnt_0_addr;     /* 0x7e12 */
 563        u8 reserved27[0x1ed];
 564        /* Random Number Generator Registers (RNG) */
 565        u8 rng_base;                    /* 0x8000 */
 566};
 567
 568/*
 569 * Register field definitions
 570 */
 571enum {
 572/* IH_FC_INT2 field values */
 573        HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03,
 574        HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
 575        HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
 576
 577/* IH_FC_STAT2 field values */
 578        HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03,
 579        HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
 580        HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
 581
 582/* IH_PHY_STAT0 field values */
 583        HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
 584        HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
 585        HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
 586        HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
 587        HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
 588        HDMI_IH_PHY_STAT0_HPD = 0x1,
 589
 590/* IH_MUTE_I2CMPHY_STAT0 field values */
 591        HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
 592        HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
 593
 594/* IH_AHBDMAAUD_STAT0 field values */
 595        HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
 596        HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
 597        HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
 598        HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
 599        HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
 600        HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
 601
 602/* IH_MUTE_FC_STAT2 field values */
 603        HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03,
 604        HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
 605        HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
 606
 607/* IH_MUTE_AHBDMAAUD_STAT0 field values */
 608        HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
 609        HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
 610        HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
 611        HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
 612        HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
 613        HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
 614
 615/* IH_MUTE field values */
 616        HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
 617        HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
 618
 619/* TX_INVID0 field values */
 620        HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
 621        HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
 622        HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
 623        HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
 624        HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
 625
 626/* TX_INSTUFFING field values */
 627        HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
 628        HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
 629        HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
 630        HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
 631        HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
 632        HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
 633        HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
 634        HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
 635        HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
 636
 637/* VP_PR_CD field values */
 638        HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
 639        HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
 640        HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
 641        HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
 642
 643/* VP_STUFF field values */
 644        HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
 645        HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
 646        HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
 647        HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
 648        HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
 649        HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
 650        HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
 651        HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
 652        HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
 653        HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
 654        HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
 655        HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
 656        HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
 657        HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
 658        HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
 659
 660/* VP_CONF field values */
 661        HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
 662        HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
 663        HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
 664        HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
 665        HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
 666        HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
 667        HDMI_VP_CONF_PR_EN_MASK = 0x10,
 668        HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
 669        HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
 670        HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
 671        HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
 672        HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
 673        HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
 674        HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
 675        HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
 676        HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
 677        HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
 678        HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
 679        HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
 680
 681/* VP_REMAP field values */
 682        HDMI_VP_REMAP_MASK = 0x3,
 683        HDMI_VP_REMAP_YCC422_24bit = 0x2,
 684        HDMI_VP_REMAP_YCC422_20bit = 0x1,
 685        HDMI_VP_REMAP_YCC422_16bit = 0x0,
 686
 687/* FC_INVIDCONF field values */
 688        HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
 689        HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
 690        HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
 691        HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
 692        HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
 693        HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
 694        HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
 695        HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
 696        HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
 697        HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
 698        HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
 699        HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
 700        HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
 701        HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
 702        HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
 703        HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
 704        HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
 705        HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
 706        HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
 707        HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
 708        HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
 709
 710/* FC_AUDICONF0 field values */
 711        HDMI_FC_AUDICONF0_CC_OFFSET = 4,
 712        HDMI_FC_AUDICONF0_CC_MASK = 0x70,
 713        HDMI_FC_AUDICONF0_CT_OFFSET = 0,
 714        HDMI_FC_AUDICONF0_CT_MASK = 0xF,
 715
 716/* FC_AUDICONF1 field values */
 717        HDMI_FC_AUDICONF1_SS_OFFSET = 3,
 718        HDMI_FC_AUDICONF1_SS_MASK = 0x18,
 719        HDMI_FC_AUDICONF1_SF_OFFSET = 0,
 720        HDMI_FC_AUDICONF1_SF_MASK = 0x7,
 721
 722/* FC_AUDICONF3 field values */
 723        HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
 724        HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
 725        HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
 726        HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
 727        HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
 728        HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
 729
 730/* FC_AUDSCHNLS0 field values */
 731        HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
 732        HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
 733        HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
 734        HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
 735
 736/* FC_AUDSCHNLS3-6 field values */
 737        HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
 738        HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
 739        HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
 740        HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
 741        HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
 742        HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
 743        HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
 744        HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
 745
 746        HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
 747        HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
 748        HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
 749        HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
 750        HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
 751        HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
 752        HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
 753        HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
 754
 755/* HDMI_FC_AUDSCHNLS7 field values */
 756        HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
 757        HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
 758
 759/* HDMI_FC_AUDSCHNLS8 field values */
 760        HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
 761        HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
 762        HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
 763        HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
 764
 765/* FC_AUDSCONF field values */
 766        HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
 767        HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
 768        HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
 769        HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
 770        HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
 771        HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
 772
 773/* FC_STAT2 field values */
 774        HDMI_FC_STAT2_OVERFLOW_MASK = 0x03,
 775        HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
 776        HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
 777
 778/* FC_INT2 field values */
 779        HDMI_FC_INT2_OVERFLOW_MASK = 0x03,
 780        HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
 781        HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
 782
 783/* FC_MASK2 field values */
 784        HDMI_FC_MASK2_OVERFLOW_MASK = 0x03,
 785        HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02,
 786        HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01,
 787
 788/* FC_PRCONF field values */
 789        HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
 790        HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
 791        HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
 792        HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
 793
 794/* FC_AVICONF0-FC_AVICONF3 field values */
 795        HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
 796        HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
 797        HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
 798        HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
 799        HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
 800        HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
 801        HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
 802        HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
 803        HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
 804        HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
 805        HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
 806        HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C,
 807        HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
 808        HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
 809        HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
 810        HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
 811
 812        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
 813        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
 814        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
 815        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
 816        HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
 817        HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
 818        HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
 819        HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
 820        HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
 821        HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
 822        HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
 823        HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
 824        HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
 825        HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
 826
 827        HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
 828        HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
 829        HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
 830        HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
 831        HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
 832        HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
 833        HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
 834        HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
 835        HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
 836        HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
 837        HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
 838        HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
 839        HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
 840        HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
 841        HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
 842        HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
 843        HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
 844        HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
 845
 846        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
 847        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
 848        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
 849        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
 850        HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
 851        HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
 852        HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
 853        HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
 854
 855/* FC_DBGFORCE field values */
 856        HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
 857        HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
 858
 859/* PHY_CONF0 field values */
 860        HDMI_PHY_CONF0_PDZ_MASK = 0x80,
 861        HDMI_PHY_CONF0_PDZ_OFFSET = 7,
 862        HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
 863        HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
 864        HDMI_PHY_CONF0_SPARECTRL = 0x20,
 865        HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
 866        HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
 867        HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
 868        HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
 869        HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4,
 870        HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2,
 871        HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
 872        HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
 873        HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
 874        HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
 875
 876/* PHY_TST0 field values */
 877        HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
 878        HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
 879        HDMI_PHY_TST0_TSTEN_MASK = 0x10,
 880        HDMI_PHY_TST0_TSTEN_OFFSET = 4,
 881        HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
 882        HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
 883
 884/* PHY_STAT0 field values */
 885        HDMI_PHY_RX_SENSE3 = 0x80,
 886        HDMI_PHY_RX_SENSE2 = 0x40,
 887        HDMI_PHY_RX_SENSE1 = 0x20,
 888        HDMI_PHY_RX_SENSE0 = 0x10,
 889        HDMI_PHY_HPD = 0x02,
 890        HDMI_PHY_TX_PHY_LOCK = 0x01,
 891
 892/* Convenience macro RX_SENSE | HPD */
 893        HDMI_DVI_STAT = 0xF2,
 894
 895/* PHY_I2CM_SLAVE_ADDR field values */
 896        HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
 897        HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
 898
 899/* PHY_I2CM_OPERATION_ADDR field values */
 900        HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
 901        HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
 902
 903/* HDMI_PHY_I2CM_INT_ADDR */
 904        HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
 905        HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04,
 906
 907/* HDMI_PHY_I2CM_CTLINT_ADDR */
 908        HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
 909        HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40,
 910        HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
 911        HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04,
 912
 913/* AUD_CTS3 field values */
 914        HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
 915        HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
 916        HDMI_AUD_CTS3_N_SHIFT_1 = 0,
 917        HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
 918        HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
 919        HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
 920        HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
 921        HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
 922        /* note that the CTS3 MANUAL bit has been removed
 923           from our part. Can't set it, will read as 0. */
 924        HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
 925        HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
 926
 927/* AHB_DMA_CONF0 field values */
 928        HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
 929        HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
 930        HDMI_AHB_DMA_CONF0_HBR = 0x10,
 931        HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
 932        HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
 933        HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
 934        HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
 935        HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
 936        HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
 937        HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
 938        HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
 939
 940/* HDMI_AHB_DMA_START field values */
 941        HDMI_AHB_DMA_START_START_OFFSET = 0,
 942        HDMI_AHB_DMA_START_START_MASK = 0x01,
 943
 944/* HDMI_AHB_DMA_STOP field values */
 945        HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
 946        HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
 947
 948/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
 949        HDMI_AHB_DMA_DONE = 0x80,
 950        HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
 951        HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
 952        HDMI_AHB_DMA_ERROR = 0x10,
 953        HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
 954        HDMI_AHB_DMA_FIFO_FULL = 0x02,
 955        HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
 956
 957/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT, AHB_DMA_BUFFMASK, AHB_DMA_BUFFPOL field values */
 958        HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
 959        HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
 960
 961/* MC_CLKDIS field values */
 962        HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
 963        HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
 964        HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
 965        HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
 966        HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
 967        HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
 968        HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
 969
 970/* MC_SWRSTZ field values */
 971        HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
 972
 973/* MC_FLOWCTRL field values */
 974        HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
 975        HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
 976        HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
 977
 978/* MC_PHYRSTZ field values */
 979        HDMI_MC_PHYRSTZ_ASSERT = 0x0,
 980        HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
 981
 982/* MC_HEACPHY_RST field values */
 983        HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
 984        HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
 985
 986/* CSC_CFG field values */
 987        HDMI_CSC_CFG_INTMODE_MASK = 0x30,
 988        HDMI_CSC_CFG_INTMODE_OFFSET = 4,
 989        HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
 990        HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
 991        HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
 992        HDMI_CSC_CFG_DECMODE_MASK = 0x3,
 993        HDMI_CSC_CFG_DECMODE_OFFSET = 0,
 994        HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
 995        HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
 996        HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
 997        HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
 998
 999/* CSC_SCALE field values */
1000        HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,

1001        HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
1002        HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
1003        HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
1004        HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
1005        HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
1006
1007/* A_HDCPCFG0 field values */
1008        HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80,
1009        HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80,
1010        HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00,
1011        HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40,
1012        HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40,
1013        HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00,
1014        HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20,
1015        HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20,
1016        HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00,
1017        HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10,
1018        HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10,
1019        HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00,
1020        HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8,
1021        HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8,
1022        HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0,
1023        HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4,
1024        HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4,
1025        HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0,
1026        HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2,
1027        HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2,
1028        HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0,
1029        HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1,
1030        HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1,
1031        HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0,
1032
1033/* A_HDCPCFG1 field values */
1034        HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8,
1035        HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8,
1036        HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0,
1037        HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4,
1038        HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4,
1039        HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0,
1040        HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2,
1041        HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2,
1042        HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0,
1043        HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1,
1044        HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0,
1045
1046/* A_VIDPOLCFG field values */
1047        HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60,
1048        HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5,
1049        HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10,
1050        HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10,
1051        HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0,
1052        HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8,
1053        HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8,
1054        HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0,
1055        HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2,
1056        HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2,
1057        HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
1058};
1059
1060#endif /* __MXC_HDMI_H__ */
1061