LXR uboot/arch/arm/mach-sunxi/dram_sun8i

   1/*
   2 * Sun8i platform dram controller init.
   3 *
   4 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9/*
  10 * Note this code uses a lot of magic hex values, that is because this code
  11 * simply replays the init sequence as done by the Allwinner boot0 code, so
  12 * we do not know what these values mean. There are no symbolic constants for
  13 * these magic values, since we do not know how to name them and making up
  14 * names for them is not useful.
  15 *
  16 * The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one
  17 * found in the TI Keystone2 documentation:
  18 * http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf
  19 * "Table4-2 DDR3 PHY Registers"
  20 * This may be used as a (possible) reference for future work / cleanups.
  21 */
  22
  23#include <common.h>
  24#include <errno.h>
  25#include <asm/io.h>
  26#include <asm/arch/clock.h>
  27#include <asm/arch/dram.h>
  28#include <asm/arch/prcm.h>
  29
  30static const struct dram_para dram_para = {
  31        .clock = CONFIG_DRAM_CLK,
  32        .type = 3,
  33        .zq = CONFIG_DRAM_ZQ,
  34        .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN),
  35        .odt_correction = CONFIG_DRAM_ODT_CORRECTION,
  36        .para1 = 0, /* not used (only used when tpr13 bit 31 is set */
  37        .para2 = 0, /* not used (only used when tpr13 bit 31 is set */
  38        .mr0 = 6736,
  39        .mr1 = 4,
  40        .mr2 = 16,
  41        .mr3 = 0,
  42        /* tpr0 - 10 contain timing constants or-ed together in u32 vals */
  43        .tpr0 = 0x2ab83def,
  44        .tpr1 = 0x18082356,
  45        .tpr2 = 0x00034156,
  46        .tpr3 = 0x448c5533,
  47        .tpr4 = 0x08010d00,
  48        .tpr5 = 0x0340b20f,
  49        .tpr6 = 0x20d118cc,
  50        .tpr7 = 0x14062485,
  51        .tpr8 = 0x220d1d52,
  52        .tpr9 = 0x1e078c22,
  53        .tpr10 = 0x3c,
  54        .tpr11 = 0, /* not used */
  55        .tpr12 = 0, /* not used */
  56        .tpr13 = 0x30000,
  57};
  58
  59static void mctl_sys_init(void)
  60{
  61        struct sunxi_ccm_reg * const ccm =
  62                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  63
  64        /* enable pll5, note the divide by 2 is deliberate! */
  65        clock_set_pll5(dram_para.clock * 1000000 / 2,
  66                       dram_para.tpr13 & 0x40000);
  67
  68        /* deassert ahb mctl reset */
  69        setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
  70
  71        /* enable ahb mctl clock */
  72        setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
  73}
  74
  75static void mctl_apply_odt_correction(u32 *reg, int correction)
  76{
  77        int val;
  78
  79        val = (readl(reg) >> 8) & 0xff;
  80        val += correction;
  81
  82        /* clamp */
  83        if (val < 0)
  84                val = 0;
  85        else if (val > 255)
  86                val = 255;
  87
  88        clrsetbits_le32(reg, 0xff00, val << 8);
  89}
  90
  91static void mctl_init(u32 *bus_width)
  92{
  93        struct sunxi_ccm_reg * const ccm =
  94                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  95        struct sunxi_mctl_com_reg * const mctl_com =
  96                (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  97        struct sunxi_mctl_ctl_reg * const mctl_ctl =
  98                (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  99        struct sunxi_mctl_phy_reg * const mctl_phy =
 100                (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
 101
 102        if (dram_para.tpr13 & 0x20)
 103                writel(0x40b, &mctl_phy->dcr);
 104        else
 105                writel(0x1000040b, &mctl_phy->dcr);
 106
 107        if (dram_para.clock >= 480)
 108                writel(0x5c000, &mctl_phy->dllgcr);
 109        else
 110                writel(0xdc000, &mctl_phy->dllgcr);
 111
 112        writel(0x0a003e3f, &mctl_phy->pgcr0);
 113        writel(0x03008421, &mctl_phy->pgcr1);
 114
 115        writel(dram_para.mr0, &mctl_phy->mr0);
 116        writel(dram_para.mr1, &mctl_phy->mr1);
 117        writel(dram_para.mr2, &mctl_phy->mr2);
 118        writel(dram_para.mr3, &mctl_phy->mr3);
 119
 120        if (!(dram_para.tpr13 & 0x10000)) {
 121                clrsetbits_le32(&mctl_phy->dx0gcr, 0x3800, 0x2000);
 122                clrsetbits_le32(&mctl_phy->dx1gcr, 0x3800, 0x2000);
 123        }
 124
 125        /*
 126         * All the masking and shifting below converts what I assume are DDR
 127         * timing constants from Allwinner dram_para tpr format to the actual
 128         * timing registers format.
 129         */
 130
 131        writel((dram_para.tpr0 & 0x000fffff), &mctl_phy->ptr2);
 132        writel((dram_para.tpr1 & 0x1fffffff), &mctl_phy->ptr3);
 133        writel((dram_para.tpr0 & 0x3ff00000) >> 2 |
 134               (dram_para.tpr2 & 0x0003ffff), &mctl_phy->ptr4);
 135
 136        writel(dram_para.tpr3, &mctl_phy->dtpr0);
 137        writel(dram_para.tpr4, &mctl_phy->dtpr2);
 138
 139        writel(0x01000081, &mctl_phy->dtcr);
 140
 141        if (dram_para.clock <= 240 || !dram_para.odt_en) {
 142                clrbits_le32(&mctl_phy->dx0gcr, 0x600);
 143                clrbits_le32(&mctl_phy->dx1gcr, 0x600);
 144        }
 145        if (dram_para.clock <= 240) {
 146                writel(0, &mctl_phy->odtcr);
 147                writel(0, &mctl_ctl->odtmap);
 148        }
 149
 150        writel(((dram_para.tpr5 & 0x0f00) << 12) |
 151               ((dram_para.tpr5 & 0x00f8) <<  9) |
 152               ((dram_para.tpr5 & 0x0007) <<  8),
 153               &mctl_ctl->rfshctl0);
 154
 155        writel(((dram_para.tpr5 & 0x0003f000) << 12) |
 156               ((dram_para.tpr5 & 0x00fc0000) >>  2) |
 157               ((dram_para.tpr5 & 0x3f000000) >> 16) |
 158               ((dram_para.tpr6 & 0x0000003f) >>  0),
 159               &mctl_ctl->dramtmg0);
 160
 161        writel(((dram_para.tpr6 & 0x000007c0) << 10) |
 162               ((dram_para.tpr6 & 0x0000f800) >> 3) |
 163               ((dram_para.tpr6 & 0x003f0000) >> 16),
 164               &mctl_ctl->dramtmg1);
 165
 166        writel(((dram_para.tpr6 & 0x0fc00000) << 2) |
 167               ((dram_para.tpr7 & 0x0000001f) << 16) |
 168               ((dram_para.tpr7 & 0x000003e0) << 3) |
 169               ((dram_para.tpr7 & 0x0000fc00) >> 10),
 170               &mctl_ctl->dramtmg2);
 171
 172        writel(((dram_para.tpr7 & 0x03ff0000) >> 16) |
 173               ((dram_para.tpr6 & 0xf0000000) >> 16),
 174               &mctl_ctl->dramtmg3);
 175
 176        writel(((dram_para.tpr7 & 0x3c000000) >> 2 ) |
 177               ((dram_para.tpr8 & 0x00000007) << 16) |
 178               ((dram_para.tpr8 & 0x00000038) << 5) |
 179               ((dram_para.tpr8 & 0x000003c0) >> 6),
 180               &mctl_ctl->dramtmg4);
 181
 182        writel(((dram_para.tpr8 & 0x00003c00) << 14) |
 183               ((dram_para.tpr8 & 0x0003c000) <<  2) |
 184               ((dram_para.tpr8 & 0x00fc0000) >> 10) |
 185               ((dram_para.tpr8 & 0x0f000000) >> 24),
 186               &mctl_ctl->dramtmg5);
 187
 188        writel(0x00000008, &mctl_ctl->dramtmg8);
 189
 190        writel(((dram_para.tpr8 & 0xf0000000) >> 4) |
 191               ((dram_para.tpr9 & 0x00007c00) << 6) |
 192               ((dram_para.tpr9 & 0x000003e0) << 3) |
 193               ((dram_para.tpr9 & 0x0000001f) >> 0),
 194               &mctl_ctl->pitmg0);
 195
 196        setbits_le32(&mctl_ctl->pitmg1, 0x80000);
 197
 198        writel(((dram_para.tpr9 & 0x003f8000) << 9) | 0x2001,
 199               &mctl_ctl->sched);
 200
 201        writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3);
 202        writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4);
 203
 204        writel(0x00000000, &mctl_ctl->pimisc);
 205        writel(0x80000000, &mctl_ctl->upd0);
 206
 207        writel(((dram_para.tpr9  & 0xffc00000) >> 22) |
 208               ((dram_para.tpr10 & 0x00000fff) << 16),
 209               &mctl_ctl->rfshtmg);
 210
 211        if (dram_para.tpr13 & 0x20)
 212                writel(0x01040001, &mctl_ctl->mstr);
 213        else
 214                writel(0x01040401, &mctl_ctl->mstr);
 215
 216        if (!(dram_para.tpr13 & 0x20000)) {
 217                writel(0x00000002, &mctl_ctl->pwrctl);
 218                writel(0x00008001, &mctl_ctl->pwrtmg);
 219        }
 220
 221        writel(0x00000001, &mctl_ctl->rfshctl3);
 222        writel(0x00000001, &mctl_ctl->pimisc);
 223
 224        /* deassert dram_clk_cfg reset */
 225        setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
 226
 227        setbits_le32(&mctl_com->ccr, 0x80000);
 228
 229        /* zq stuff */
 230        writel((dram_para.zq >> 8) & 0xff, &mctl_phy->zqcr1);
 231
 232        writel(0x00000003, &mctl_phy->pir);
 233        udelay(10);
 234        mctl_await_completion(&mctl_phy->pgsr0, 0x09, 0x09);
 235
 236        writel(readl(&mctl_phy->zqsr0) | 0x10000000, &mctl_phy->zqcr2);
 237        writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
 238
 239        /* A23-v1.0 SDK uses 0xfdf3, A23-v2.0 SDK uses 0x5f3 */
 240        writel(0x000005f3, &mctl_phy->pir);
 241        udelay(10);
 242        mctl_await_completion(&mctl_phy->pgsr0, 0x03, 0x03);
 243
 244        if (readl(&mctl_phy->dx1gsr0) & 0x1000000) {
 245                *bus_width = 8;
 246                writel(0, &mctl_phy->dx1gcr);
 247                writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
 248                writel(0x5f3, &mctl_phy->pir);
 249                udelay(10000);
 250                setbits_le32(&mctl_ctl->mstr, 0x1000);
 251        } else
 252                *bus_width = 16;
 253
 254        if (dram_para.odt_correction) {
 255                mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1,
 256                                          dram_para.odt_correction);
 257                mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1,
 258                                          dram_para.odt_correction);
 259        }
 260
 261        mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01);
 262
 263        writel(0x08003e3f, &mctl_phy->pgcr0);
 264        writel(0x00000000, &mctl_ctl->rfshctl3);
 265}
 266
 267unsigned long sunxi_dram_init(void)
 268{
 269        struct sunxi_mctl_com_reg * const mctl_com =
 270                (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 271        const u32 columns = 13;
 272        u32 bus, bus_width, offset, page_size, rows;
 273
 274        mctl_sys_init();
 275        mctl_init(&bus_width);
 276
 277        if (bus_width == 16) {
 278                page_size = 8;
 279                bus = 1;
 280        } else {
 281                page_size = 7;
 282                bus = 0;
 283        }
 284
 285        if (!(dram_para.tpr13 & 0x80000000)) {
 286                /* Detect and set rows */
 287                writel(0x000310f4 | MCTL_CR_PAGE_SIZE(page_size),
 288                       &mctl_com->cr);
 289                setbits_le32(&mctl_com->swonr, 0x0003ffff);
 290                for (rows = 11; rows < 16; rows++) {
 291                        offset = 1 << (rows + columns + bus);
 292                        if (mctl_mem_matches(offset))
 293                                break;
 294                }
 295                clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
 296                                MCTL_CR_ROW(rows));
 297        } else {
 298                rows = (dram_para.para1 >> 16) & 0xff;
 299                writel(((dram_para.para2 & 0x000000f0) << 11) |
 300                       ((rows - 1) << 4) |
 301                       ((dram_para.para1 & 0x0f000000) >> 22) |
 302                       0x31000 | MCTL_CR_PAGE_SIZE(page_size),
 303                       &mctl_com->cr);
 304                setbits_le32(&mctl_com->swonr, 0x0003ffff);
 305        }
 306
 307        /* Setup DRAM master priority? If this is left out things still work */
 308        writel(0x00000008, &mctl_com->mcr0_0);
 309        writel(0x0001000d, &mctl_com->mcr1_0);
 310        writel(0x00000004, &mctl_com->mcr0_1);
 311        writel(0x00000080, &mctl_com->mcr1_1);
 312        writel(0x00000004, &mctl_com->mcr0_2);
 313        writel(0x00000019, &mctl_com->mcr1_2);
 314        writel(0x00000004, &mctl_com->mcr0_3);
 315        writel(0x00000080, &mctl_com->mcr1_3);
 316        writel(0x00000004, &mctl_com->mcr0_4);
 317        writel(0x01010040, &mctl_com->mcr1_4);
 318        writel(0x00000004, &mctl_com->mcr0_5);
 319        writel(0x0001002f, &mctl_com->mcr1_5);
 320        writel(0x00000004, &mctl_com->mcr0_6);
 321        writel(0x00010020, &mctl_com->mcr1_6);
 322        writel(0x00000004, &mctl_com->mcr0_7);
 323        writel(0x00010020, &mctl_com->mcr1_7);
 324        writel(0x00000008, &mctl_com->mcr0_8);
 325        writel(0x00000001, &mctl_com->mcr1_8);
 326        writel(0x00000008, &mctl_com->mcr0_9);
 327        writel(0x00000005, &mctl_com->mcr1_9);
 328        writel(0x00000008, &mctl_com->mcr0_10);
 329        writel(0x00000003, &mctl_com->mcr1_10);
 330        writel(0x00000008, &mctl_com->mcr0_11);
 331        writel(0x00000005, &mctl_com->mcr1_11);
 332        writel(0x00000008, &mctl_com->mcr0_12);
 333        writel(0x00000003, &mctl_com->mcr1_12);
 334        writel(0x00000008, &mctl_com->mcr0_13);
 335        writel(0x00000004, &mctl_com->mcr1_13);
 336        writel(0x00000008, &mctl_com->mcr0_14);
 337        writel(0x00000002, &mctl_com->mcr1_14);
 338        writel(0x00000008, &mctl_com->mcr0_15);
 339        writel(0x00000003, &mctl_com->mcr1_15);
 340        writel(0x00010138, &mctl_com->bwcr);
 341
 342        return 1 << (rows + columns + bus);
 343}
 344