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10#include <common.h>
11#include <linux/bug.h>
12#include <asm/io.h>
13#include <asm/arch/gp_padctrl.h>
14#include <asm/arch/mc.h>
15#include <asm/arch-tegra/ap.h>
16#include <asm/arch-tegra/clock.h>
17#include <asm/arch-tegra/fuse.h>
18#include <asm/arch-tegra/pmc.h>
19#include <asm/arch-tegra/scu.h>
20#include <asm/arch-tegra/tegra.h>
21#include <asm/arch-tegra/warmboot.h>
22
23int tegra_get_chip(void)
24{
25 int rev;
26 struct apb_misc_gp_ctlr *gp =
27 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
28
29
30
31
32
33
34 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
35 debug("%s: CHIPID is 0x%02X\n", __func__, rev);
36
37 return rev;
38}
39
40int tegra_get_sku_info(void)
41{
42 int sku_id;
43 struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
44
45 sku_id = readl(&fuse->sku_info) & 0xff;
46 debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
47
48 return sku_id;
49}
50
51int tegra_get_chip_sku(void)
52{
53 uint sku_id, chip_id;
54
55 chip_id = tegra_get_chip();
56 sku_id = tegra_get_sku_info();
57
58 switch (chip_id) {
59 case CHIPID_TEGRA20:
60 switch (sku_id) {
61 case SKU_ID_T20_7:
62 case SKU_ID_T20:
63 return TEGRA_SOC_T20;
64 case SKU_ID_T25SE:
65 case SKU_ID_AP25:
66 case SKU_ID_T25:
67 case SKU_ID_AP25E:
68 case SKU_ID_T25E:
69 return TEGRA_SOC_T25;
70 }
71 break;
72 case CHIPID_TEGRA30:
73 switch (sku_id) {
74 case SKU_ID_T33:
75 case SKU_ID_T30:
76 case SKU_ID_TM30MQS_P_A3:
77 default:
78 return TEGRA_SOC_T30;
79 }
80 break;
81 case CHIPID_TEGRA114:
82 switch (sku_id) {
83 case SKU_ID_T114_ENG:
84 case SKU_ID_T114_1:
85 default:
86 return TEGRA_SOC_T114;
87 }
88 break;
89 case CHIPID_TEGRA124:
90 switch (sku_id) {
91 case SKU_ID_T124_ENG:
92 default:
93 return TEGRA_SOC_T124;
94 }
95 break;
96 case CHIPID_TEGRA210:
97 switch (sku_id) {
98 case SKU_ID_T210_ENG:
99 default:
100 return TEGRA_SOC_T210;
101 }
102 break;
103 }
104
105
106 printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
107 __func__, chip_id, sku_id);
108 return TEGRA_SOC_UNKNOWN;
109}
110
111#ifndef CONFIG_ARM64
112static void enable_scu(void)
113{
114 struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
115 u32 reg;
116
117
118 if (tegra_get_chip() != CHIPID_TEGRA20)
119 return;
120
121
122 if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
123 return;
124
125
126 writel(0xFFFF, &scu->scu_inv_all);
127
128
129 reg = readl(&scu->scu_ctrl);
130 reg |= SCU_CTRL_ENABLE;
131 writel(reg, &scu->scu_ctrl);
132}
133
134static u32 get_odmdata(void)
135{
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141
142
143 unsigned long bct_start;
144 u32 odmdata;
145
146 bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
147 odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
148
149 return odmdata;
150}
151
152static void init_pmc_scratch(void)
153{
154 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
155 u32 odmdata;
156 int i;
157
158
159 for (i = 0; i < 23; i++)
160 writel(0, &pmc->pmc_scratch1+i);
161
162
163 odmdata = get_odmdata();
164 writel(odmdata, &pmc->pmc_scratch20);
165}
166
167#ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE
168void protect_secure_section(void)
169{
170 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
171
172
173 BUILD_BUG_ON(CONFIG_ARMV7_SECURE_BASE & 0xFFFFF);
174 BUILD_BUG_ON(CONFIG_ARMV7_SECURE_RESERVE_SIZE & 0xFFFFF);
175
176 writel(CONFIG_ARMV7_SECURE_BASE, &mc->mc_security_cfg0);
177 writel(CONFIG_ARMV7_SECURE_RESERVE_SIZE >> 20, &mc->mc_security_cfg1);
178}
179#endif
180
181#if defined(CONFIG_ARMV7_NONSEC)
182static void smmu_flush(struct mc_ctlr *mc)
183{
184 (void)readl(&mc->mc_smmu_config);
185}
186
187static void smmu_enable(void)
188{
189 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
190 u32 value;
191
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195
196
197 writel(0xffffffff, &mc->mc_smmu_translation_enable_0);
198 writel(0xffffffff, &mc->mc_smmu_translation_enable_1);
199 writel(0xffffffff, &mc->mc_smmu_translation_enable_2);
200 writel(0xffffffff, &mc->mc_smmu_translation_enable_3);
201
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206 value = readl(&mc->mc_smmu_config);
207 value |= TEGRA_MC_SMMU_CONFIG_ENABLE;
208 writel(value, &mc->mc_smmu_config);
209
210 smmu_flush(mc);
211}
212#else
213static void smmu_enable(void)
214{
215}
216#endif
217
218void s_init(void)
219{
220
221 init_pmc_scratch();
222
223 enable_scu();
224
225
226 config_cache();
227
228
229 smmu_enable();
230}
231#endif
232