LXR uboot/arch/arm/mach-uniphier/bcu/bcu-sld3.c

   1/*
   2 * Copyright (C) 2011-2014 Panasonic Corporation
   3 * Copyright (C) 2015-2016 Socionext Inc.
   4 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9#include <linux/io.h>
  10
  11#include "../init.h"
  12#include "bcu-regs.h"
  13
  14#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
  15
  16void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd)
  17{
  18        int shift;
  19
  20        writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
  21        writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
  22        writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
  23        /*
  24         * 0xe0000000-0xefffffff: Ex-bus
  25         * 0xf0000000-0xfbffffff: ASM bus
  26         * 0xfc000000-0xffffffff: OCM bus
  27         */
  28        writel(0x24440000, BCSCR5);
  29
  30        /* Specify DDR channel */
  31        shift = bd->dram_ch[0].size / 0x04000000 * 4;
  32        writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
  33
  34        shift -= 32;
  35        writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
  36
  37        shift -= 32;
  38        writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
  39}
  40