uboot/arch/arm/mach-versatile/timer.c
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   1/*
   2 * (C) Copyright 2003
   3 * Texas Instruments <www.ti.com>
   4 *
   5 * (C) Copyright 2002
   6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7 * Marius Groeger <mgroeger@sysgo.de>
   8 *
   9 * (C) Copyright 2002
  10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  11 * Alex Zuepke <azu@sysgo.de>
  12 *
  13 * (C) Copyright 2002-2004
  14 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  15 *
  16 * (C) Copyright 2004
  17 * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
  18 *
  19 * SPDX-License-Identifier:     GPL-2.0+
  20 */
  21
  22#include <common.h>
  23
  24#define TIMER_ENABLE    (1 << 7)
  25#define TIMER_MODE_MSK  (1 << 6)
  26#define TIMER_MODE_FR   (0 << 6)
  27#define TIMER_MODE_PD   (1 << 6)
  28
  29#define TIMER_INT_EN    (1 << 5)
  30#define TIMER_PRS_MSK   (3 << 2)
  31#define TIMER_PRS_8S    (1 << 3)
  32#define TIMER_SIZE_MSK  (1 << 2)
  33#define TIMER_ONE_SHT   (1 << 0)
  34
  35int timer_init (void)
  36{
  37        ulong   tmr_ctrl_val;
  38
  39        /* 1st disable the Timer */
  40        tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
  41        tmr_ctrl_val &= ~TIMER_ENABLE;
  42        *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
  43
  44        /*
  45         * The Timer Control Register has one Undefined/Shouldn't Use Bit
  46         * So we should do read/modify/write Operation
  47         */
  48
  49        /*
  50         * Timer Mode : Free Running
  51         * Interrupt : Disabled
  52         * Prescale : 8 Stage, Clk/256
  53         * Tmr Siz : 16 Bit Counter
  54         * Tmr in Wrapping Mode
  55         */
  56        tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
  57        tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
  58        tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
  59
  60        *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
  61
  62        return 0;
  63}
  64
  65