LXR uboot/arch/powerpc/cpu/mpc83xx/spl

   1/*
   2 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <mpc83xx.h>
   9
  10DECLARE_GLOBAL_DATA_PTR;
  11
  12/*
  13 * Breathe some life into the CPU...
  14 *
  15 * Set up the memory map,
  16 * initialize a bunch of registers,
  17 * initialize the UPM's
  18 */
  19void cpu_init_f (volatile immap_t * im)
  20{
  21        /* Pointer is writable since we allocated a register for it */
  22        gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  23
  24        /* global data region was cleared in start.S */
  25
  26        /* system performance tweaking */
  27
  28#ifdef CONFIG_SYS_ACR_PIPE_DEP
  29        /* Arbiter pipeline depth */
  30        im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
  31                          (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
  32#endif
  33
  34#ifdef CONFIG_SYS_ACR_RPTCNT
  35        /* Arbiter repeat count */
  36        im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
  37                          (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
  38#endif
  39
  40#ifdef CONFIG_SYS_SPCR_OPT
  41        /* Optimize transactions between CSB and other devices */
  42        im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
  43                           (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
  44#endif
  45
  46        /* Enable Time Base & Decrementer (so we will have udelay()) */
  47        im->sysconf.spcr |= SPCR_TBEN;
  48
  49        /* DDR control driver register */
  50#ifdef CONFIG_SYS_DDRCDR
  51        im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
  52#endif
  53        /* Output buffer impedance register */
  54#ifdef CONFIG_SYS_OBIR
  55        im->sysconf.obir = CONFIG_SYS_OBIR;
  56#endif
  57
  58        /*
  59         * Memory Controller:
  60         */
  61
  62        /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
  63         * addresses - these have to be modified later when FLASH size
  64         * has been determined
  65         */
  66
  67#if defined(CONFIG_SYS_NAND_BR_PRELIM)  \
  68        && defined(CONFIG_SYS_NAND_OR_PRELIM) \
  69        && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
  70        && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
  71        set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
  72        set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
  73        im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
  74        im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
  75#else
  76#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
  77#endif
  78}
  79
  80/*
  81 * Get timebase clock frequency (like cpu_clk in Hz)
  82 */
  83unsigned long get_tbclk(void)
  84{
  85        return (gd->bus_clk + 3L) / 4L;
  86}
  87
  88void puts(const char *str)
  89{
  90        while (*str)
  91                putc(*str++);
  92}
  93