1/* 2 * MPC8xx Internal Memory Map 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * The I/O on the MPC860 is comprised of blocks of special registers 6 * and the dual port ram for the Communication Processor Module. 7 * Within this space are functional units such as the SIU, memory 8 * controller, system timers, and other control functions. It is 9 * a combination that I found difficult to separate into logical 10 * functional files.....but anyone else is welcome to try. -- Dan 11 */ 12#ifndef __IMMAP_8XX__ 13#define __IMMAP_8XX__ 14 15/* System configuration registers. 16*/ 17typedef struct sys_conf { 18 uint sc_siumcr; 19 uint sc_sypcr; 20 uint sc_swt; 21 char res1[2]; 22 ushort sc_swsr; 23 uint sc_sipend; 24 uint sc_simask; 25 uint sc_siel; 26 uint sc_sivec; 27 uint sc_tesr; 28 char res2[0xc]; 29 uint sc_sdcr; 30 char res3[0x4c]; 31} sysconf8xx_t; 32 33/* PCMCIA configuration registers. 34*/ 35typedef struct pcmcia_conf { 36 uint pcmc_pbr0; 37 uint pcmc_por0; 38 uint pcmc_pbr1; 39 uint pcmc_por1; 40 uint pcmc_pbr2; 41 uint pcmc_por2; 42 uint pcmc_pbr3; 43 uint pcmc_por3; 44 uint pcmc_pbr4; 45 uint pcmc_por4; 46 uint pcmc_pbr5; 47 uint pcmc_por5; 48 uint pcmc_pbr6; 49 uint pcmc_por6; 50 uint pcmc_pbr7; 51 uint pcmc_por7; 52 char res1[0x20]; 53 uint pcmc_pgcra; 54 uint pcmc_pgcrb; 55 uint pcmc_pscr; 56 char res2[4]; 57 uint pcmc_pipr; 58 char res3[4]; 59 uint pcmc_per; 60 char res4[4]; 61} pcmconf8xx_t; 62 63/* Memory controller registers. 64*/ 65typedef struct mem_ctlr { 66 uint memc_br0; 67 uint memc_or0; 68 uint memc_br1; 69 uint memc_or1; 70 uint memc_br2; 71 uint memc_or2; 72 uint memc_br3; 73 uint memc_or3; 74 uint memc_br4; 75 uint memc_or4; 76 uint memc_br5; 77 uint memc_or5; 78 uint memc_br6; 79 uint memc_or6; 80 uint memc_br7; 81 uint memc_or7; 82 char res1[0x24]; 83 uint memc_mar; 84 uint memc_mcr; 85 char res2[4]; 86 uint memc_mamr; 87 uint memc_mbmr; 88 ushort memc_mstat; 89 ushort memc_mptpr; 90 uint memc_mdr; 91 char res3[0x80]; 92} memctl8xx_t; 93 94/* System Integration Timers. 95*/ 96typedef struct sys_int_timers { 97 ushort sit_tbscr; 98 char res0[0x02]; 99 uint sit_tbreff0; 100 uint sit_tbreff1; 101 char res1[0x14]; 102 ushort sit_rtcsc; 103 char res2[0x02]; 104 uint sit_rtc; 105 uint sit_rtsec; 106 uint sit_rtcal; 107 char res3[0x10]; 108 ushort sit_piscr; 109 char res4[2]; 110 uint sit_pitc; 111 uint sit_pitr; 112 char res5[0x34]; 113} sit8xx_t; 114 115#define TBSCR_TBIRQ_MASK ((ushort)0xff00) 116#define TBSCR_REFA ((ushort)0x0080) 117#define TBSCR_REFB ((ushort)0x0040) 118#define TBSCR_REFAE ((ushort)0x0008) 119#define TBSCR_REFBE ((ushort)0x0004) 120#define TBSCR_TBF ((ushort)0x0002) 121#define TBSCR_TBE ((ushort)0x0001) 122 123#define RTCSC_RTCIRQ_MASK ((ushort)0xff00) 124#define RTCSC_SEC ((ushort)0x0080) 125#define RTCSC_ALR ((ushort)0x0040) 126#define RTCSC_38K ((ushort)0x0010) 127#define RTCSC_SIE ((ushort)0x0008) 128#define RTCSC_ALE ((ushort)0x0004) 129#define RTCSC_RTF ((ushort)0x0002) 130#define RTCSC_RTE ((ushort)0x0001) 131 132#define PISCR_PIRQ_MASK ((ushort)0xff00) 133#define PISCR_PS ((ushort)0x0080) 134#define PISCR_PIE ((ushort)0x0004) 135#define PISCR_PTF ((ushort)0x0002) 136#define PISCR_PTE ((ushort)0x0001) 137 138/* Clocks and Reset. 139*/ 140typedef struct clk_and_reset { 141 uint car_sccr; 142 uint car_plprcr; 143 uint car_rsr; 144 char res[0x74]; /* Reserved area */ 145} car8xx_t; 146 147/* System Integration Timers keys. 148*/ 149typedef struct sitk { 150 uint sitk_tbscrk; 151 uint sitk_tbreff0k; 152 uint sitk_tbreff1k; 153 uint sitk_tbk; 154 char res1[0x10]; 155 uint sitk_rtcsck; 156 uint sitk_rtck; 157 uint sitk_rtseck; 158 uint sitk_rtcalk; 159 char res2[0x10]; 160 uint sitk_piscrk; 161 uint sitk_pitck; 162 char res3[0x38]; 163} sitk8xx_t; 164 165/* Clocks and reset keys. 166*/ 167typedef struct cark { 168 uint cark_sccrk; 169 uint cark_plprcrk; 170 uint cark_rsrk; 171 char res[0x474]; 172} cark8xx_t; 173 174/* The key to unlock registers maintained by keep-alive power. 175*/ 176#define KAPWR_KEY ((unsigned int)0x55ccaa33) 177 178/* Video interface. MPC823 Only. 179*/ 180typedef struct vid823 { 181 ushort vid_vccr; 182 ushort res1; 183 u_char vid_vsr; 184 u_char res2; 185 u_char vid_vcmr; 186 u_char res3; 187 uint vid_vbcb; 188 uint res4; 189 uint vid_vfcr0; 190 uint vid_vfaa0; 191 uint vid_vfba0; 192 uint vid_vfcr1; 193 uint vid_vfaa1; 194 uint vid_vfba1; 195 u_char res5[0x18]; 196} vid823_t; 197 198/* LCD interface. 823 Only. 199*/ 200typedef struct lcd { 201 uint lcd_lccr; 202 uint lcd_lchcr; 203 uint lcd_lcvcr; 204 char res1[4]; 205 uint lcd_lcfaa; 206 uint lcd_lcfba; 207 char lcd_lcsr; 208 char res2[0x7]; 209} lcd823_t; 210 211/* I2C 212*/ 213typedef struct i2c { 214 u_char i2c_i2mod; 215 char res1[3]; 216 u_char i2c_i2add; 217 char res2[3]; 218 u_char i2c_i2brg; 219 char res3[3]; 220 u_char i2c_i2com; 221 char res4[3]; 222 u_char i2c_i2cer; 223 char res5[3]; 224 u_char i2c_i2cmr; 225 char res6[0x8b]; 226} i2c8xx_t; 227 228/* DMA control/status registers. 229*/ 230typedef struct sdma_csr { 231 char res1[4]; 232 uint sdma_sdar; 233 u_char sdma_sdsr; 234 char res3[3]; 235 u_char sdma_sdmr; 236 char res4[3]; 237 u_char sdma_idsr1; 238 char res5[3]; 239 u_char sdma_idmr1; 240 char res6[3]; 241 u_char sdma_idsr2; 242 char res7[3]; 243 u_char sdma_idmr2; 244 char res8[0x13]; 245} sdma8xx_t; 246 247/* Communication Processor Module Interrupt Controller. 248*/ 249typedef struct cpm_ic { 250 ushort cpic_civr; 251 char res[0xe]; 252 uint cpic_cicr; 253 uint cpic_cipr; 254 uint cpic_cimr; 255 uint cpic_cisr; 256} cpic8xx_t; 257 258/* Input/Output Port control/status registers. 259*/ 260typedef struct io_port { 261 ushort iop_padir; 262 ushort iop_papar; 263 ushort iop_paodr; 264 ushort iop_padat; 265 char res1[8]; 266 ushort iop_pcdir; 267 ushort iop_pcpar; 268 ushort iop_pcso; 269 ushort iop_pcdat; 270 ushort iop_pcint; 271 char res2[6]; 272 ushort iop_pddir; 273 ushort iop_pdpar; 274 char res3[2]; 275 ushort iop_pddat; 276 uint utmode; 277 char res4[4]; 278} iop8xx_t; 279 280/* Communication Processor Module Timers 281*/ 282typedef struct cpm_timers { 283 ushort cpmt_tgcr; 284 char res1[0xe]; 285 ushort cpmt_tmr1; 286 ushort cpmt_tmr2; 287 ushort cpmt_trr1; 288 ushort cpmt_trr2; 289 ushort cpmt_tcr1; 290 ushort cpmt_tcr2; 291 ushort cpmt_tcn1; 292 ushort cpmt_tcn2; 293 ushort cpmt_tmr3; 294 ushort cpmt_tmr4; 295 ushort cpmt_trr3; 296 ushort cpmt_trr4; 297 ushort cpmt_tcr3; 298 ushort cpmt_tcr4; 299 ushort cpmt_tcn3; 300 ushort cpmt_tcn4; 301 ushort cpmt_ter1; 302 ushort cpmt_ter2; 303 ushort cpmt_ter3; 304 ushort cpmt_ter4; 305 char res2[8]; 306} cpmtimer8xx_t; 307 308/* Finally, the Communication Processor stuff..... 309*/ 310typedef struct scc { /* Serial communication channels */ 311 uint scc_gsmrl; 312 uint scc_gsmrh; 313 ushort scc_psmr; 314 char res1[2]; 315 ushort scc_todr; 316 ushort scc_dsr; 317 ushort scc_scce; 318 char res2[2]; 319 ushort scc_sccm; 320 char res3; 321 u_char scc_sccs; 322 char res4[8]; 323} scc_t; 324 325typedef struct smc { /* Serial management channels */ 326 char res1[2]; 327 ushort smc_smcmr; 328 char res2[2]; 329 u_char smc_smce; 330 char res3[3]; 331 u_char smc_smcm; 332 char res4[5]; 333} smc_t; 334 335/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but 336 * it fits within the address space. 337 */ 338 339typedef struct fec { 340 uint fec_addr_low; /* lower 32 bits of station address */ 341 ushort fec_addr_high; /* upper 16 bits of station address */ 342 ushort res1; /* reserved */ 343 uint fec_hash_table_high; /* upper 32-bits of hash table */ 344 uint fec_hash_table_low; /* lower 32-bits of hash table */ 345 uint fec_r_des_start; /* beginning of Rx descriptor ring */ 346 uint fec_x_des_start; /* beginning of Tx descriptor ring */ 347 uint fec_r_buff_size; /* Rx buffer size */ 348 uint res2[9]; /* reserved */ 349 uint fec_ecntrl; /* ethernet control register */ 350 uint fec_ievent; /* interrupt event register */ 351 uint fec_imask; /* interrupt mask register */ 352 uint fec_ivec; /* interrupt level and vector status */ 353 uint fec_r_des_active; /* Rx ring updated flag */ 354 uint fec_x_des_active; /* Tx ring updated flag */ 355 uint res3[10]; /* reserved */ 356 uint fec_mii_data; /* MII data register */ 357 uint fec_mii_speed; /* MII speed control register */ 358 uint res4[17]; /* reserved */ 359 uint fec_r_bound; /* end of RAM (read-only) */ 360 uint fec_r_fstart; /* Rx FIFO start address */ 361 uint res5[6]; /* reserved */ 362 uint fec_x_fstart; /* Tx FIFO start address */ 363 uint res6[17]; /* reserved */ 364 uint fec_fun_code; /* fec SDMA function code */ 365 uint res7[3]; /* reserved */ 366 uint fec_r_cntrl; /* Rx control register */ 367 uint fec_r_hash; /* Rx hash register */ 368 uint res8[14]; /* reserved */ 369 uint fec_x_cntrl; /* Tx control register */ 370 uint res9[0x1e]; /* reserved */ 371} fec_t; 372 373/* The FEC and LCD color map share the same address space.... 374 * I guess we will never see an 823T :-). 375 */ 376union fec_lcd { 377 fec_t fl_un_fec; 378 u_char fl_un_cmap[0x200]; 379}; 380 381typedef struct comm_proc { 382 /* General control and status registers. 383 */ 384 ushort cp_cpcr; 385 u_char res1[2]; 386 ushort cp_rccr; 387 u_char res2; 388 u_char cp_rmds; 389 u_char res3[4]; 390 ushort cp_cpmcr1; 391 ushort cp_cpmcr2; 392 ushort cp_cpmcr3; 393 ushort cp_cpmcr4; 394 u_char res4[2]; 395 ushort cp_rter; 396 u_char res5[2]; 397 ushort cp_rtmr; 398 u_char res6[0x14]; 399 400 /* Baud rate generators. 401 */ 402 uint cp_brgc1; 403 uint cp_brgc2; 404 uint cp_brgc3; 405 uint cp_brgc4; 406 407 /* Serial Communication Channels. 408 */ 409 scc_t cp_scc[4]; 410 411 /* Serial Management Channels. 412 */ 413 smc_t cp_smc[2]; 414 415 /* Serial Peripheral Interface. 416 */ 417 ushort cp_spmode; 418 u_char res7[4]; 419 u_char cp_spie; 420 u_char res8[3]; 421 u_char cp_spim; 422 u_char res9[2]; 423 u_char cp_spcom; 424 u_char res10[2]; 425 426 /* Parallel Interface Port. 427 */ 428 u_char res11[2]; 429 ushort cp_pipc; 430 u_char res12[2]; 431 ushort cp_ptpr; 432 uint cp_pbdir; 433 uint cp_pbpar; 434 u_char res13[2]; 435 ushort cp_pbodr; 436 uint cp_pbdat; 437 438 /* Port E - MPC87x/88x only. 439 */ 440 uint cp_pedir; 441 uint cp_pepar; 442 uint cp_peso; 443 uint cp_peodr; 444 uint cp_pedat; 445 446 /* Communications Processor Timing Register - 447 Contains RMII Timing for the FECs on MPC87x/88x only. 448 */ 449 uint cp_cptr; 450 451 /* Serial Interface and Time Slot Assignment. 452 */ 453 uint cp_simode; 454 u_char cp_sigmr; 455 u_char res15; 456 u_char cp_sistr; 457 u_char cp_sicmr; 458 u_char res16[4]; 459 uint cp_sicr; 460 uint cp_sirp; 461 u_char res17[0xc]; 462 463 /* 256 bytes of MPC823 video controller RAM array. 464 */ 465 u_char cp_vcram[0x100]; 466 u_char cp_siram[0x200]; 467 468 /* The fast ethernet controller is not really part of the CPM, 469 * but it resides in the address space. 470 * The LCD color map is also here. 471 */ 472 union fec_lcd fl_un; 473#define cp_fec fl_un.fl_un_fec 474#define lcd_cmap fl_un.fl_un_cmap 475 char res18[0xE00]; 476 477 /* The MPC885 family has a second FEC here */ 478 fec_t cp_fec2; 479#define cp_fec1 cp_fec /* consistency macro */ 480 481 /* Dual Ported RAM follows. 482 * There are many different formats for this memory area 483 * depending upon the devices used and options chosen. 484 * Some processors don't have all of it populated. 485 */ 486 u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */ 487 488 /* Parameter RAM */ 489 union { 490 u_char cp_dparam[0x400]; 491 u16 cp_dparam16[0x200]; 492 }; 493} cpm8xx_t; 494 495/* Internal memory map. 496*/ 497typedef struct immap { 498 sysconf8xx_t im_siu_conf; /* SIU Configuration */ 499 pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ 500 memctl8xx_t im_memctl; /* Memory Controller */ 501 sit8xx_t im_sit; /* System integration timers */ 502 car8xx_t im_clkrst; /* Clocks and reset */ 503 sitk8xx_t im_sitk; /* Sys int timer keys */ 504 cark8xx_t im_clkrstk; /* Clocks and reset keys */ 505 vid823_t im_vid; /* Video (823 only) */ 506 lcd823_t im_lcd; /* LCD (823 only) */ 507 i2c8xx_t im_i2c; /* I2C control/status */ 508 sdma8xx_t im_sdma; /* SDMA control/status */ 509 cpic8xx_t im_cpic; /* CPM Interrupt Controller */ 510 iop8xx_t im_ioport; /* IO Port control/status */ 511 cpmtimer8xx_t im_cpmtimer; /* CPM timers */ 512 cpm8xx_t im_cpm; /* Communication processor */ 513} immap_t; 514 515#endif /* __IMMAP_8XX__ */ 516