1/* LEON2 header file. LEON2 is a SOC processor. 2 * 3 * (C) Copyright 2008 4 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef __LEON2_H__ 10#define __LEON2_H__ 11 12#ifdef CONFIG_LEON2 13 14/* LEON 2 I/O register definitions */ 15#define LEON2_PREGS 0x80000000 16#define LEON2_MCFG1 0x00 17#define LEON2_MCFG2 0x04 18#define LEON2_ECTRL 0x08 19#define LEON2_FADDR 0x0C 20#define LEON2_MSTAT 0x10 21#define LEON2_CCTRL 0x14 22#define LEON2_PWDOWN 0x18 23#define LEON2_WPROT1 0x1C 24#define LEON2_WPROT2 0x20 25#define LEON2_LCONF 0x24 26#define LEON2_TCNT0 0x40 27#define LEON2_TRLD0 0x44 28#define LEON2_TCTRL0 0x48 29#define LEON2_TCNT1 0x50 30#define LEON2_TRLD1 0x54 31#define LEON2_TCTRL1 0x58 32#define LEON2_SCNT 0x60 33#define LEON2_SRLD 0x64 34#define LEON2_UART0 0x70 35#define LEON2_UDATA0 0x70 36#define LEON2_USTAT0 0x74 37#define LEON2_UCTRL0 0x78 38#define LEON2_USCAL0 0x7C 39#define LEON2_UART1 0x80 40#define LEON2_UDATA1 0x80 41#define LEON2_USTAT1 0x84 42#define LEON2_UCTRL1 0x88 43#define LEON2_USCAL1 0x8C 44#define LEON2_IMASK 0x90 45#define LEON2_IPEND 0x94 46#define LEON2_IFORCE 0x98 47#define LEON2_ICLEAR 0x9C 48#define LEON2_IOREG 0xA0 49#define LEON2_IODIR 0xA4 50#define LEON2_IOICONF 0xA8 51#define LEON2_IPEND2 0xB0 52#define LEON2_IMASK2 0xB4 53#define LEON2_ISTAT2 0xB8 54#define LEON2_ICLEAR2 0xBC 55 56#ifndef __ASSEMBLER__ 57/* 58 * Structure for LEON memory mapped registers. 59 * 60 * Source: Section 6.1 - On-chip registers 61 * 62 * NOTE: There is only one of these structures per CPU, its base address 63 * is 0x80000000, and the variable LEON_REG is placed there by the 64 * linkcmds file. 65 */ 66typedef struct { 67 volatile unsigned int Memory_Config_1; 68 volatile unsigned int Memory_Config_2; 69 volatile unsigned int Edac_Control; 70 volatile unsigned int Failed_Address; 71 volatile unsigned int Memory_Status; 72 volatile unsigned int Cache_Control; 73 volatile unsigned int Power_Down; 74 volatile unsigned int Write_Protection_1; 75 volatile unsigned int Write_Protection_2; 76 volatile unsigned int Leon_Configuration; 77 volatile unsigned int dummy2; 78 volatile unsigned int dummy3; 79 volatile unsigned int dummy4; 80 volatile unsigned int dummy5; 81 volatile unsigned int dummy6; 82 volatile unsigned int dummy7; 83 volatile unsigned int Timer_Counter_1; 84 volatile unsigned int Timer_Reload_1; 85 volatile unsigned int Timer_Control_1; 86 volatile unsigned int Watchdog; 87 volatile unsigned int Timer_Counter_2; 88 volatile unsigned int Timer_Reload_2; 89 volatile unsigned int Timer_Control_2; 90 volatile unsigned int dummy8; 91 volatile unsigned int Scaler_Counter; 92 volatile unsigned int Scaler_Reload; 93 volatile unsigned int dummy9; 94 volatile unsigned int dummy10; 95 volatile unsigned int UART_Channel_1; 96 volatile unsigned int UART_Status_1; 97 volatile unsigned int UART_Control_1; 98 volatile unsigned int UART_Scaler_1; 99 volatile unsigned int UART_Channel_2; 100 volatile unsigned int UART_Status_2; 101 volatile unsigned int UART_Control_2; 102 volatile unsigned int UART_Scaler_2; 103 volatile unsigned int Interrupt_Mask; 104 volatile unsigned int Interrupt_Pending; 105 volatile unsigned int Interrupt_Force; 106 volatile unsigned int Interrupt_Clear; 107 volatile unsigned int PIO_Data; 108 volatile unsigned int PIO_Direction; 109 volatile unsigned int PIO_Interrupt; 110} LEON2_regs; 111 112typedef struct { 113 volatile unsigned int UART_Channel; 114 volatile unsigned int UART_Status; 115 volatile unsigned int UART_Control; 116 volatile unsigned int UART_Scaler; 117} LEON2_Uart_regs; 118 119#endif 120 121/* 122 * The following constants are intended to be used ONLY in assembly 123 * language files. 124 * 125 * NOTE: The intended style of usage is to load the address of LEON REGS 126 * into a register and then use these as displacements from 127 * that register. 128 */ 129#define LEON_REG_MEMCFG1_OFFSET 0x00 130#define LEON_REG_MEMCFG2_OFFSET 0x04 131#define LEON_REG_EDACCTRL_OFFSET 0x08 132#define LEON_REG_FAILADDR_OFFSET 0x0C 133#define LEON_REG_MEMSTATUS_OFFSET 0x10 134#define LEON_REG_CACHECTRL_OFFSET 0x14 135#define LEON_REG_POWERDOWN_OFFSET 0x18 136#define LEON_REG_WRITEPROT1_OFFSET 0x1C 137#define LEON_REG_WRITEPROT2_OFFSET 0x20 138#define LEON_REG_LEONCONF_OFFSET 0x24 139#define LEON_REG_UNIMPLEMENTED_2_OFFSET 0x28 140#define LEON_REG_UNIMPLEMENTED_3_OFFSET 0x2C 141#define LEON_REG_UNIMPLEMENTED_4_OFFSET 0x30 142#define LEON_REG_UNIMPLEMENTED_5_OFFSET 0x34 143#define LEON_REG_UNIMPLEMENTED_6_OFFSET 0x38 144#define LEON_REG_UNIMPLEMENTED_7_OFFSET 0x3C 145#define LEON_REG_TIMERCNT1_OFFSET 0x40 146#define LEON_REG_TIMERLOAD1_OFFSET 0x44 147#define LEON_REG_TIMERCTRL1_OFFSET 0x48 148#define LEON_REG_WDOG_OFFSET 0x4C 149#define LEON_REG_TIMERCNT2_OFFSET 0x50 150#define LEON_REG_TIMERLOAD2_OFFSET 0x54 151#define LEON_REG_TIMERCTRL2_OFFSET 0x58 152#define LEON_REG_UNIMPLEMENTED_8_OFFSET 0x5C 153#define LEON_REG_SCALERCNT_OFFSET 0x60 154#define LEON_REG_SCALER_LOAD_OFFSET 0x64 155#define LEON_REG_UNIMPLEMENTED_9_OFFSET 0x68 156#define LEON_REG_UNIMPLEMENTED_10_OFFSET 0x6C 157#define LEON_REG_UARTDATA1_OFFSET 0x70 158#define LEON_REG_UARTSTATUS1_OFFSET 0x74 159#define LEON_REG_UARTCTRL1_OFFSET 0x78 160#define LEON_REG_UARTSCALER1_OFFSET 0x7C 161#define LEON_REG_UARTDATA2_OFFSET 0x80 162#define LEON_REG_UARTSTATUS2_OFFSET 0x84 163#define LEON_REG_UARTCTRL2_OFFSET 0x88 164#define LEON_REG_UARTSCALER2_OFFSET 0x8C 165#define LEON_REG_IRQMASK_OFFSET 0x90 166#define LEON_REG_IRQPEND_OFFSET 0x94 167#define LEON_REG_IRQFORCE_OFFSET 0x98 168#define LEON_REG_IRQCLEAR_OFFSET 0x9C 169#define LEON_REG_PIODATA_OFFSET 0xA0 170#define LEON_REG_PIODIR_OFFSET 0xA4 171#define LEON_REG_PIOIRQ_OFFSET 0xA8 172#define LEON_REG_SIM_RAM_SIZE_OFFSET 0xF4 173#define LEON_REG_SIM_ROM_SIZE_OFFSET 0xF8 174 175/* 176 * Interrupt Sources 177 * 178 * The interrupt source numbers directly map to the trap type and to 179 * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask, 180 * and the Interrupt Pending Registers. 181 */ 182#define LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR 1 183#define LEON_INTERRUPT_UART_1_RX_TX 2 184#define LEON_INTERRUPT_UART_0_RX_TX 3 185#define LEON_INTERRUPT_EXTERNAL_0 4 186#define LEON_INTERRUPT_EXTERNAL_1 5 187#define LEON_INTERRUPT_EXTERNAL_2 6 188#define LEON_INTERRUPT_EXTERNAL_3 7 189#define LEON_INTERRUPT_TIMER1 8 190#define LEON_INTERRUPT_TIMER2 9 191#define LEON_INTERRUPT_EMPTY1 10 192#define LEON_INTERRUPT_EMPTY2 11 193#define LEON_INTERRUPT_OPEN_ETH 12 194#define LEON_INTERRUPT_EMPTY4 13 195#define LEON_INTERRUPT_EMPTY5 14 196#define LEON_INTERRUPT_EMPTY6 15 197 198/* Timer Bits */ 199#define LEON2_TIMER_CTRL_EN 0x1 /* Timer enable */ 200#define LEON2_TIMER_CTRL_RS 0x2 /* Timer reStart */ 201#define LEON2_TIMER_CTRL_LD 0x4 /* Timer reLoad */ 202#define LEON2_TIMER1_IRQNO 8 /* Timer 1 IRQ number */ 203#define LEON2_TIMER2_IRQNO 9 /* Timer 2 IRQ number */ 204#define LEON2_TIMER1_IE (1<<LEON2_TIMER1_IRQNO) /* Timer 1 interrupt enable */ 205#define LEON2_TIMER2_IE (1<<LEON2_TIMER2_IRQNO) /* Timer 2 interrupt enable */ 206 207/* UART bits */ 208#define LEON2_UART_CTRL_RE 1 /* UART Receiver enable */ 209#define LEON2_UART_CTRL_TE 2 /* UART Transmitter enable */ 210#define LEON2_UART_CTRL_RI 4 /* UART Receiver Interrupt enable */ 211#define LEON2_UART_CTRL_TI 8 /* UART Transmitter Interrupt enable */ 212#define LEON2_UART_CTRL_DBG (1<<11) /* Debug Bit used by GRMON */ 213 214#define LEON2_UART_STAT_DR 1 /* UART Data Ready */ 215#define LEON2_UART_STAT_TSE 2 /* UART Transmit Shift Reg empty */ 216#define LEON2_UART_STAT_THE 4 /* UART Transmit Hold Reg empty */ 217 218#else 219#error Include LEON2 header file only if LEON2 processor 220#endif 221 222#endif 223