LXR uboot/board/atmel/atstk1000/atstk1000.c

   1/*
   2 * Copyright (C) 2005-2006 Atmel Corporation
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6#include <common.h>
   7
   8#include <asm/io.h>
   9#include <asm/sdram.h>
  10#include <asm/arch/clk.h>
  11#include <asm/arch/hmatrix.h>
  12#include <asm/arch/mmu.h>
  13#include <asm/arch/portmux.h>
  14#include <netdev.h>
  15
  16DECLARE_GLOBAL_DATA_PTR;
  17
  18struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
  19        {
  20                .virt_pgno      = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
  21                .nr_pages       = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
  22                .phys           = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
  23                                        | MMU_VMR_CACHE_NONE,
  24        }, {
  25                .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
  26                .nr_pages       = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
  27                .phys           = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
  28                                        | MMU_VMR_CACHE_WRBACK,
  29        },
  30};
  31
  32static const struct sdram_config sdram_config = {
  33        .data_bits      = SDRAM_DATA_32BIT,
  34#ifdef CONFIG_ATSTK1000_16MB_SDRAM
  35        /* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
  36        .row_bits       = 12,
  37#else
  38        /* MT48LC2M32B2P-5 (8 MB) on motherboard */
  39        .row_bits       = 11,
  40#endif
  41        .col_bits       = 8,
  42        .bank_bits      = 2,
  43        .cas            = 3,
  44        .twr            = 2,
  45        .trc            = 7,
  46        .trp            = 2,
  47        .trcd           = 2,
  48        .tras           = 5,
  49        .txsr           = 5,
  50        /* 15.6 us */
  51        .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
  52};
  53
  54int board_early_init_f(void)
  55{
  56        /* Enable SDRAM in the EBI mux */
  57        hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
  58
  59        portmux_enable_ebi(sdram_config.data_bits, 23, 0, PORTMUX_DRIVE_HIGH);
  60        sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
  61
  62        portmux_enable_usart1(PORTMUX_DRIVE_MIN);
  63
  64#if defined(CONFIG_MACB)
  65        portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
  66        portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
  67#endif
  68#if defined(CONFIG_MMC)
  69        portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
  70#endif
  71
  72        return 0;
  73}
  74
  75int board_early_init_r(void)
  76{
  77        gd->bd->bi_phy_id[0] = 0x10;
  78        gd->bd->bi_phy_id[1] = 0x11;
  79        return 0;
  80}
  81
  82#ifdef CONFIG_CMD_NET
  83int board_eth_init(bd_t *bi)
  84{
  85        macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
  86        macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
  87        return 0;
  88}
  89#endif
  90