LXR uboot/board/bosch/shc/board.c

   1/*
   2 * board.c
   3 *
   4 * (C) Copyright 2016
   5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   6 *
   7 * Based on:
   8 * Board functions for TI AM335X based boards
   9 *
  10 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  11 *
  12 * SPDX-License-Identifier:     GPL-2.0+
  13 */
  14
  15#include <common.h>
  16#include <errno.h>
  17#include <spl.h>
  18#include <asm/arch/cpu.h>
  19#include <asm/arch/hardware.h>
  20#include <asm/arch/omap.h>
  21#include <asm/arch/ddr_defs.h>
  22#include <asm/arch/clock.h>
  23#include <asm/arch/gpio.h>
  24#include <asm/arch/mmc_host_def.h>
  25#include <asm/arch/sys_proto.h>
  26#include <asm/arch/mem.h>
  27#include <asm/io.h>
  28#include <asm/emif.h>
  29#include <asm/gpio.h>
  30#include <i2c.h>
  31#include <miiphy.h>
  32#include <cpsw.h>
  33#include <power/tps65217.h>
  34#include <environment.h>
  35#include <watchdog.h>
  36#include <environment.h>
  37#include "mmc.h"
  38#include "board.h"
  39
  40DECLARE_GLOBAL_DATA_PTR;
  41
  42#if defined(CONFIG_SPL_BUILD) || \
  43        (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
  44static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  45#endif
  46static struct shc_eeprom __attribute__((section(".data"))) header;
  47static int shc_eeprom_valid;
  48
  49/*
  50 * Read header information from EEPROM into global structure.
  51 */
  52static int read_eeprom(void)
  53{
  54        /* Check if baseboard eeprom is available */
  55        if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  56                puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
  57                return -ENODEV;
  58        }
  59
  60        /* read the eeprom using i2c */
  61        if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
  62                     sizeof(header))) {
  63                puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
  64                return -EIO;
  65        }
  66
  67        if (header.magic != HDR_MAGIC) {
  68                printf("Incorrect magic number (0x%x) in EEPROM\n",
  69                       header.magic);
  70                return -EIO;
  71        }
  72
  73        shc_eeprom_valid = 1;
  74
  75        return 0;
  76}
  77
  78static void shc_request_gpio(void)
  79{
  80        gpio_request(LED_PWR_BL_GPIO, "LED PWR BL");
  81        gpio_request(LED_PWR_RD_GPIO, "LED PWR RD");
  82        gpio_request(RESET_GPIO, "reset");
  83        gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN");
  84        gpio_request(WIFI_RST_GPIO, "WIFI rst");
  85        gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst");
  86        gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst");
  87        gpio_request(ENOC_RST_GPIO, "ENOC rst");
  88#if defined CONFIG_B_SAMPLE
  89        gpio_request(LED_PWR_GN_GPIO, "LED PWR GN");
  90        gpio_request(LED_CONN_BL_GPIO, "LED CONN BL");
  91        gpio_request(LED_CONN_RD_GPIO, "LED CONN RD");
  92        gpio_request(LED_CONN_GN_GPIO, "LED CONN GN");
  93#else
  94        gpio_request(LED_LAN_BL_GPIO, "LED LAN BL");
  95        gpio_request(LED_LAN_RD_GPIO, "LED LAN RD");
  96        gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL");
  97        gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD");
  98        gpio_request(LED_PWM_GPIO, "LED PWM");
  99        gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst");
 100#endif
 101        gpio_request(BACK_BUTTON_GPIO, "Back button");
 102        gpio_request(FRONT_BUTTON_GPIO, "Front button");
 103}
 104
 105/*
 106 * Function which forces all installed modules into running state for ICT
 107 * testing. Called by SPL.
 108 */
 109static void __maybe_unused force_modules_running(void)
 110{
 111        /* Wi-Fi power regulator enable - high = enabled */
 112        gpio_direction_output(WIFI_REGEN_GPIO, 1);
 113        /*
 114         * Wait for Wi-Fi power regulator to reach a stable voltage
 115         * (soft-start time, max. 350 µs)
 116         */
 117        __udelay(350);
 118
 119        /* Wi-Fi module reset - high = running */
 120        gpio_direction_output(WIFI_RST_GPIO, 1);
 121
 122        /* ZigBee reset - high = running */
 123        gpio_direction_output(ZIGBEE_RST_GPIO, 1);
 124
 125        /* BidCos reset - high = running */
 126        gpio_direction_output(BIDCOS_RST_GPIO, 1);
 127
 128#if !defined(CONFIG_B_SAMPLE)
 129        /* Z-Wave reset - high = running */
 130        gpio_direction_output(Z_WAVE_RST_GPIO, 1);
 131#endif
 132
 133        /* EnOcean reset - low = running */
 134        gpio_direction_output(ENOC_RST_GPIO, 0);
 135}
 136
 137/*
 138 * Function which forces all installed modules into reset - to be released by
 139 * the OS, called by SPL
 140 */
 141static void __maybe_unused force_modules_reset(void)
 142{
 143        /* Wi-Fi module reset - low = reset */
 144        gpio_direction_output(WIFI_RST_GPIO, 0);
 145
 146        /* Wi-Fi power regulator enable - low = disabled */
 147        gpio_direction_output(WIFI_REGEN_GPIO, 0);
 148
 149        /* ZigBee reset - low = reset */
 150        gpio_direction_output(ZIGBEE_RST_GPIO, 0);
 151
 152        /* BidCos reset - low = reset */
 153        /*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/
 154
 155#if !defined(CONFIG_B_SAMPLE)
 156        /* Z-Wave reset - low = reset */
 157        gpio_direction_output(Z_WAVE_RST_GPIO, 0);
 158#endif
 159
 160        /* EnOcean reset - high = reset*/
 161        gpio_direction_output(ENOC_RST_GPIO, 1);
 162}
 163
 164/*
 165 * Function to set the LEDs in the state "Bootloader booting"
 166 */
 167static void __maybe_unused leds_set_booting(void)
 168{
 169#if defined(CONFIG_B_SAMPLE)
 170
 171        /* Turn all red LEDs on */
 172        gpio_direction_output(LED_PWR_RD_GPIO, 1);
 173        gpio_direction_output(LED_CONN_RD_GPIO, 1);
 174
 175#else /* All other SHCs starting with B2-Sample */
 176        /* Set the PWM GPIO */
 177        gpio_direction_output(LED_PWM_GPIO, 1);
 178        /* Turn all red LEDs on */
 179        gpio_direction_output(LED_PWR_RD_GPIO, 1);
 180        gpio_direction_output(LED_LAN_RD_GPIO, 1);
 181        gpio_direction_output(LED_CLOUD_RD_GPIO, 1);
 182
 183#endif
 184}
 185
 186/*
 187 * Function to set the LEDs in the state "Bootloader error"
 188 */
 189static void leds_set_failure(int state)
 190{
 191#if defined(CONFIG_B_SAMPLE)
 192        /* Turn all blue and green LEDs off */
 193        gpio_set_value(LED_PWR_BL_GPIO, 0);
 194        gpio_set_value(LED_PWR_GN_GPIO, 0);
 195        gpio_set_value(LED_CONN_BL_GPIO, 0);
 196        gpio_set_value(LED_CONN_GN_GPIO, 0);
 197
 198        /* Turn all red LEDs to 'state' */
 199        gpio_set_value(LED_PWR_RD_GPIO, state);
 200        gpio_set_value(LED_CONN_RD_GPIO, state);
 201
 202#else /* All other SHCs starting with B2-Sample */
 203        /* Set the PWM GPIO */
 204        gpio_direction_output(LED_PWM_GPIO, 1);
 205
 206        /* Turn all blue LEDs off */
 207        gpio_set_value(LED_PWR_BL_GPIO, 0);
 208        gpio_set_value(LED_LAN_BL_GPIO, 0);
 209        gpio_set_value(LED_CLOUD_BL_GPIO, 0);
 210
 211        /* Turn all red LEDs to 'state' */
 212        gpio_set_value(LED_PWR_RD_GPIO, state);
 213        gpio_set_value(LED_LAN_RD_GPIO, state);
 214        gpio_set_value(LED_CLOUD_RD_GPIO, state);
 215#endif
 216}
 217
 218/*
 219 * Function to set the LEDs in the state "Bootloader finished"
 220 */
 221static void leds_set_finish(void)
 222{
 223#if defined(CONFIG_B_SAMPLE)
 224        /* Turn all LEDs off */
 225        gpio_set_value(LED_PWR_BL_GPIO, 0);
 226        gpio_set_value(LED_PWR_RD_GPIO, 0);
 227        gpio_set_value(LED_PWR_GN_GPIO, 0);
 228        gpio_set_value(LED_CONN_BL_GPIO, 0);
 229        gpio_set_value(LED_CONN_RD_GPIO, 0);
 230        gpio_set_value(LED_CONN_GN_GPIO, 0);
 231#else /* All other SHCs starting with B2-Sample */
 232        /* Turn all LEDs off */
 233        gpio_set_value(LED_PWR_BL_GPIO, 0);
 234        gpio_set_value(LED_PWR_RD_GPIO, 0);
 235        gpio_set_value(LED_LAN_BL_GPIO, 0);
 236        gpio_set_value(LED_LAN_RD_GPIO, 0);
 237        gpio_set_value(LED_CLOUD_BL_GPIO, 0);
 238        gpio_set_value(LED_CLOUD_RD_GPIO, 0);
 239
 240        /* Turn off the PWM GPIO and mux it to EHRPWM */
 241        gpio_set_value(LED_PWM_GPIO, 0);
 242        enable_shc_board_pwm_pin_mux();
 243#endif
 244}
 245
 246static void check_button_status(void)
 247{
 248        ulong value;
 249        gpio_direction_input(FRONT_BUTTON_GPIO);
 250        value = gpio_get_value(FRONT_BUTTON_GPIO);
 251
 252        if (value == 0) {
 253                printf("front button activated !\n");
 254                setenv("harakiri", "1");
 255        }
 256}
 257
 258#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 259#ifdef CONFIG_SPL_OS_BOOT
 260int spl_start_uboot(void)
 261{
 262        return 1;
 263}
 264#endif
 265
 266static void shc_board_early_init(void)
 267{
 268        shc_request_gpio();
 269# ifdef CONFIG_SHC_ICT
 270        /* Force all modules into enabled state for ICT testing */
 271        force_modules_running();
 272# else
 273        /* Force all modules to enter Reset state until released by the OS */
 274        force_modules_reset();
 275# endif
 276        leds_set_booting();
 277}
 278
 279#define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */
 280#define OSC     (V_OSCK/1000000)
 281/* Bosch: Predivider must be fixed to 4, so N = 4-1 */
 282#define MPUPLL_N        (4-1)
 283/* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */
 284#define MPUPLL_FREF (OSC / (MPUPLL_N + 1))
 285
 286const struct dpll_params dpll_ddr_shc = {
 287                400, OSC-1, 1, -1, -1, -1, -1};
 288
 289const struct dpll_params *get_dpll_ddr_params(void)
 290{
 291        return &dpll_ddr_shc;
 292}
 293
 294/*
 295 * As we enabled downspread SSC with 1.8%, the values needed to be corrected
 296 * such that the 20% overshoot will not lead to too high frequencies.
 297 * In all cases, this is achieved by subtracting one from M (6 MHz less).
 298 * Example: 600 MHz CPU
 299 *   Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz
 300 *   600 MHz - 6 MHz (1x Fref) = 594 MHz
 301 *   SSC: 594 MHz * 1.8% = 10.7 MHz SSC
 302 *   Overshoot: 10.7 MHz * 20 % = 2.2 MHz
 303 *   --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK!
 304 */
 305const struct dpll_params dpll_mpu_shc_opp100 = {
 306                99, MPUPLL_N, 1, -1, -1, -1, -1};
 307
 308void am33xx_spl_board_init(void)
 309{
 310        int sil_rev;
 311        int mpu_vdd;
 312
 313        puts(BOARD_ID_STR);
 314
 315        /*
 316         * Set CORE Frequency to OPP100
 317         * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100)
 318         */
 319        do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 320
 321        sil_rev = readl(&cdev->deviceid) >> 28;
 322        if (sil_rev < 2) {
 323                puts("We do not support Silicon Revisions below 2.0!\n");
 324                return;
 325        }
 326
 327        dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 328        if (i2c_probe(TPS65217_CHIP_PM))
 329                return;
 330
 331        /*
 332         * Retrieve the CPU max frequency by reading the efuse
 333         * SHC-Default: 600 MHz
 334         */
 335        switch (dpll_mpu_opp100.m) {
 336        case MPUPLL_M_1000:
 337                mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 338                break;
 339        case MPUPLL_M_800:
 340                mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 341                break;
 342        case MPUPLL_M_720:
 343                mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
 344                break;
 345        case MPUPLL_M_600:
 346                mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
 347                break;
 348        case MPUPLL_M_300:
 349                mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV;
 350                break;
 351        default:
 352                puts("Cannot determine the frequency, failing!\n");
 353                return;
 354        }
 355
 356        if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 357                puts("tps65217_voltage_update failure\n");
 358                return;
 359        }
 360
 361        /* Set MPU Frequency to what we detected */
 362        printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF);
 363        printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF *
 364               dpll_mpu_shc_opp100.m);
 365        do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100);
 366
 367        /* Enable Spread Spectrum for this freq to be clean on EMI side */
 368        set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE);
 369
 370        /*
 371         * Using the default voltages for the PMIC (TPS65217D)
 372         * LS1 = 1.8V (VDD_1V8)
 373         * LS2 = 3.3V (VDD_3V3A)
 374         * LDO1 = 1.8V (VIO and VRTC)
 375         * LDO2 = 3.3V (VDD_3V3AUX)
 376         */
 377        shc_board_early_init();
 378}
 379
 380void set_uart_mux_conf(void)
 381{
 382        enable_uart0_pin_mux();
 383}
 384
 385void set_mux_conf_regs(void)
 386{
 387        enable_shc_board_pin_mux();
 388}
 389
 390const struct ctrl_ioregs ioregs_evmsk = {
 391        .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 392        .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 393        .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 394        .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 395        .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 396};
 397
 398static const struct ddr_data ddr3_shc_data = {
 399        .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 400        .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 401        .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 402        .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 403};
 404
 405static const struct cmd_control ddr3_shc_cmd_ctrl_data = {
 406        .cmd0csratio = MT41K256M16HA125E_RATIO,
 407        .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 408
 409        .cmd1csratio = MT41K256M16HA125E_RATIO,
 410        .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 411
 412        .cmd2csratio = MT41K256M16HA125E_RATIO,
 413        .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 414};
 415
 416static struct emif_regs ddr3_shc_emif_reg_data = {
 417        .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 418        .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 419        .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 420        .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 421        .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 422        .zq_config = MT41K256M16HA125E_ZQ_CFG,
 423        .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
 424                                PHY_EN_DYN_PWRDN,
 425};
 426
 427void sdram_init(void)
 428{
 429        /* Configure the DDR3 RAM */
 430        config_ddr(400, &ioregs_evmsk, &ddr3_shc_data,
 431                   &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0);
 432}
 433#endif
 434
 435/*
 436 * Basic board specific setup.  Pinmux has been handled already.
 437 */
 438int board_init(void)
 439{
 440#if defined(CONFIG_HW_WATCHDOG)
 441        hw_watchdog_init();
 442#endif
 443        i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 444        if (read_eeprom() < 0)
 445                puts("EEPROM Content Invalid.\n");
 446
 447        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 448#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
 449        gpmc_init();
 450#endif
 451        shc_request_gpio();
 452
 453        return 0;
 454}
 455
 456#ifdef CONFIG_BOARD_LATE_INIT
 457int board_late_init(void)
 458{
 459        check_button_status();
 460#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 461        if (shc_eeprom_valid)
 462                if (is_valid_ethaddr(header.mac_addr))
 463                        eth_setenv_enetaddr("ethaddr", header.mac_addr);
 464#endif
 465
 466        return 0;
 467}
 468#endif
 469
 470#ifndef CONFIG_DM_ETH
 471#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 472        (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 473static void cpsw_control(int enabled)
 474{
 475        /* VTP can be added here */
 476
 477        return;
 478}
 479
 480static struct cpsw_slave_data cpsw_slaves[] = {
 481        {
 482                .slave_reg_ofs  = 0x208,
 483                .sliver_reg_ofs = 0xd80,
 484                .phy_addr       = 0,
 485        },
 486        {
 487                .slave_reg_ofs  = 0x308,
 488                .sliver_reg_ofs = 0xdc0,
 489                .phy_addr       = 1,
 490        },
 491};
 492
 493static struct cpsw_platform_data cpsw_data = {
 494        .mdio_base              = CPSW_MDIO_BASE,
 495        .cpsw_base              = CPSW_BASE,
 496        .mdio_div               = 0xff,
 497        .channels               = 8,
 498        .cpdma_reg_ofs          = 0x800,
 499        .slaves                 = 1,
 500        .slave_data             = cpsw_slaves,
 501        .ale_reg_ofs            = 0xd00,
 502        .ale_entries            = 1024,
 503        .host_port_reg_ofs      = 0x108,
 504        .hw_stats_reg_ofs       = 0x900,
 505        .bd_ram_ofs             = 0x2000,
 506        .mac_control            = (1 << 5),
 507        .control                = cpsw_control,
 508        .host_port_num          = 0,
 509        .version                = CPSW_CTRL_VERSION_2,
 510};
 511#endif
 512
 513/*
 514 * This function will:
 515 * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
 516 * in the environment
 517 * Perform fixups to the PHY present on certain boards.  We only need this
 518 * function in:
 519 * - SPL with either CPSW or USB ethernet support
 520 * - Full U-Boot, with either CPSW or USB ethernet
 521 * Build in only these cases to avoid warnings about unused variables
 522 * when we build an SPL that has neither option but full U-Boot will.
 523 */
 524#if ((defined(CONFIG_SPL_ETH_SUPPORT) || \
 525        defined(CONFIG_SPL_USBETH_SUPPORT)) && \
 526        defined(CONFIG_SPL_BUILD)) || \
 527        ((defined(CONFIG_DRIVER_TI_CPSW) || \
 528          defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
 529         !defined(CONFIG_SPL_BUILD))
 530int board_eth_init(bd_t *bis)
 531{
 532        int rv, n = 0;
 533        uint8_t mac_addr[6];
 534        uint32_t mac_hi, mac_lo;
 535
 536        /* try reading mac address from efuse */
 537        mac_lo = readl(&cdev->macid0l);
 538        mac_hi = readl(&cdev->macid0h);
 539        mac_addr[0] = mac_hi & 0xFF;
 540        mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 541        mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 542        mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 543        mac_addr[4] = mac_lo & 0xFF;
 544        mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 545
 546#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 547        (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 548        if (!getenv("ethaddr")) {
 549                printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 550
 551                if (is_valid_ethaddr(mac_addr))
 552                        eth_setenv_enetaddr("ethaddr", mac_addr);
 553        }
 554
 555        writel(MII_MODE_ENABLE, &cdev->miisel);
 556        cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
 557        cpsw_slaves[1].phy_if = cpsw_slaves[0].phy_if;
 558        rv = cpsw_register(&cpsw_data);
 559        if (rv < 0)
 560                printf("Error %d registering CPSW switch\n", rv);
 561        else
 562                n += rv;
 563#endif
 564
 565#if defined(CONFIG_USB_ETHER) && \
 566        (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 567        if (is_valid_ethaddr(mac_addr))
 568                eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
 569
 570        rv = usb_eth_initialize(bis);
 571        if (rv < 0)
 572                printf("Error %d registering USB_ETHER\n", rv);
 573        else
 574                n += rv;
 575#endif
 576        return n;
 577}
 578#endif
 579
 580#endif /* CONFIG_DM_ETH */
 581
 582#ifdef CONFIG_SHOW_BOOT_PROGRESS
 583static void bosch_check_reset_pin(void)
 584{
 585        if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) {
 586                printf("Resetting ...\n");
 587                writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
 588                disable_interrupts();
 589                reset_cpu(0);
 590                /*NOTREACHED*/
 591        }
 592}
 593
 594static void hang_bosch(const char *cause, int code)
 595{
 596        int lv;
 597
 598        gpio_direction_input(RESET_GPIO);
 599
 600        /* Enable reset pin interrupt on falling edge */
 601        writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
 602        writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT);
 603        enable_interrupts();
 604
 605        puts(cause);
 606        for (;;) {
 607                for (lv = 0; lv < code; lv++) {
 608                        bosch_check_reset_pin();
 609                        leds_set_failure(1);
 610                        __udelay(150 * 1000);
 611                        leds_set_failure(0);
 612                        __udelay(150 * 1000);
 613                }
 614#if defined(BLINK_CODE)
 615                __udelay(300 * 1000);
 616#endif
 617        }
 618}
 619
 620void show_boot_progress(int val)
 621{
 622        switch (val) {
 623        case BOOTSTAGE_ID_NEED_RESET:
 624                hang_bosch("need reset", 4);
 625                break;
 626        }
 627}
 628#endif
 629
 630void arch_preboot_os(void)
 631{
 632        leds_set_finish();
 633}
 634
 635#if defined(CONFIG_GENERIC_MMC)
 636int board_mmc_init(bd_t *bis)
 637{
 638        int ret;
 639
 640        /* Bosch: Do not enable 52MHz for eMMC device to avoid EMI */
 641        ret = omap_mmc_init(0, MMC_MODE_HS_52MHz, 26000000, -1, -1);
 642        if (ret)
 643                return ret;
 644
 645        ret = omap_mmc_init(1, MMC_MODE_HS_52MHz, 26000000, -1, -1);
 646        return ret;
 647}
 648#endif
 649