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56#include <common.h>
57#include <net.h>
58#include <netdev.h>
59#include <miiphy.h>
60#include <i2c.h>
61#include <spi.h>
62#include <dataflash.h>
63#include <mmc.h>
64#include <atmel_mci.h>
65
66#include <asm/arch/at91sam9260.h>
67#include <asm/arch/at91sam9260_matrix.h>
68#include <asm/arch/at91sam9_smc.h>
69#include <asm/arch/at91_common.h>
70#include <asm/arch/at91_spi.h>
71#include <asm/arch/clk.h>
72#include <asm/arch/gpio.h>
73#include <asm/io.h>
74#include <asm/gpio.h>
75
76#include "ethernut5_pwrman.h"
77
78DECLARE_GLOBAL_DATA_PTR;
79
80AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
81
82struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
83 {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}
84};
85
86
87
88
89
90
91dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
92 { 0x00021000, 0x00041FFF, FLAG_PROTECT_SET, 0, "setup" },
93 { 0x00042000, 0x000C5FFF, FLAG_PROTECT_SET, 0, "uboot" },
94 { 0x000C6000, 0x00359FFF, FLAG_PROTECT_SET, 0, "kernel" },
95 { 0x0035A000, 0x003DDFFF, FLAG_PROTECT_SET, 0, "nutos" },
96 { 0x003DE000, 0x003FEFFF, FLAG_PROTECT_CLEAR, 0, "env" }
97};
98
99
100
101
102
103
104
105
106int dram_init(void)
107{
108 gd->ram_size = get_ram_size(
109 (void *)CONFIG_SYS_SDRAM_BASE,
110 CONFIG_SYS_SDRAM_SIZE);
111 return 0;
112}
113
114#ifdef CONFIG_CMD_NAND
115static void ethernut5_nand_hw_init(void)
116{
117 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
118 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
119 unsigned long csa;
120
121
122 csa = readl(&matrix->ebicsa);
123 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
124 writel(csa, &matrix->ebicsa);
125
126
127 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
128 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
129 &smc->cs[3].setup);
130 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
131 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
132 &smc->cs[3].pulse);
133 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
134 &smc->cs[3].cycle);
135 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
136 AT91_SMC_MODE_EXNW_DISABLE |
137 AT91_SMC_MODE_DBW_8 |
138 AT91_SMC_MODE_TDF_CYCLE(2),
139 &smc->cs[3].mode);
140
141#ifdef CONFIG_SYS_NAND_READY_PIN
142
143 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
144#endif
145 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
146}
147#endif
148
149
150
151
152int board_init(void)
153{
154 at91_periph_clk_enable(ATMEL_ID_PIOA);
155 at91_periph_clk_enable(ATMEL_ID_PIOB);
156 at91_periph_clk_enable(ATMEL_ID_PIOC);
157
158
159 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
160
161 at91_seriald_hw_init();
162 ethernut5_power_init();
163#ifdef CONFIG_CMD_NAND
164 ethernut5_nand_hw_init();
165#endif
166#ifdef CONFIG_HAS_DATAFLASH
167 at91_spi0_hw_init(1 << 0);
168#endif
169 return 0;
170}
171
172#ifdef CONFIG_MACB
173
174
175
176int board_eth_init(bd_t *bis)
177{
178 const char *devname;
179 unsigned short mode;
180
181 at91_periph_clk_enable(ATMEL_ID_EMAC0);
182
183
184 ethernut5_phy_reset();
185
186 at91_macb_hw_init();
187
188 if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID))
189 return -1;
190
191
192
193
194
195 devname = miiphy_get_current_dev();
196 if (miiphy_read(devname, 0, 18, &mode) == 0) {
197
198 mode |= 0x00E0;
199 miiphy_write(devname, 0, 18, mode);
200
201 miiphy_write(devname, 0, MII_BMCR, BMCR_RESET);
202 }
203
204 return eth_init();
205}
206#endif
207
208#ifdef CONFIG_GENERIC_ATMEL_MCI
209int board_mmc_init(bd_t *bd)
210{
211 at91_periph_clk_enable(ATMEL_ID_MCI);
212
213
214 at91_mci_hw_init();
215
216 return atmel_mci_init((void *)ATMEL_BASE_MCI);
217}
218
219int board_mmc_getcd(struct mmc *mmc)
220{
221 return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN);
222}
223#endif
224
225#ifdef CONFIG_ATMEL_SPI
226
227
228
229
230
231
232
233void spi_cs_activate(struct spi_slave *slave)
234{
235
236 at91_set_pio_output(AT91_PIO_PORTA, 3, 0);
237}
238
239void spi_cs_deactivate(struct spi_slave *slave)
240{
241
242 at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
243
244 at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
245}
246
247int spi_cs_is_valid(unsigned int bus, unsigned int cs)
248{
249 return bus == 0 && cs == 0;
250}
251#endif
252