LXR uboot/board/freescale/ls1012afrdm/ls1012afrdm.c

   1/*
   2 * Copyright 2016 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <i2c.h>
   9#include <asm/io.h>
  10#include <asm/arch/clock.h>
  11#include <asm/arch/fsl_serdes.h>
  12#ifdef CONFIG_FSL_LS_PPA
  13#include <asm/arch/ppa.h>
  14#endif
  15#include <asm/arch/soc.h>
  16#include <hwconfig.h>
  17#include <environment.h>
  18#include <fsl_mmdc.h>
  19#include <netdev.h>
  20
  21DECLARE_GLOBAL_DATA_PTR;
  22
  23int checkboard(void)
  24{
  25        puts("Board: LS1012AFRDM ");
  26
  27        return 0;
  28}
  29
  30int dram_init(void)
  31{
  32        static const struct fsl_mmdc_info mparam = {
  33                0x04180000,     /* mdctl */
  34                0x00030035,     /* mdpdc */
  35                0x12554000,     /* mdotc */
  36                0xbabf7954,     /* mdcfg0 */
  37                0xdb328f64,     /* mdcfg1 */
  38                0x01ff00db,     /* mdcfg2 */
  39                0x00001680,     /* mdmisc */
  40                0x0f3c8000,     /* mdref */
  41                0x00002000,     /* mdrwd */
  42                0x00bf1023,     /* mdor */
  43                0x0000003f,     /* mdasp */
  44                0x0000022a,     /* mpodtctrl */
  45                0xa1390003,     /* mpzqhwctrl */
  46        };
  47
  48        mmdc_init(&mparam);
  49
  50        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  51
  52        return 0;
  53}
  54
  55int board_eth_init(bd_t *bis)
  56{
  57        return pci_eth_init(bis);
  58}
  59
  60int board_early_init_f(void)
  61{
  62        fsl_lsch2_early_init_f();
  63
  64        return 0;
  65}
  66
  67int board_init(void)
  68{
  69        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
  70        /*
  71         * Set CCI-400 control override register to enable barrier
  72         * transaction
  73         */
  74        out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
  75
  76#ifdef CONFIG_ENV_IS_NOWHERE
  77        gd->env_addr = (ulong)&default_environment[0];
  78#endif
  79
  80#ifdef CONFIG_FSL_LS_PPA
  81        ppa_init();
  82#endif
  83        return 0;
  84}
  85
  86int ft_board_setup(void *blob, bd_t *bd)
  87{
  88        arch_fixup_fdt(blob);
  89
  90        ft_cpu_setup(blob, bd);
  91
  92        return 0;
  93}
  94
  95void dram_init_banksize(void)
  96{
  97        /*
  98         * gd->arch.secure_ram tracks the location of secure memory.
  99         * It was set as if the memory starts from 0.
 100         * The address needs to add the offset of its bank.
 101         */
 102        gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 103        if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
 104                gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
 105                gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
 106                gd->bd->bi_dram[1].size = gd->ram_size -
 107                        CONFIG_SYS_DDR_BLOCK1_SIZE;
 108#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 109                gd->arch.secure_ram = gd->bd->bi_dram[1].start +
 110                        gd->arch.secure_ram -
 111                        CONFIG_SYS_DDR_BLOCK1_SIZE;
 112                gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 113#endif
 114        } else {
 115                gd->bd->bi_dram[0].size = gd->ram_size;
 116#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 117                gd->arch.secure_ram = gd->bd->bi_dram[0].start +
 118                        gd->arch.secure_ram;
 119                gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 120#endif
 121        }
 122}
 123