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7#include <asm/arch/clock.h>
8#include <asm/arch/iomux.h>
9#include <asm/arch/imx-regs.h>
10#include <asm/arch/crm_regs.h>
11#include <asm/arch/mx6ul_pins.h>
12#include <asm/arch/mx6-pins.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/gpio.h>
15#include <asm/imx-common/iomux-v3.h>
16#include <asm/imx-common/boot_mode.h>
17#include <asm/imx-common/mxc_i2c.h>
18#include <asm/io.h>
19#include <common.h>
20#include <fsl_esdhc.h>
21#include <i2c.h>
22#include <miiphy.h>
23#include <linux/sizes.h>
24#include <mmc.h>
25#include <netdev.h>
26#include <power/pmic.h>
27#include <power/pfuze3000_pmic.h>
28#include "../common/pfuze.h"
29#include <usb.h>
30#include <usb/ehci-ci.h>
31
32DECLARE_GLOBAL_DATA_PTR;
33
34#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37
38#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
39 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
40 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
41
42#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
43 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
44 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45
46#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
48 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
49 PAD_CTL_ODE)
50
51#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
52 PAD_CTL_SPEED_HIGH | \
53 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
54
55#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
56 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
57
58#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
59 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
60
61#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
62
63#define IOX_SDI IMX_GPIO_NR(5, 10)
64#define IOX_STCP IMX_GPIO_NR(5, 7)
65#define IOX_SHCP IMX_GPIO_NR(5, 11)
66#define IOX_OE IMX_GPIO_NR(5, 8)
67
68static iomux_v3_cfg_t const iox_pads[] = {
69
70 MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
71
72 MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
73
74 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
75
76 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
77};
78
79
80
81
82
83
84
85
86
87
88
89enum qn {
90 HDMI_NRST,
91 ENET1_NRST,
92 ENET2_NRST,
93 CAN1_2_STBY,
94 BT_NPWD,
95 CSI_RST,
96 CSI_PWDN,
97 LCD_NPWREN,
98};
99
100enum qn_func {
101 qn_reset,
102 qn_enable,
103 qn_disable,
104};
105
106enum qn_level {
107 qn_low = 0,
108 qn_high = 1,
109};
110
111static enum qn_level seq[3][2] = {
112 {0, 1}, {1, 1}, {0, 0}
113};
114
115static enum qn_func qn_output[8] = {
116 qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
117 qn_disable, qn_disable
118};
119
120static void iox74lv_init(void)
121{
122 int i;
123
124 gpio_direction_output(IOX_OE, 0);
125
126 for (i = 7; i >= 0; i--) {
127 gpio_direction_output(IOX_SHCP, 0);
128 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
129 udelay(500);
130 gpio_direction_output(IOX_SHCP, 1);
131 udelay(500);
132 }
133
134 gpio_direction_output(IOX_STCP, 0);
135 udelay(500);
136
137
138
139 gpio_direction_output(IOX_STCP, 1);
140
141 for (i = 7; i >= 0; i--) {
142 gpio_direction_output(IOX_SHCP, 0);
143 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
144 udelay(500);
145 gpio_direction_output(IOX_SHCP, 1);
146 udelay(500);
147 }
148 gpio_direction_output(IOX_STCP, 0);
149 udelay(500);
150
151
152
153 gpio_direction_output(IOX_STCP, 1);
154};
155
156#ifdef CONFIG_SYS_I2C_MXC
157#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
158
159static struct i2c_pads_info i2c_pad_info1 = {
160 .scl = {
161 .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
162 .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
163 .gp = IMX_GPIO_NR(1, 28),
164 },
165 .sda = {
166 .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
167 .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
168 .gp = IMX_GPIO_NR(1, 29),
169 },
170};
171
172#ifdef CONFIG_POWER
173#define I2C_PMIC 0
174int power_init_board(void)
175{
176 if (is_mx6ul_9x9_evk()) {
177 struct pmic *pfuze;
178 int ret;
179 unsigned int reg, rev_id;
180
181 ret = power_pfuze3000_init(I2C_PMIC);
182 if (ret)
183 return ret;
184
185 pfuze = pmic_get("PFUZE3000");
186 ret = pmic_probe(pfuze);
187 if (ret)
188 return ret;
189
190 pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®);
191 pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
192 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n",
193 reg, rev_id);
194
195
196 pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1);
197
198
199 reg = 0x40;
200 pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
201
202
203 reg = 0xc;
204 pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
205
206
207 reg = 0xb;
208 pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
209 }
210
211 return 0;
212}
213#endif
214#endif
215
216int dram_init(void)
217{
218 gd->ram_size = imx_ddr_size();
219
220 return 0;
221}
222
223static iomux_v3_cfg_t const uart1_pads[] = {
224 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
225 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
226};
227
228static iomux_v3_cfg_t const usdhc1_pads[] = {
229 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
230 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
231 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
232 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
233 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
234 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
235
236
237 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
238
239 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
240
241 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
242};
243
244
245
246
247
248
249
250#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
251static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
252 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
253 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
254 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
255 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
256 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
257 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
258 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
259 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
260 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
261 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
262
263
264
265
266 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
267};
268#else
269static iomux_v3_cfg_t const usdhc2_pads[] = {
270 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
271 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
272 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
273 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
274 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
275 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
276};
277
278
279
280
281
282static iomux_v3_cfg_t const usdhc2_cd_pad =
283 MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
284
285static iomux_v3_cfg_t const usdhc2_dat3_pad =
286 MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
287 MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
288#endif
289
290static void setup_iomux_uart(void)
291{
292 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
293}
294
295#ifdef CONFIG_FSL_QSPI
296
297#define QSPI_PAD_CTRL1 \
298 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
299 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
300
301static iomux_v3_cfg_t const quadspi_pads[] = {
302 MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
303 MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
304 MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
305 MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
306 MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
307 MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
308};
309
310static int board_qspi_init(void)
311{
312
313 imx_iomux_v3_setup_multiple_pads(quadspi_pads,
314 ARRAY_SIZE(quadspi_pads));
315
316 enable_qspi_clk(0);
317
318 return 0;
319}
320#endif
321
322#ifdef CONFIG_FSL_ESDHC
323static struct fsl_esdhc_cfg usdhc_cfg[2] = {
324 {USDHC1_BASE_ADDR, 0, 4},
325#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
326 {USDHC2_BASE_ADDR, 0, 8},
327#else
328 {USDHC2_BASE_ADDR, 0, 4},
329#endif
330};
331
332#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
333#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
334#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
335#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
336
337int board_mmc_getcd(struct mmc *mmc)
338{
339 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
340 int ret = 0;
341
342 switch (cfg->esdhc_base) {
343 case USDHC1_BASE_ADDR:
344 ret = !gpio_get_value(USDHC1_CD_GPIO);
345 break;
346 case USDHC2_BASE_ADDR:
347#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
348 ret = 1;
349#else
350 imx_iomux_v3_setup_pad(usdhc2_cd_pad);
351 gpio_direction_input(USDHC2_CD_GPIO);
352
353
354
355
356
357 ret = gpio_get_value(USDHC2_CD_GPIO);
358
359 imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
360#endif
361 break;
362 }
363
364 return ret;
365}
366
367int board_mmc_init(bd_t *bis)
368{
369#ifdef CONFIG_SPL_BUILD
370#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
371 imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
372 ARRAY_SIZE(usdhc2_emmc_pads));
373#else
374 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
375#endif
376 gpio_direction_output(USDHC2_PWR_GPIO, 0);
377 udelay(500);
378 gpio_direction_output(USDHC2_PWR_GPIO, 1);
379 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
380 return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
381#else
382 int i, ret;
383
384
385
386
387
388
389
390 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
391 switch (i) {
392 case 0:
393 imx_iomux_v3_setup_multiple_pads(
394 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
395 gpio_direction_input(USDHC1_CD_GPIO);
396 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
397
398 gpio_direction_output(USDHC1_PWR_GPIO, 0);
399 udelay(500);
400 gpio_direction_output(USDHC1_PWR_GPIO, 1);
401 break;
402 case 1:
403#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
404 imx_iomux_v3_setup_multiple_pads(
405 usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
406#else
407 imx_iomux_v3_setup_multiple_pads(
408 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
409#endif
410 gpio_direction_output(USDHC2_PWR_GPIO, 0);
411 udelay(500);
412 gpio_direction_output(USDHC2_PWR_GPIO, 1);
413 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
414 break;
415 default:
416 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
417 return -EINVAL;
418 }
419
420 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
421 if (ret) {
422 printf("Warning: failed to initialize mmc dev %d\n", i);
423 return ret;
424 }
425 }
426#endif
427 return 0;
428}
429#endif
430
431#ifdef CONFIG_USB_EHCI_MX6
432#define USB_OTHERREGS_OFFSET 0x800
433#define UCTRL_PWR_POL (1 << 9)
434
435static iomux_v3_cfg_t const usb_otg_pads[] = {
436 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
437};
438
439
440static void setup_usb(void)
441{
442 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
443 ARRAY_SIZE(usb_otg_pads));
444}
445
446int board_usb_phy_mode(int port)
447{
448 if (port == 1)
449 return USB_INIT_HOST;
450 else
451 return usb_phy_mode(port);
452}
453
454int board_ehci_hcd_init(int port)
455{
456 u32 *usbnc_usb_ctrl;
457
458 if (port > 1)
459 return -EINVAL;
460
461 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
462 port * 4);
463
464
465 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
466
467 return 0;
468}
469#endif
470
471#ifdef CONFIG_FEC_MXC
472
473
474
475
476static iomux_v3_cfg_t const fec1_pads[] = {
477 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
478 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
479 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
480 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
481 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
482 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
483 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
484 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
485 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
486 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
487};
488
489static iomux_v3_cfg_t const fec2_pads[] = {
490 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
491 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
492
493 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
494 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
495 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
496 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
497
498 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
499 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
500 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
501 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
502};
503
504static void setup_iomux_fec(int fec_id)
505{
506 if (fec_id == 0)
507 imx_iomux_v3_setup_multiple_pads(fec1_pads,
508 ARRAY_SIZE(fec1_pads));
509 else
510 imx_iomux_v3_setup_multiple_pads(fec2_pads,
511 ARRAY_SIZE(fec2_pads));
512}
513
514int board_eth_init(bd_t *bis)
515{
516 setup_iomux_fec(CONFIG_FEC_ENET_DEV);
517
518 return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
519 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
520}
521
522static int setup_fec(int fec_id)
523{
524 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
525 int ret;
526
527 if (fec_id == 0) {
528
529
530
531
532 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
533 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
534 } else {
535
536
537
538
539 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
540 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
541 }
542
543 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
544 if (ret)
545 return ret;
546
547 enable_enet_clk(1);
548
549 return 0;
550}
551
552int board_phy_config(struct phy_device *phydev)
553{
554 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
555
556 if (phydev->drv->config)
557 phydev->drv->config(phydev);
558
559 return 0;
560}
561#endif
562
563#ifdef CONFIG_VIDEO_MXS
564static iomux_v3_cfg_t const lcd_pads[] = {
565 MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
566 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
567 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
568 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
569 MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
570 MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
571 MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
572 MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
573 MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
574 MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
575 MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
576 MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
577 MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
578 MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
579 MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
580 MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
581 MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
582 MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
583 MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
584 MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
585 MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
586 MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
587 MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
588 MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
589 MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
590 MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
591 MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
592 MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
593
594
595 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
596
597
598 MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
599};
600
601static int setup_lcd(void)
602{
603 enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
604
605 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
606
607
608 gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
609 udelay(500);
610 gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
611
612
613 gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
614
615 return 0;
616}
617#endif
618
619int board_early_init_f(void)
620{
621 setup_iomux_uart();
622
623 return 0;
624}
625
626int board_init(void)
627{
628
629 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
630
631 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
632
633 iox74lv_init();
634
635#ifdef CONFIG_SYS_I2C_MXC
636 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
637#endif
638
639#ifdef CONFIG_FEC_MXC
640 setup_fec(CONFIG_FEC_ENET_DEV);
641#endif
642
643#ifdef CONFIG_USB_EHCI_MX6
644 setup_usb();
645#endif
646
647#ifdef CONFIG_FSL_QSPI
648 board_qspi_init();
649#endif
650
651#ifdef CONFIG_VIDEO_MXS
652 setup_lcd();
653#endif
654
655 return 0;
656}
657
658#ifdef CONFIG_CMD_BMODE
659static const struct boot_mode board_boot_modes[] = {
660
661 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
662 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
663 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
664 {NULL, 0},
665};
666#endif
667
668int board_late_init(void)
669{
670#ifdef CONFIG_CMD_BMODE
671 add_board_boot_modes(board_boot_modes);
672#endif
673
674#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
675 setenv("board_name", "EVK");
676
677 if (is_mx6ul_9x9_evk())
678 setenv("board_rev", "9X9");
679 else
680 setenv("board_rev", "14X14");
681#endif
682
683 return 0;
684}
685
686int checkboard(void)
687{
688 if (is_mx6ul_9x9_evk())
689 puts("Board: MX6UL 9x9 EVK\n");
690 else
691 puts("Board: MX6UL 14x14 EVK\n");
692
693 return 0;
694}
695
696#ifdef CONFIG_SPL_BUILD
697#include <libfdt.h>
698#include <spl.h>
699#include <asm/arch/mx6-ddr.h>
700
701
702static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
703 .grp_addds = 0x00000030,
704 .grp_ddrmode_ctl = 0x00020000,
705 .grp_b0ds = 0x00000030,
706 .grp_ctlds = 0x00000030,
707 .grp_b1ds = 0x00000030,
708 .grp_ddrpke = 0x00000000,
709 .grp_ddrmode = 0x00020000,
710#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
711 .grp_ddr_type = 0x00080000,
712#else
713 .grp_ddr_type = 0x000c0000,
714#endif
715};
716
717#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
718static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
719 .dram_dqm0 = 0x00000030,
720 .dram_dqm1 = 0x00000030,
721 .dram_ras = 0x00000030,
722 .dram_cas = 0x00000030,
723 .dram_odt0 = 0x00000000,
724 .dram_odt1 = 0x00000000,
725 .dram_sdba2 = 0x00000000,
726 .dram_sdclk_0 = 0x00000030,
727 .dram_sdqs0 = 0x00003030,
728 .dram_sdqs1 = 0x00003030,
729 .dram_reset = 0x00000030,
730};
731
732static struct mx6_mmdc_calibration mx6_mmcd_calib = {
733 .p0_mpwldectrl0 = 0x00000000,
734 .p0_mpdgctrl0 = 0x20000000,
735 .p0_mprddlctl = 0x4040484f,
736 .p0_mpwrdlctl = 0x40405247,
737 .mpzqlp2ctl = 0x1b4700c7,
738};
739
740static struct mx6_lpddr2_cfg mem_ddr = {
741 .mem_speed = 800,
742 .density = 2,
743 .width = 16,
744 .banks = 4,
745 .rowaddr = 14,
746 .coladdr = 10,
747 .trcd_lp = 1500,
748 .trppb_lp = 1500,
749 .trpab_lp = 2000,
750 .trasmin = 4250,
751};
752
753struct mx6_ddr_sysinfo ddr_sysinfo = {
754 .dsize = 0,
755 .cs_density = 18,
756 .ncs = 1,
757 .cs1_mirror = 0,
758 .walat = 0,
759 .ralat = 5,
760 .mif3_mode = 3,
761 .bi_on = 1,
762 .rtt_wr = 0,
763 .rtt_nom = 0,
764 .sde_to_rst = 0,
765 .rst_to_cke = 0x10,
766 .ddr_type = DDR_TYPE_LPDDR2,
767 .refsel = 0,
768 .refr = 3,
769};
770
771#else
772static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
773 .dram_dqm0 = 0x00000030,
774 .dram_dqm1 = 0x00000030,
775 .dram_ras = 0x00000030,
776 .dram_cas = 0x00000030,
777 .dram_odt0 = 0x00000030,
778 .dram_odt1 = 0x00000030,
779 .dram_sdba2 = 0x00000000,
780 .dram_sdclk_0 = 0x00000030,
781 .dram_sdqs0 = 0x00000030,
782 .dram_sdqs1 = 0x00000030,
783 .dram_reset = 0x00000030,
784};
785
786static struct mx6_mmdc_calibration mx6_mmcd_calib = {
787 .p0_mpwldectrl0 = 0x00000000,
788 .p0_mpdgctrl0 = 0x41570155,
789 .p0_mprddlctl = 0x4040474A,
790 .p0_mpwrdlctl = 0x40405550,
791};
792
793struct mx6_ddr_sysinfo ddr_sysinfo = {
794 .dsize = 0,
795 .cs_density = 20,
796 .ncs = 1,
797 .cs1_mirror = 0,
798 .rtt_wr = 2,
799 .rtt_nom = 1,
800 .walat = 0,
801 .ralat = 5,
802 .mif3_mode = 3,
803 .bi_on = 1,
804 .sde_to_rst = 0x10,
805 .rst_to_cke = 0x23,
806 .ddr_type = DDR_TYPE_DDR3,
807 .refsel = 0,
808 .refr = 1,
809};
810
811static struct mx6_ddr3_cfg mem_ddr = {
812 .mem_speed = 800,
813 .density = 4,
814 .width = 16,
815 .banks = 8,
816 .rowaddr = 15,
817 .coladdr = 10,
818 .pagesz = 2,
819 .trcd = 1375,
820 .trcmin = 4875,
821 .trasmin = 3500,
822};
823#endif
824
825static void ccgr_init(void)
826{
827 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
828
829 writel(0xFFFFFFFF, &ccm->CCGR0);
830 writel(0xFFFFFFFF, &ccm->CCGR1);
831 writel(0xFFFFFFFF, &ccm->CCGR2);
832 writel(0xFFFFFFFF, &ccm->CCGR3);
833 writel(0xFFFFFFFF, &ccm->CCGR4);
834 writel(0xFFFFFFFF, &ccm->CCGR5);
835 writel(0xFFFFFFFF, &ccm->CCGR6);
836 writel(0xFFFFFFFF, &ccm->CCGR7);
837}
838
839static void spl_dram_init(void)
840{
841 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
842 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
843}
844
845void board_init_f(ulong dummy)
846{
847 ccgr_init();
848
849
850 arch_cpu_init();
851
852
853 board_early_init_f();
854
855
856 timer_init();
857
858
859 preloader_console_init();
860
861
862 spl_dram_init();
863
864
865 memset(__bss_start, 0, __bss_end - __bss_start);
866
867
868 board_init_r(NULL, 0);
869}
870#endif
871
