LXR uboot/board/ti/ks2_evm/ddr3

   1/*
   2 * Keystone2: DDR3 initialization
   3 *
   4 * (C) Copyright 2012-2014
   5 *     Texas Instruments Incorporated, <www.ti.com>
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10#include <common.h>
  11#include "ddr3_cfg.h"
  12#include <asm/arch/ddr3.h>
  13#include <asm/arch/hardware.h>
  14
  15struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
  16struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
  17
  18u32 ddr3_init(void)
  19{
  20        u32 ddr3_size;
  21        struct ddr3_spd_cb spd_cb;
  22
  23        if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
  24                printf("Sorry, I don't know how to configure DDR3A.\n"
  25                       "Bye :(\n");
  26                for (;;)
  27                        ;
  28        }
  29
  30        printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
  31
  32        if ((cpu_revision() > 1) ||
  33            (__raw_readl(KS2_RSTCTRL_RSTYPE) & 0x1)) {
  34                printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
  35                if (spd_cb.ddrspdclock == 1600)
  36                        init_pll(&ddr3a_400);
  37                else
  38                        init_pll(&ddr3a_333);
  39        }
  40
  41        if (cpu_revision() > 0) {
  42                if (cpu_revision() > 1) {
  43                        /* PG 2.0 */
  44                        /* Reset DDR3A PHY after PLL enabled */
  45                        ddr3_reset_ddrphy();
  46                        spd_cb.phy_cfg.zq0cr1 |= 0x10000;
  47                        spd_cb.phy_cfg.zq1cr1 |= 0x10000;
  48                        spd_cb.phy_cfg.zq2cr1 |= 0x10000;
  49                }
  50                ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
  51
  52                ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
  53
  54                ddr3_size = spd_cb.ddr_size_gbyte;
  55        } else {
  56                ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
  57                spd_cb.emif_cfg.sdcfg |= 0x1000;
  58                ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
  59                ddr3_size = spd_cb.ddr_size_gbyte / 2;
  60        }
  61        printf("DRAM: %d GiB (includes reported below)\n", ddr3_size);
  62
  63        /* Apply the workaround for PG 1.0 and 1.1 Silicons */
  64        if (cpu_revision() <= 1)
  65                ddr3_err_reset_workaround();
  66
  67        return ddr3_size;
  68}
  69