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18#ifndef __DRIVERS_USB_DWC3_CORE_H
19#define __DRIVERS_USB_DWC3_CORE_H
20
21#include <linux/ioport.h>
22
23#include <linux/usb/ch9.h>
24#include <linux/usb/otg.h>
25
26#define DWC3_MSG_MAX 500
27
28
29#define DWC3_EP0_BOUNCE_SIZE 512
30#define DWC3_ENDPOINTS_NUM 32
31#define DWC3_XHCI_RESOURCES_NUM 2
32
33#define DWC3_SCRATCHBUF_SIZE 4096
34#define DWC3_EVENT_SIZE 4
35#define DWC3_EVENT_MAX_NUM 64
36#define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
37#define DWC3_EVENT_TYPE_MASK 0xfe
38
39#define DWC3_EVENT_TYPE_DEV 0
40#define DWC3_EVENT_TYPE_CARKIT 3
41#define DWC3_EVENT_TYPE_I2C 4
42
43#define DWC3_DEVICE_EVENT_DISCONNECT 0
44#define DWC3_DEVICE_EVENT_RESET 1
45#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
46#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
47#define DWC3_DEVICE_EVENT_WAKEUP 4
48#define DWC3_DEVICE_EVENT_HIBER_REQ 5
49#define DWC3_DEVICE_EVENT_EOPF 6
50#define DWC3_DEVICE_EVENT_SOF 7
51#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
52#define DWC3_DEVICE_EVENT_CMD_CMPL 10
53#define DWC3_DEVICE_EVENT_OVERFLOW 11
54
55#define DWC3_GEVNTCOUNT_MASK 0xfffc
56#define DWC3_GSNPSID_MASK 0xffff0000
57#define DWC3_GSNPSREV_MASK 0xffff
58
59
60#define DWC3_XHCI_REGS_START 0x0
61#define DWC3_XHCI_REGS_END 0x7fff
62#define DWC3_GLOBALS_REGS_START 0xc100
63#define DWC3_GLOBALS_REGS_END 0xc6ff
64#define DWC3_DEVICE_REGS_START 0xc700
65#define DWC3_DEVICE_REGS_END 0xcbff
66#define DWC3_OTG_REGS_START 0xcc00
67#define DWC3_OTG_REGS_END 0xccff
68
69
70#define DWC3_GSBUSCFG0 0xc100
71#define DWC3_GSBUSCFG1 0xc104
72#define DWC3_GTXTHRCFG 0xc108
73#define DWC3_GRXTHRCFG 0xc10c
74#define DWC3_GCTL 0xc110
75#define DWC3_GEVTEN 0xc114
76#define DWC3_GSTS 0xc118
77#define DWC3_GSNPSID 0xc120
78#define DWC3_GGPIO 0xc124
79#define DWC3_GUID 0xc128
80#define DWC3_GUCTL 0xc12c
81#define DWC3_GBUSERRADDR0 0xc130
82#define DWC3_GBUSERRADDR1 0xc134
83#define DWC3_GPRTBIMAP0 0xc138
84#define DWC3_GPRTBIMAP1 0xc13c
85#define DWC3_GHWPARAMS0 0xc140
86#define DWC3_GHWPARAMS1 0xc144
87#define DWC3_GHWPARAMS2 0xc148
88#define DWC3_GHWPARAMS3 0xc14c
89#define DWC3_GHWPARAMS4 0xc150
90#define DWC3_GHWPARAMS5 0xc154
91#define DWC3_GHWPARAMS6 0xc158
92#define DWC3_GHWPARAMS7 0xc15c
93#define DWC3_GDBGFIFOSPACE 0xc160
94#define DWC3_GDBGLTSSM 0xc164
95#define DWC3_GPRTBIMAP_HS0 0xc180
96#define DWC3_GPRTBIMAP_HS1 0xc184
97#define DWC3_GPRTBIMAP_FS0 0xc188
98#define DWC3_GPRTBIMAP_FS1 0xc18c
99
100#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
101#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
102
103#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
104
105#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
106
107#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
108#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
109
110#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
111#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
112#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
113#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
114
115#define DWC3_GHWPARAMS8 0xc600
116
117
118#define DWC3_DCFG 0xc700
119#define DWC3_DCTL 0xc704
120#define DWC3_DEVTEN 0xc708
121#define DWC3_DSTS 0xc70c
122#define DWC3_DGCMDPAR 0xc710
123#define DWC3_DGCMD 0xc714
124#define DWC3_DALEPENA 0xc720
125#define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
126#define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
127#define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
128#define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
129
130
131#define DWC3_OCFG 0xcc00
132#define DWC3_OCTL 0xcc04
133#define DWC3_OEVT 0xcc08
134#define DWC3_OEVTEN 0xcc0C
135#define DWC3_OSTS 0xcc10
136
137
138
139
140#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
141#define DWC3_GCTL_U2RSTECN (1 << 16)
142#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
143#define DWC3_GCTL_CLK_BUS (0)
144#define DWC3_GCTL_CLK_PIPE (1)
145#define DWC3_GCTL_CLK_PIPEHALF (2)
146#define DWC3_GCTL_CLK_MASK (3)
147
148#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
149#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
150#define DWC3_GCTL_PRTCAP_HOST 1
151#define DWC3_GCTL_PRTCAP_DEVICE 2
152#define DWC3_GCTL_PRTCAP_OTG 3
153
154#define DWC3_GCTL_CORESOFTRESET (1 << 11)
155#define DWC3_GCTL_SOFITPSYNC (1 << 10)
156#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
157#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
158#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
159#define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
160#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
161#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
162
163
164#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
165#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
166
167
168#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
169#define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
170#define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
171#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
172#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
173#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
174#define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
175#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
176#define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
177#define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
178#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
179#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
180
181
182#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
183#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
184
185
186#define DWC3_GEVNTSIZ_INTMASK (1 << 31)
187#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
188
189
190#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
191#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
192#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
193#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
194#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
195#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
196
197
198#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
199#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
200#define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1
201#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
202#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
203#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
204#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
205#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
206#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
207#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
208#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
209
210
211#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
212#define DWC3_MAX_HIBER_SCRATCHBUFS 15
213
214
215#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
216
217
218#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
219#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
220
221#define DWC3_DCFG_SPEED_MASK (7 << 0)
222#define DWC3_DCFG_SUPERSPEED (4 << 0)
223#define DWC3_DCFG_HIGHSPEED (0 << 0)
224#define DWC3_DCFG_FULLSPEED2 (1 << 0)
225#define DWC3_DCFG_LOWSPEED (2 << 0)
226#define DWC3_DCFG_FULLSPEED1 (3 << 0)
227
228#define DWC3_DCFG_LPM_CAP (1 << 22)
229
230
231#define DWC3_DCTL_RUN_STOP (1 << 31)
232#define DWC3_DCTL_CSFTRST (1 << 30)
233#define DWC3_DCTL_LSFTRST (1 << 29)
234
235#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
236#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
237
238#define DWC3_DCTL_APPL1RES (1 << 23)
239
240
241#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
242#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
243#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
244#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
245#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
246#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
247#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
248
249
250#define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
251#define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
252
253#define DWC3_DCTL_KEEP_CONNECT (1 << 19)
254#define DWC3_DCTL_L1_HIBER_EN (1 << 18)
255#define DWC3_DCTL_CRS (1 << 17)
256#define DWC3_DCTL_CSS (1 << 16)
257
258#define DWC3_DCTL_INITU2ENA (1 << 12)
259#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
260#define DWC3_DCTL_INITU1ENA (1 << 10)
261#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
262#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
263
264#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
265#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
266
267#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
268#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
269#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
270#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
271#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
272#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
273#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
274
275
276#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
277#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
278#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
279#define DWC3_DEVTEN_ERRTICERREN (1 << 9)
280#define DWC3_DEVTEN_SOFEN (1 << 7)
281#define DWC3_DEVTEN_EOPFEN (1 << 6)
282#define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
283#define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
284#define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
285#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
286#define DWC3_DEVTEN_USBRSTEN (1 << 1)
287#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
288
289
290#define DWC3_DSTS_DCNRD (1 << 29)
291
292
293#define DWC3_DSTS_PWRUPREQ (1 << 24)
294
295
296#define DWC3_DSTS_RSS (1 << 25)
297#define DWC3_DSTS_SSS (1 << 24)
298
299#define DWC3_DSTS_COREIDLE (1 << 23)
300#define DWC3_DSTS_DEVCTRLHLT (1 << 22)
301
302#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
303#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
304
305#define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
306
307#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
308#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
309
310#define DWC3_DSTS_CONNECTSPD (7 << 0)
311
312#define DWC3_DSTS_SUPERSPEED (4 << 0)
313#define DWC3_DSTS_HIGHSPEED (0 << 0)
314#define DWC3_DSTS_FULLSPEED2 (1 << 0)
315#define DWC3_DSTS_LOWSPEED (2 << 0)
316#define DWC3_DSTS_FULLSPEED1 (3 << 0)
317
318
319#define DWC3_DGCMD_SET_LMP 0x01
320#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
321#define DWC3_DGCMD_XMIT_FUNCTION 0x03
322
323
324#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
325#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
326
327#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
328#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
329#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
330#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
331
332#define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1)
333#define DWC3_DGCMD_CMDACT (1 << 10)
334#define DWC3_DGCMD_CMDIOC (1 << 8)
335
336
337#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
338#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
339#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
340#define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
341#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
342#define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
343
344
345#define DWC3_DEPCMD_PARAM_SHIFT 16
346#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
347#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
348#define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1)
349#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
350#define DWC3_DEPCMD_CMDACT (1 << 10)
351#define DWC3_DEPCMD_CMDIOC (1 << 8)
352
353#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
354#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
355#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
356#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
357#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
358#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
359
360#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
361
362#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
363#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
364#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
365
366
367#define DWC3_DALEPENA_EP(n) (1 << n)
368
369#define DWC3_DEPCMD_TYPE_CONTROL 0
370#define DWC3_DEPCMD_TYPE_ISOC 1
371#define DWC3_DEPCMD_TYPE_BULK 2
372#define DWC3_DEPCMD_TYPE_INTR 3
373
374
375
376struct dwc3_trb;
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388struct dwc3_event_buffer {
389 void *buf;
390 unsigned length;
391 unsigned int lpos;
392 unsigned int count;
393 unsigned int flags;
394
395#define DWC3_EVENT_PENDING (1UL << 0)
396
397 dma_addr_t dma;
398
399 struct dwc3 *dwc;
400};
401
402#define DWC3_EP_FLAG_STALLED (1 << 0)
403#define DWC3_EP_FLAG_WEDGED (1 << 1)
404
405#define DWC3_EP_DIRECTION_TX true
406#define DWC3_EP_DIRECTION_RX false
407
408#define DWC3_TRB_NUM 32
409#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
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433struct dwc3_ep {
434 struct usb_ep endpoint;
435 struct list_head request_list;
436 struct list_head req_queued;
437
438 struct dwc3_trb *trb_pool;
439 dma_addr_t trb_pool_dma;
440 u32 free_slot;
441 u32 busy_slot;
442 const struct usb_ss_ep_comp_descriptor *comp_desc;
443 struct dwc3 *dwc;
444
445 u32 saved_state;
446 unsigned flags;
447#define DWC3_EP_ENABLED (1 << 0)
448#define DWC3_EP_STALL (1 << 1)
449#define DWC3_EP_WEDGE (1 << 2)
450#define DWC3_EP_BUSY (1 << 4)
451#define DWC3_EP_PENDING_REQUEST (1 << 5)
452#define DWC3_EP_MISSED_ISOC (1 << 6)
453
454
455#define DWC3_EP0_DIR_IN (1 << 31)
456
457 unsigned current_trb;
458
459 u8 number;
460 u8 type;
461 u8 resource_index;
462 u32 interval;
463
464 char name[20];
465
466 unsigned direction:1;
467 unsigned stream_capable:1;
468};
469
470enum dwc3_phy {
471 DWC3_PHY_UNKNOWN = 0,
472 DWC3_PHY_USB3,
473 DWC3_PHY_USB2,
474};
475
476enum dwc3_ep0_next {
477 DWC3_EP0_UNKNOWN = 0,
478 DWC3_EP0_COMPLETE,
479 DWC3_EP0_NRDY_DATA,
480 DWC3_EP0_NRDY_STATUS,
481};
482
483enum dwc3_ep0_state {
484 EP0_UNCONNECTED = 0,
485 EP0_SETUP_PHASE,
486 EP0_DATA_PHASE,
487 EP0_STATUS_PHASE,
488};
489
490enum dwc3_link_state {
491
492 DWC3_LINK_STATE_U0 = 0x00,
493 DWC3_LINK_STATE_U1 = 0x01,
494 DWC3_LINK_STATE_U2 = 0x02,
495 DWC3_LINK_STATE_U3 = 0x03,
496 DWC3_LINK_STATE_SS_DIS = 0x04,
497 DWC3_LINK_STATE_RX_DET = 0x05,
498 DWC3_LINK_STATE_SS_INACT = 0x06,
499 DWC3_LINK_STATE_POLL = 0x07,
500 DWC3_LINK_STATE_RECOV = 0x08,
501 DWC3_LINK_STATE_HRESET = 0x09,
502 DWC3_LINK_STATE_CMPLY = 0x0a,
503 DWC3_LINK_STATE_LPBK = 0x0b,
504 DWC3_LINK_STATE_RESET = 0x0e,
505 DWC3_LINK_STATE_RESUME = 0x0f,
506 DWC3_LINK_STATE_MASK = 0x0f,
507};
508
509
510#define DWC3_TRB_SIZE_MASK (0x00ffffff)
511#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
512#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
513#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
514
515#define DWC3_TRBSTS_OK 0
516#define DWC3_TRBSTS_MISSED_ISOC 1
517#define DWC3_TRBSTS_SETUP_PENDING 2
518#define DWC3_TRB_STS_XFER_IN_PROG 4
519
520
521#define DWC3_TRB_CTRL_HWO (1 << 0)
522#define DWC3_TRB_CTRL_LST (1 << 1)
523#define DWC3_TRB_CTRL_CHN (1 << 2)
524#define DWC3_TRB_CTRL_CSP (1 << 3)
525#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
526#define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
527#define DWC3_TRB_CTRL_IOC (1 << 11)
528#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
529
530#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
531#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
532#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
533#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
534#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
535#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
536#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
537#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
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545
546struct dwc3_trb {
547 u32 bpl;
548 u32 bph;
549 u32 size;
550 u32 ctrl;
551} __packed;
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565struct dwc3_hwparams {
566 u32 hwparams0;
567 u32 hwparams1;
568 u32 hwparams2;
569 u32 hwparams3;
570 u32 hwparams4;
571 u32 hwparams5;
572 u32 hwparams6;
573 u32 hwparams7;
574 u32 hwparams8;
575};
576
577
578#define DWC3_MODE(n) ((n) & 0x7)
579
580#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
581
582
583#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
584
585
586#define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
587#define DWC3_NUM_EPS_MASK (0x3f << 12)
588#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
589 (DWC3_NUM_EPS_MASK)) >> 12)
590#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
591 (DWC3_NUM_IN_EPS_MASK)) >> 18)
592
593
594#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
595
596struct dwc3_request {
597 struct usb_request request;
598 struct list_head list;
599 struct dwc3_ep *dep;
600 u32 start_slot;
601
602 u8 epnum;
603 struct dwc3_trb *trb;
604 dma_addr_t trb_dma;
605
606 unsigned direction:1;
607 unsigned mapped:1;
608 unsigned queued:1;
609};
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614
615struct dwc3_scratchpad_array {
616 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
617};
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701struct dwc3 {
702 struct usb_ctrlrequest *ctrl_req;
703 struct dwc3_trb *ep0_trb;
704 void *ep0_bounce;
705 void *scratchbuf;
706 u8 *setup_buf;
707 dma_addr_t ctrl_req_addr;
708 dma_addr_t ep0_trb_addr;
709 dma_addr_t ep0_bounce_addr;
710 dma_addr_t scratch_addr;
711 struct dwc3_request ep0_usb_req;
712
713
714 spinlock_t lock;
715
716 struct device *dev;
717
718 struct platform_device *xhci;
719 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
720
721 struct dwc3_event_buffer **ev_buffs;
722 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
723
724 struct usb_gadget gadget;
725 struct usb_gadget_driver *gadget_driver;
726
727 void __iomem *regs;
728 size_t regs_size;
729
730 enum usb_dr_mode dr_mode;
731
732
733 u32 dcfg;
734 u32 gctl;
735
736 u32 nr_scratch;
737 u32 num_event_buffers;
738 u32 u1u2;
739 u32 maximum_speed;
740 u32 revision;
741
742#define DWC3_REVISION_173A 0x5533173a
743#define DWC3_REVISION_175A 0x5533175a
744#define DWC3_REVISION_180A 0x5533180a
745#define DWC3_REVISION_183A 0x5533183a
746#define DWC3_REVISION_185A 0x5533185a
747#define DWC3_REVISION_187A 0x5533187a
748#define DWC3_REVISION_188A 0x5533188a
749#define DWC3_REVISION_190A 0x5533190a
750#define DWC3_REVISION_194A 0x5533194a
751#define DWC3_REVISION_200A 0x5533200a
752#define DWC3_REVISION_202A 0x5533202a
753#define DWC3_REVISION_210A 0x5533210a
754#define DWC3_REVISION_220A 0x5533220a
755#define DWC3_REVISION_230A 0x5533230a
756#define DWC3_REVISION_240A 0x5533240a
757#define DWC3_REVISION_250A 0x5533250a
758#define DWC3_REVISION_260A 0x5533260a
759#define DWC3_REVISION_270A 0x5533270a
760#define DWC3_REVISION_280A 0x5533280a
761
762 enum dwc3_ep0_next ep0_next_event;
763 enum dwc3_ep0_state ep0state;
764 enum dwc3_link_state link_state;
765
766 u16 isoch_delay;
767 u16 u2sel;
768 u16 u2pel;
769 u8 u1sel;
770 u8 u1pel;
771
772 u8 speed;
773
774 u8 num_out_eps;
775 u8 num_in_eps;
776
777 void *mem;
778
779 struct dwc3_hwparams hwparams;
780 struct dentry *root;
781 struct debugfs_regset32 *regset;
782
783 u8 test_mode;
784 u8 test_mode_nr;
785 u8 lpm_nyet_threshold;
786 u8 hird_threshold;
787
788 unsigned delayed_status:1;
789 unsigned ep0_bounced:1;
790 unsigned ep0_expect_in:1;
791 unsigned has_hibernation:1;
792 unsigned has_lpm_erratum:1;
793 unsigned is_utmi_l1_suspend:1;
794 unsigned is_selfpowered:1;
795 unsigned is_fpga:1;
796 unsigned needs_fifo_resize:1;
797 unsigned pullups_connected:1;
798 unsigned resize_fifos:1;
799 unsigned setup_packet_pending:1;
800 unsigned start_config_issued:1;
801 unsigned three_stage_setup:1;
802
803 unsigned disable_scramble_quirk:1;
804 unsigned u2exit_lfps_quirk:1;
805 unsigned u2ss_inp3_quirk:1;
806 unsigned req_p1p2p3_quirk:1;
807 unsigned del_p1p2p3_quirk:1;
808 unsigned del_phy_power_chg_quirk:1;
809 unsigned lfps_filter_quirk:1;
810 unsigned rx_detect_poll_quirk:1;
811 unsigned dis_u3_susphy_quirk:1;
812 unsigned dis_u2_susphy_quirk:1;
813
814 unsigned tx_de_emphasis_quirk:1;
815 unsigned tx_de_emphasis:2;
816 int index;
817 struct list_head list;
818};
819
820
821
822
823
824struct dwc3_event_type {
825 u32 is_devspec:1;
826 u32 type:7;
827 u32 reserved8_31:24;
828} __packed;
829
830#define DWC3_DEPEVT_XFERCOMPLETE 0x01
831#define DWC3_DEPEVT_XFERINPROGRESS 0x02
832#define DWC3_DEPEVT_XFERNOTREADY 0x03
833#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
834#define DWC3_DEPEVT_STREAMEVT 0x06
835#define DWC3_DEPEVT_EPCMDCMPLT 0x07
836
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840
841static inline const char *dwc3_ep_event_string(u8 event)
842{
843 switch (event) {
844 case DWC3_DEPEVT_XFERCOMPLETE:
845 return "Transfer Complete";
846 case DWC3_DEPEVT_XFERINPROGRESS:
847 return "Transfer In-Progress";
848 case DWC3_DEPEVT_XFERNOTREADY:
849 return "Transfer Not Ready";
850 case DWC3_DEPEVT_RXTXFIFOEVT:
851 return "FIFO";
852 case DWC3_DEPEVT_STREAMEVT:
853 return "Stream";
854 case DWC3_DEPEVT_EPCMDCMPLT:
855 return "Endpoint Command Complete";
856 }
857
858 return "UNKNOWN";
859}
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880struct dwc3_event_depevt {
881 u32 one_bit:1;
882 u32 endpoint_number:5;
883 u32 endpoint_event:4;
884 u32 reserved11_10:2;
885 u32 status:4;
886
887
888#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
889
890
891#define DEPEVT_STATUS_BUSERR (1 << 0)
892#define DEPEVT_STATUS_SHORT (1 << 1)
893#define DEPEVT_STATUS_IOC (1 << 2)
894#define DEPEVT_STATUS_LST (1 << 3)
895
896
897#define DEPEVT_STREAMEVT_FOUND 1
898#define DEPEVT_STREAMEVT_NOTFOUND 2
899
900
901#define DEPEVT_STATUS_CONTROL_DATA 1
902#define DEPEVT_STATUS_CONTROL_STATUS 2
903
904 u32 parameters:16;
905} __packed;
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929struct dwc3_event_devt {
930 u32 one_bit:1;
931 u32 device_event:7;
932 u32 type:4;
933 u32 reserved15_12:4;
934 u32 event_info:9;
935 u32 reserved31_25:7;
936} __packed;
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944
945struct dwc3_event_gevt {
946 u32 one_bit:1;
947 u32 device_event:7;
948 u32 phy_port_number:4;
949 u32 reserved31_12:20;
950} __packed;
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960union dwc3_event {
961 u32 raw;
962 struct dwc3_event_type type;
963 struct dwc3_event_depevt depevt;
964 struct dwc3_event_devt devt;
965 struct dwc3_event_gevt gevt;
966};
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974
975struct dwc3_gadget_ep_cmd_params {
976 u32 param2;
977 u32 param1;
978 u32 param0;
979};
980
981
982
983
984
985#define DWC3_HAS_PERIPHERAL BIT(0)
986#define DWC3_HAS_XHCI BIT(1)
987#define DWC3_HAS_OTG BIT(3)
988
989
990int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
991
992#ifdef CONFIG_USB_DWC3_HOST
993int dwc3_host_init(struct dwc3 *dwc);
994void dwc3_host_exit(struct dwc3 *dwc);
995#else
996static inline int dwc3_host_init(struct dwc3 *dwc)
997{ return 0; }
998static inline void dwc3_host_exit(struct dwc3 *dwc)
999{ }
1000#endif
1001
1002#ifdef CONFIG_USB_DWC3_GADGET
1003int dwc3_gadget_init(struct dwc3 *dwc);
1004void dwc3_gadget_exit(struct dwc3 *dwc);
1005int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1006int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1007int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1008int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1009 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
1010int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1011#else
1012static inline int dwc3_gadget_init(struct dwc3 *dwc)
1013{ return 0; }
1014static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1015{ }
1016static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1017{ return 0; }
1018static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1019{ return 0; }
1020static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1021 enum dwc3_link_state state)
1022{ return 0; }
1023
1024static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1025 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
1026{ return 0; }
1027static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1028 int cmd, u32 param)
1029{ return 0; }
1030#endif
1031
1032#endif
1033