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8#include <common.h>
9#include <dm.h>
10#include <errno.h>
11#include <malloc.h>
12#include <memalign.h>
13#include <usb.h>
14#include <usb/lin_gadget_compat.h>
15#include <linux/mii.h>
16#include <linux/bitops.h>
17#include "usb_ether.h"
18#include "r8152.h"
19
20#ifndef CONFIG_DM_ETH
21
22static int curr_eth_dev;
23
24struct r8152_dongle {
25 unsigned short vendor;
26 unsigned short product;
27};
28
29static const struct r8152_dongle const r8152_dongles[] = {
30
31 { 0x0bda, 0x8050 },
32 { 0x0bda, 0x8152 },
33 { 0x0bda, 0x8153 },
34
35
36 { 0x04e8, 0xa101 },
37
38
39 { 0x17ef, 0x304f },
40 { 0x17ef, 0x3052 },
41 { 0x17ef, 0x3054 },
42 { 0x17ef, 0x3057 },
43 { 0x17ef, 0x7205 },
44 { 0x17ef, 0x720a },
45 { 0x17ef, 0x720b },
46 { 0x17ef, 0x720c },
47
48
49 { 0x2357, 0x0601 },
50
51
52 { 0x0955, 0x09ff },
53};
54#endif
55
56struct r8152_version {
57 unsigned short tcr;
58 unsigned short version;
59 bool gmii;
60};
61
62static const struct r8152_version const r8152_versions[] = {
63 { 0x4c00, RTL_VER_01, 0 },
64 { 0x4c10, RTL_VER_02, 0 },
65 { 0x5c00, RTL_VER_03, 1 },
66 { 0x5c10, RTL_VER_04, 1 },
67 { 0x5c20, RTL_VER_05, 1 },
68 { 0x5c30, RTL_VER_06, 1 },
69 { 0x4800, RTL_VER_07, 0 },
70};
71
72static
73int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
74{
75 ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size);
76 int ret;
77
78 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
79 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
80 value, index, tmp, size, 500);
81 memcpy(data, tmp, size);
82 return ret;
83}
84
85static
86int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
87{
88 ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size);
89
90 memcpy(tmp, data, size);
91 return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
92 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
93 value, index, tmp, size, 500);
94}
95
96int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
97 void *data, u16 type)
98{
99 u16 burst_size = 64;
100 int ret;
101 int txsize;
102
103
104 if ((size & 3) || !size || (index & 3) || !data)
105 return -EINVAL;
106
107 if (index + size > 0xffff)
108 return -EINVAL;
109
110 while (size) {
111 txsize = min(size, burst_size);
112 ret = get_registers(tp, index, type, txsize, data);
113 if (ret < 0)
114 break;
115
116 index += txsize;
117 data += txsize;
118 size -= txsize;
119 }
120
121 return ret;
122}
123
124int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
125 u16 size, void *data, u16 type)
126{
127 int ret;
128 u16 byteen_start, byteen_end, byte_en_to_hw;
129 u16 burst_size = 512;
130 int txsize;
131
132
133 if ((size & 3) || !size || (index & 3) || !data)
134 return -EINVAL;
135
136 if (index + size > 0xffff)
137 return -EINVAL;
138
139 byteen_start = byteen & BYTE_EN_START_MASK;
140 byteen_end = byteen & BYTE_EN_END_MASK;
141
142 byte_en_to_hw = byteen_start | (byteen_start << 4);
143 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
144 if (ret < 0)
145 return ret;
146
147 index += 4;
148 data += 4;
149 size -= 4;
150
151 if (size) {
152 size -= 4;
153
154 while (size) {
155 txsize = min(size, burst_size);
156
157 ret = set_registers(tp, index,
158 type | BYTE_EN_DWORD,
159 txsize, data);
160 if (ret < 0)
161 return ret;
162
163 index += txsize;
164 data += txsize;
165 size -= txsize;
166 }
167
168 byte_en_to_hw = byteen_end | (byteen_end >> 4);
169 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
170 if (ret < 0)
171 return ret;
172 }
173
174 return ret;
175}
176
177int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
178{
179 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
180}
181
182int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
183{
184 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
185}
186
187int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
188{
189 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
190}
191
192int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
193{
194 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
195}
196
197u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
198{
199 __le32 data;
200
201 generic_ocp_read(tp, index, sizeof(data), &data, type);
202
203 return __le32_to_cpu(data);
204}
205
206void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
207{
208 __le32 tmp = __cpu_to_le32(data);
209
210 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
211}
212
213u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
214{
215 u32 data;
216 __le32 tmp;
217 u8 shift = index & 2;
218
219 index &= ~3;
220
221 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
222
223 data = __le32_to_cpu(tmp);
224 data >>= (shift * 8);
225 data &= 0xffff;
226
227 return data;
228}
229
230void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
231{
232 u32 mask = 0xffff;
233 __le32 tmp;
234 u16 byen = BYTE_EN_WORD;
235 u8 shift = index & 2;
236
237 data &= mask;
238
239 if (index & 2) {
240 byen <<= shift;
241 mask <<= (shift * 8);
242 data <<= (shift * 8);
243 index &= ~3;
244 }
245
246 tmp = __cpu_to_le32(data);
247
248 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
249}
250
251u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
252{
253 u32 data;
254 __le32 tmp;
255 u8 shift = index & 3;
256
257 index &= ~3;
258
259 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
260
261 data = __le32_to_cpu(tmp);
262 data >>= (shift * 8);
263 data &= 0xff;
264
265 return data;
266}
267
268void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
269{
270 u32 mask = 0xff;
271 __le32 tmp;
272 u16 byen = BYTE_EN_BYTE;
273 u8 shift = index & 3;
274
275 data &= mask;
276
277 if (index & 3) {
278 byen <<= shift;
279 mask <<= (shift * 8);
280 data <<= (shift * 8);
281 index &= ~3;
282 }
283
284 tmp = __cpu_to_le32(data);
285
286 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
287}
288
289u16 ocp_reg_read(struct r8152 *tp, u16 addr)
290{
291 u16 ocp_base, ocp_index;
292
293 ocp_base = addr & 0xf000;
294 if (ocp_base != tp->ocp_base) {
295 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
296 tp->ocp_base = ocp_base;
297 }
298
299 ocp_index = (addr & 0x0fff) | 0xb000;
300 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
301}
302
303void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
304{
305 u16 ocp_base, ocp_index;
306
307 ocp_base = addr & 0xf000;
308 if (ocp_base != tp->ocp_base) {
309 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
310 tp->ocp_base = ocp_base;
311 }
312
313 ocp_index = (addr & 0x0fff) | 0xb000;
314 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
315}
316
317static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
318{
319 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
320}
321
322static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
323{
324 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
325}
326
327void sram_write(struct r8152 *tp, u16 addr, u16 data)
328{
329 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
330 ocp_reg_write(tp, OCP_SRAM_DATA, data);
331}
332
333int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
334 const u32 mask, bool set, unsigned int timeout)
335{
336 u32 val;
337
338 while (--timeout) {
339 if (ocp_reg)
340 val = ocp_reg_read(tp, index);
341 else
342 val = ocp_read_dword(tp, type, index);
343
344 if (!set)
345 val = ~val;
346
347 if ((val & mask) == mask)
348 return 0;
349
350 mdelay(1);
351 }
352
353 debug("%s: Timeout (index=%04x mask=%08x timeout=%d)\n",
354 __func__, index, mask, timeout);
355
356 return -ETIMEDOUT;
357}
358
359static void r8152b_reset_packet_filter(struct r8152 *tp)
360{
361 u32 ocp_data;
362
363 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
364 ocp_data &= ~FMC_FCR_MCU_EN;
365 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
366 ocp_data |= FMC_FCR_MCU_EN;
367 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
368}
369
370static void rtl8152_wait_fifo_empty(struct r8152 *tp)
371{
372 int ret;
373
374 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
375 PLA_PHY_PWR_TXEMP, 1, R8152_WAIT_TIMEOUT);
376 if (ret)
377 debug("Timeout waiting for FIFO empty\n");
378
379 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_TCR0,
380 TCR0_TX_EMPTY, 1, R8152_WAIT_TIMEOUT);
381 if (ret)
382 debug("Timeout waiting for TX empty\n");
383}
384
385static void rtl8152_nic_reset(struct r8152 *tp)
386{
387 int ret;
388 u32 ocp_data;
389
390 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, BIST_CTRL);
391 ocp_data |= BIST_CTRL_SW_RESET;
392 ocp_write_dword(tp, MCU_TYPE_PLA, BIST_CTRL, ocp_data);
393
394 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, BIST_CTRL,
395 BIST_CTRL_SW_RESET, 0, R8152_WAIT_TIMEOUT);
396 if (ret)
397 debug("Timeout waiting for NIC reset\n");
398}
399
400static u8 rtl8152_get_speed(struct r8152 *tp)
401{
402 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
403}
404
405static void rtl_set_eee_plus(struct r8152 *tp)
406{
407 u32 ocp_data;
408
409 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
410 ocp_data &= ~EEEP_CR_EEEP_TX;
411 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
412}
413
414static void rxdy_gated_en(struct r8152 *tp, bool enable)
415{
416 u32 ocp_data;
417
418 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
419 if (enable)
420 ocp_data |= RXDY_GATED_EN;
421 else
422 ocp_data &= ~RXDY_GATED_EN;
423 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
424}
425
426static void rtl8152_set_rx_mode(struct r8152 *tp)
427{
428 u32 ocp_data;
429 __le32 tmp[2];
430
431 tmp[0] = 0xffffffff;
432 tmp[1] = 0xffffffff;
433
434 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
435
436 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
437 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
438 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
439}
440
441static int rtl_enable(struct r8152 *tp)
442{
443 u32 ocp_data;
444
445 r8152b_reset_packet_filter(tp);
446
447 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
448 ocp_data |= PLA_CR_RE | PLA_CR_TE;
449 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
450
451 rxdy_gated_en(tp, false);
452
453 rtl8152_set_rx_mode(tp);
454
455 return 0;
456}
457
458static int rtl8152_enable(struct r8152 *tp)
459{
460 rtl_set_eee_plus(tp);
461
462 return rtl_enable(tp);
463}
464
465static void r8153_set_rx_early_timeout(struct r8152 *tp)
466{
467 u32 ocp_data = tp->coalesce / 8;
468
469 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
470}
471
472static void r8153_set_rx_early_size(struct r8152 *tp)
473{
474 u32 ocp_data = (RTL8152_AGG_BUF_SZ - RTL8153_RMS) / 4;
475
476 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
477}
478
479static int rtl8153_enable(struct r8152 *tp)
480{
481 rtl_set_eee_plus(tp);
482 r8153_set_rx_early_timeout(tp);
483 r8153_set_rx_early_size(tp);
484
485 return rtl_enable(tp);
486}
487
488static void rtl_disable(struct r8152 *tp)
489{
490 u32 ocp_data;
491
492 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
493 ocp_data &= ~RCR_ACPT_ALL;
494 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
495
496 rxdy_gated_en(tp, true);
497
498 rtl8152_wait_fifo_empty(tp);
499 rtl8152_nic_reset(tp);
500}
501
502static void r8152_power_cut_en(struct r8152 *tp, bool enable)
503{
504 u32 ocp_data;
505
506 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
507 if (enable)
508 ocp_data |= POWER_CUT;
509 else
510 ocp_data &= ~POWER_CUT;
511 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
512
513 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
514 ocp_data &= ~RESUME_INDICATE;
515 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
516}
517
518static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
519{
520 u32 ocp_data;
521
522 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
523 if (enable)
524 ocp_data |= CPCR_RX_VLAN;
525 else
526 ocp_data &= ~CPCR_RX_VLAN;
527 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
528}
529
530static void r8153_u1u2en(struct r8152 *tp, bool enable)
531{
532 u8 u1u2[8];
533
534 if (enable)
535 memset(u1u2, 0xff, sizeof(u1u2));
536 else
537 memset(u1u2, 0x00, sizeof(u1u2));
538
539 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
540}
541
542static void r8153_u2p3en(struct r8152 *tp, bool enable)
543{
544 u32 ocp_data;
545
546 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
547 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
548 ocp_data |= U2P3_ENABLE;
549 else
550 ocp_data &= ~U2P3_ENABLE;
551 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
552}
553
554static void r8153_power_cut_en(struct r8152 *tp, bool enable)
555{
556 u32 ocp_data;
557
558 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
559 if (enable)
560 ocp_data |= PWR_EN | PHASE2_EN;
561 else
562 ocp_data &= ~(PWR_EN | PHASE2_EN);
563 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
564
565 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
566 ocp_data &= ~PCUT_STATUS;
567 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
568}
569
570static int r8152_read_mac(struct r8152 *tp, unsigned char *macaddr)
571{
572 int ret;
573 unsigned char enetaddr[8] = {0};
574
575 ret = pla_ocp_read(tp, PLA_IDR, 8, enetaddr);
576 if (ret < 0)
577 return ret;
578
579 memcpy(macaddr, enetaddr, ETH_ALEN);
580 return 0;
581}
582
583static void r8152b_disable_aldps(struct r8152 *tp)
584{
585 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
586 mdelay(20);
587}
588
589static void r8152b_enable_aldps(struct r8152 *tp)
590{
591 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
592 LINKENA | DIS_SDSAVE);
593}
594
595static void rtl8152_disable(struct r8152 *tp)
596{
597 r8152b_disable_aldps(tp);
598 rtl_disable(tp);
599 r8152b_enable_aldps(tp);
600}
601
602static void r8152b_hw_phy_cfg(struct r8152 *tp)
603{
604 u16 data;
605
606 data = r8152_mdio_read(tp, MII_BMCR);
607 if (data & BMCR_PDOWN) {
608 data &= ~BMCR_PDOWN;
609 r8152_mdio_write(tp, MII_BMCR, data);
610 }
611
612 r8152b_firmware(tp);
613}
614
615static void rtl8152_reinit_ll(struct r8152 *tp)
616{
617 u32 ocp_data;
618 int ret;
619
620 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
621 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
622 if (ret)
623 debug("Timeout waiting for link list ready\n");
624
625 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
626 ocp_data |= RE_INIT_LL;
627 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
628
629 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
630 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
631 if (ret)
632 debug("Timeout waiting for link list ready\n");
633}
634
635static void r8152b_exit_oob(struct r8152 *tp)
636{
637 u32 ocp_data;
638
639 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
640 ocp_data &= ~RCR_ACPT_ALL;
641 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
642
643 rxdy_gated_en(tp, true);
644 r8152b_hw_phy_cfg(tp);
645
646 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
647 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
648
649 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
650 ocp_data &= ~NOW_IS_OOB;
651 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
652
653 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
654 ocp_data &= ~MCU_BORW_EN;
655 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
656
657 rtl8152_reinit_ll(tp);
658 rtl8152_nic_reset(tp);
659
660
661 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
662
663 if (tp->udev->speed == USB_SPEED_FULL ||
664 tp->udev->speed == USB_SPEED_LOW) {
665
666 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
667 RXFIFO_THR2_FULL);
668 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
669 RXFIFO_THR3_FULL);
670 } else {
671
672 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
673 RXFIFO_THR2_HIGH);
674 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
675 RXFIFO_THR3_HIGH);
676 }
677
678
679 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
680
681 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
682 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
683 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
684 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
685
686 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
687
688 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
689 ocp_data |= TCR0_AUTO_FIFO;
690 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
691}
692
693static void r8152b_enter_oob(struct r8152 *tp)
694{
695 u32 ocp_data;
696
697 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
698 ocp_data &= ~NOW_IS_OOB;
699 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
700
701 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
702 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
703 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
704
705 rtl_disable(tp);
706
707 rtl8152_reinit_ll(tp);
708
709 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
710
711 rtl_rx_vlan_en(tp, false);
712
713 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
714 ocp_data |= ALDPS_PROXY_MODE;
715 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
716
717 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
718 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
719 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
720
721 rxdy_gated_en(tp, false);
722
723 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
724 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
725 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
726}
727
728static void r8153_hw_phy_cfg(struct r8152 *tp)
729{
730 u32 ocp_data;
731 u16 data;
732
733 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
734 tp->version == RTL_VER_05)
735 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
736
737 data = r8152_mdio_read(tp, MII_BMCR);
738 if (data & BMCR_PDOWN) {
739 data &= ~BMCR_PDOWN;
740 r8152_mdio_write(tp, MII_BMCR, data);
741 }
742
743 r8153_firmware(tp);
744
745 if (tp->version == RTL_VER_03) {
746 data = ocp_reg_read(tp, OCP_EEE_CFG);
747 data &= ~CTAP_SHORT_EN;
748 ocp_reg_write(tp, OCP_EEE_CFG, data);
749 }
750
751 data = ocp_reg_read(tp, OCP_POWER_CFG);
752 data |= EEE_CLKDIV_EN;
753 ocp_reg_write(tp, OCP_POWER_CFG, data);
754
755 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
756 data |= EN_10M_BGOFF;
757 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
758 data = ocp_reg_read(tp, OCP_POWER_CFG);
759 data |= EN_10M_PLLOFF;
760 ocp_reg_write(tp, OCP_POWER_CFG, data);
761 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
762
763 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
764 ocp_data |= PFM_PWM_SWITCH;
765 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
766
767
768 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
769
770
771 sram_write(tp, SRAM_10M_AMP1, 0x00af);
772 sram_write(tp, SRAM_10M_AMP2, 0x0208);
773}
774
775static void r8153_first_init(struct r8152 *tp)
776{
777 u32 ocp_data;
778
779 rxdy_gated_en(tp, true);
780
781 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
782 ocp_data &= ~RCR_ACPT_ALL;
783 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
784
785 r8153_hw_phy_cfg(tp);
786
787 rtl8152_nic_reset(tp);
788
789 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
790 ocp_data &= ~NOW_IS_OOB;
791 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
792
793 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
794 ocp_data &= ~MCU_BORW_EN;
795 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
796
797 rtl8152_reinit_ll(tp);
798
799 rtl_rx_vlan_en(tp, false);
800
801 ocp_data = RTL8153_RMS;
802 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
803 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
804
805 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
806 ocp_data |= TCR0_AUTO_FIFO;
807 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
808
809 rtl8152_nic_reset(tp);
810
811
812 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
813 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
814 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
815
816 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
817
818
819 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
820
821 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
822 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
823}
824
825static void r8153_enter_oob(struct r8152 *tp)
826{
827 u32 ocp_data;
828
829 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
830 ocp_data &= ~NOW_IS_OOB;
831 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
832
833 rtl_disable(tp);
834
835 rtl8152_reinit_ll(tp);
836
837 ocp_data = RTL8153_RMS;
838 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
839
840 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
841 ocp_data &= ~TEREDO_WAKE_MASK;
842 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
843
844 rtl_rx_vlan_en(tp, false);
845
846 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
847 ocp_data |= ALDPS_PROXY_MODE;
848 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
849
850 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
851 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
852 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
853
854 rxdy_gated_en(tp, false);
855
856 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
857 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
858 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
859}
860
861static void r8153_disable_aldps(struct r8152 *tp)
862{
863 u16 data;
864
865 data = ocp_reg_read(tp, OCP_POWER_CFG);
866 data &= ~EN_ALDPS;
867 ocp_reg_write(tp, OCP_POWER_CFG, data);
868 mdelay(20);
869}
870
871static void rtl8153_disable(struct r8152 *tp)
872{
873 r8153_disable_aldps(tp);
874 rtl_disable(tp);
875}
876
877static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
878{
879 u16 bmcr, anar, gbcr;
880
881 anar = r8152_mdio_read(tp, MII_ADVERTISE);
882 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
883 ADVERTISE_100HALF | ADVERTISE_100FULL);
884 if (tp->supports_gmii) {
885 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
886 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
887 } else {
888 gbcr = 0;
889 }
890
891 if (autoneg == AUTONEG_DISABLE) {
892 if (speed == SPEED_10) {
893 bmcr = 0;
894 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
895 } else if (speed == SPEED_100) {
896 bmcr = BMCR_SPEED100;
897 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
898 } else if (speed == SPEED_1000 && tp->supports_gmii) {
899 bmcr = BMCR_SPEED1000;
900 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
901 } else {
902 return -EINVAL;
903 }
904
905 if (duplex == DUPLEX_FULL)
906 bmcr |= BMCR_FULLDPLX;
907 } else {
908 if (speed == SPEED_10) {
909 if (duplex == DUPLEX_FULL)
910 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
911 else
912 anar |= ADVERTISE_10HALF;
913 } else if (speed == SPEED_100) {
914 if (duplex == DUPLEX_FULL) {
915 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
916 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
917 } else {
918 anar |= ADVERTISE_10HALF;
919 anar |= ADVERTISE_100HALF;
920 }
921 } else if (speed == SPEED_1000 && tp->supports_gmii) {
922 if (duplex == DUPLEX_FULL) {
923 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
924 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
925 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
926 } else {
927 anar |= ADVERTISE_10HALF;
928 anar |= ADVERTISE_100HALF;
929 gbcr |= ADVERTISE_1000HALF;
930 }
931 } else {
932 return -EINVAL;
933 }
934
935 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
936 }
937
938 if (tp->supports_gmii)
939 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
940
941 r8152_mdio_write(tp, MII_ADVERTISE, anar);
942 r8152_mdio_write(tp, MII_BMCR, bmcr);
943
944 return 0;
945}
946
947static void rtl8152_up(struct r8152 *tp)
948{
949 r8152b_disable_aldps(tp);
950 r8152b_exit_oob(tp);
951 r8152b_enable_aldps(tp);
952}
953
954static void rtl8152_down(struct r8152 *tp)
955{
956 r8152_power_cut_en(tp, false);
957 r8152b_disable_aldps(tp);
958 r8152b_enter_oob(tp);
959 r8152b_enable_aldps(tp);
960}
961
962static void rtl8153_up(struct r8152 *tp)
963{
964 r8153_u1u2en(tp, false);
965 r8153_disable_aldps(tp);
966 r8153_first_init(tp);
967 r8153_u2p3en(tp, false);
968}
969
970static void rtl8153_down(struct r8152 *tp)
971{
972 r8153_u1u2en(tp, false);
973 r8153_u2p3en(tp, false);
974 r8153_power_cut_en(tp, false);
975 r8153_disable_aldps(tp);
976 r8153_enter_oob(tp);
977}
978
979static void r8152b_get_version(struct r8152 *tp)
980{
981 u32 ocp_data;
982 u16 tcr;
983 int i;
984
985 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
986 tcr = (u16)(ocp_data & VERSION_MASK);
987
988 for (i = 0; i < ARRAY_SIZE(r8152_versions); i++) {
989 if (tcr == r8152_versions[i].tcr) {
990
991 tp->version = r8152_versions[i].version;
992 tp->supports_gmii = r8152_versions[i].gmii;
993 break;
994 }
995 }
996
997 if (tp->version == RTL_VER_UNKNOWN)
998 debug("r8152 Unknown tcr version 0x%04x\n", tcr);
999}
1000
1001static void r8152b_enable_fc(struct r8152 *tp)
1002{
1003 u16 anar;
1004 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1005 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1006 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1007}
1008
1009static void rtl_tally_reset(struct r8152 *tp)
1010{
1011 u32 ocp_data;
1012
1013 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
1014 ocp_data |= TALLY_RESET;
1015 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
1016}
1017
1018static void r8152b_init(struct r8152 *tp)
1019{
1020 u32 ocp_data;
1021
1022 r8152b_disable_aldps(tp);
1023
1024 if (tp->version == RTL_VER_01) {
1025 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1026 ocp_data &= ~LED_MODE_MASK;
1027 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1028 }
1029
1030 r8152_power_cut_en(tp, false);
1031
1032 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1033 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
1034 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1035 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
1036 ocp_data &= ~MCU_CLK_RATIO_MASK;
1037 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
1038 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
1039 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
1040 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
1041 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
1042
1043 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_TIMER);
1044 ocp_data |= BIT(15);
1045 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1046 ocp_write_word(tp, MCU_TYPE_USB, 0xcbfc, 0x03e8);
1047 ocp_data &= ~BIT(15);
1048 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1049
1050 r8152b_enable_fc(tp);
1051 rtl_tally_reset(tp);
1052
1053
1054 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
1055
1056 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
1057 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1058}
1059
1060static void r8153_init(struct r8152 *tp)
1061{
1062 int i;
1063 u32 ocp_data;
1064
1065 r8153_disable_aldps(tp);
1066 r8153_u1u2en(tp, false);
1067
1068 r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL,
1069 AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT);
1070
1071 for (i = 0; i < R8152_WAIT_TIMEOUT; i++) {
1072 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
1073 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
1074 break;
1075
1076 mdelay(1);
1077 }
1078
1079 r8153_u2p3en(tp, false);
1080
1081 if (tp->version == RTL_VER_04) {
1082 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
1083 ocp_data &= ~pwd_dn_scale_mask;
1084 ocp_data |= pwd_dn_scale(96);
1085 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
1086
1087 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
1088 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
1089 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
1090 } else if (tp->version == RTL_VER_05) {
1091 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
1092 ocp_data &= ~ECM_ALDPS;
1093 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
1094
1095 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1096 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1097 ocp_data &= ~DYNAMIC_BURST;
1098 else
1099 ocp_data |= DYNAMIC_BURST;
1100 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1101 } else if (tp->version == RTL_VER_06) {
1102 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1103 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1104 ocp_data &= ~DYNAMIC_BURST;
1105 else
1106 ocp_data |= DYNAMIC_BURST;
1107 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1108 }
1109
1110 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
1111 ocp_data |= EP4_FULL_FC;
1112 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
1113
1114 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
1115 ocp_data &= ~TIMER11_EN;
1116 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
1117
1118 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1119 ocp_data &= ~LED_MODE_MASK;
1120 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1121
1122 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
1123 if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
1124 ocp_data |= LPM_TIMER_500MS;
1125 else
1126 ocp_data |= LPM_TIMER_500US;
1127 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
1128
1129 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
1130 ocp_data &= ~SEN_VAL_MASK;
1131 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
1132 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
1133
1134 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
1135
1136 r8153_power_cut_en(tp, false);
1137
1138 r8152b_enable_fc(tp);
1139 rtl_tally_reset(tp);
1140}
1141
1142static void rtl8152_unload(struct r8152 *tp)
1143{
1144 if (tp->version != RTL_VER_01)
1145 r8152_power_cut_en(tp, true);
1146}
1147
1148static void rtl8153_unload(struct r8152 *tp)
1149{
1150 r8153_power_cut_en(tp, false);
1151}
1152
1153static int rtl_ops_init(struct r8152 *tp)
1154{
1155 struct rtl_ops *ops = &tp->rtl_ops;
1156 int ret = 0;
1157
1158 switch (tp->version) {
1159 case RTL_VER_01:
1160 case RTL_VER_02:
1161 case RTL_VER_07:
1162 ops->init = r8152b_init;
1163 ops->enable = rtl8152_enable;
1164 ops->disable = rtl8152_disable;
1165 ops->up = rtl8152_up;
1166 ops->down = rtl8152_down;
1167 ops->unload = rtl8152_unload;
1168 break;
1169
1170 case RTL_VER_03:
1171 case RTL_VER_04:
1172 case RTL_VER_05:
1173 case RTL_VER_06:
1174 ops->init = r8153_init;
1175 ops->enable = rtl8153_enable;
1176 ops->disable = rtl8153_disable;
1177 ops->up = rtl8153_up;
1178 ops->down = rtl8153_down;
1179 ops->unload = rtl8153_unload;
1180 break;
1181
1182 default:
1183 ret = -ENODEV;
1184 printf("r8152 Unknown Device\n");
1185 break;
1186 }
1187
1188 return ret;
1189}
1190
1191static int r8152_init_common(struct r8152 *tp)
1192{
1193 u8 speed;
1194 int timeout = 0;
1195 int link_detected;
1196
1197 debug("** %s()\n", __func__);
1198
1199 do {
1200 speed = rtl8152_get_speed(tp);
1201
1202 link_detected = speed & LINK_STATUS;
1203 if (!link_detected) {
1204 if (timeout == 0)
1205 printf("Waiting for Ethernet connection... ");
1206 mdelay(TIMEOUT_RESOLUTION);
1207 timeout += TIMEOUT_RESOLUTION;
1208 }
1209 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
1210 if (link_detected) {
1211 tp->rtl_ops.enable(tp);
1212
1213 if (timeout != 0)
1214 printf("done.\n");
1215 } else {
1216 printf("unable to connect.\n");
1217 }
1218
1219 return 0;
1220}
1221
1222static int r8152_send_common(struct ueth_data *ueth, void *packet, int length)
1223{
1224 struct usb_device *udev = ueth->pusb_dev;
1225 u32 opts1, opts2 = 0;
1226 int err;
1227 int actual_len;
1228 ALLOC_CACHE_ALIGN_BUFFER(uint8_t, msg,
1229 PKTSIZE + sizeof(struct tx_desc));
1230 struct tx_desc *tx_desc = (struct tx_desc *)msg;
1231
1232 debug("** %s(), len %d\n", __func__, length);
1233
1234 opts1 = length | TX_FS | TX_LS;
1235
1236 tx_desc->opts2 = cpu_to_le32(opts2);
1237 tx_desc->opts1 = cpu_to_le32(opts1);
1238
1239 memcpy(msg + sizeof(struct tx_desc), (void *)packet, length);
1240
1241 err = usb_bulk_msg(udev, usb_sndbulkpipe(udev, ueth->ep_out),
1242 (void *)msg, length + sizeof(struct tx_desc),
1243 &actual_len, USB_BULK_SEND_TIMEOUT);
1244 debug("Tx: len = %zu, actual = %u, err = %d\n",
1245 length + sizeof(struct tx_desc), actual_len, err);
1246
1247 return err;
1248}
1249
1250#ifndef CONFIG_DM_ETH
1251static int r8152_init(struct eth_device *eth, bd_t *bd)
1252{
1253 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1254 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1255
1256 return r8152_init_common(tp);
1257}
1258
1259static int r8152_send(struct eth_device *eth, void *packet, int length)
1260{
1261 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1262
1263 return r8152_send_common(dev, packet, length);
1264}
1265
1266static int r8152_recv(struct eth_device *eth)
1267{
1268 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1269
1270 ALLOC_CACHE_ALIGN_BUFFER(uint8_t, recv_buf, RTL8152_AGG_BUF_SZ);
1271 unsigned char *pkt_ptr;
1272 int err;
1273 int actual_len;
1274 u16 packet_len;
1275
1276 u32 bytes_process = 0;
1277 struct rx_desc *rx_desc;
1278
1279 debug("** %s()\n", __func__);
1280
1281 err = usb_bulk_msg(dev->pusb_dev,
1282 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
1283 (void *)recv_buf,
1284 RTL8152_AGG_BUF_SZ,
1285 &actual_len,
1286 USB_BULK_RECV_TIMEOUT);
1287 debug("Rx: len = %u, actual = %u, err = %d\n", RTL8152_AGG_BUF_SZ,
1288 actual_len, err);
1289 if (err != 0) {
1290 debug("Rx: failed to receive\n");
1291 return -1;
1292 }
1293 if (actual_len > RTL8152_AGG_BUF_SZ) {
1294 debug("Rx: received too many bytes %d\n", actual_len);
1295 return -1;
1296 }
1297
1298 while (bytes_process < actual_len) {
1299 rx_desc = (struct rx_desc *)(recv_buf + bytes_process);
1300 pkt_ptr = recv_buf + sizeof(struct rx_desc) + bytes_process;
1301
1302 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1303 packet_len -= CRC_SIZE;
1304
1305 net_process_received_packet(pkt_ptr, packet_len);
1306
1307 bytes_process +=
1308 (packet_len + sizeof(struct rx_desc) + CRC_SIZE);
1309
1310 if (bytes_process % 8)
1311 bytes_process = bytes_process + 8 - (bytes_process % 8);
1312 }
1313
1314 return 0;
1315}
1316
1317static void r8152_halt(struct eth_device *eth)
1318{
1319 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1320 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1321
1322 debug("** %s()\n", __func__);
1323
1324 tp->rtl_ops.disable(tp);
1325}
1326
1327static int r8152_write_hwaddr(struct eth_device *eth)
1328{
1329 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1330 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1331
1332 unsigned char enetaddr[8] = {0};
1333
1334 memcpy(enetaddr, eth->enetaddr, ETH_ALEN);
1335
1336 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1337 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
1338 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1339
1340 debug("MAC %pM\n", eth->enetaddr);
1341 return 0;
1342}
1343
1344void r8152_eth_before_probe(void)
1345{
1346 curr_eth_dev = 0;
1347}
1348
1349
1350int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
1351 struct ueth_data *ss)
1352{
1353 struct usb_interface *iface;
1354 struct usb_interface_descriptor *iface_desc;
1355 int ep_in_found = 0, ep_out_found = 0;
1356 int i;
1357
1358 struct r8152 *tp;
1359
1360
1361 iface = &dev->config.if_desc[ifnum];
1362 iface_desc = &dev->config.if_desc[ifnum].desc;
1363
1364 for (i = 0; i < ARRAY_SIZE(r8152_dongles); i++) {
1365 if (dev->descriptor.idVendor == r8152_dongles[i].vendor &&
1366 dev->descriptor.idProduct == r8152_dongles[i].product)
1367
1368 break;
1369 }
1370
1371 if (i == ARRAY_SIZE(r8152_dongles))
1372 return 0;
1373
1374 memset(ss, 0, sizeof(struct ueth_data));
1375
1376
1377 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
1378 dev->descriptor.idVendor, dev->descriptor.idProduct);
1379
1380
1381 ss->ifnum = ifnum;
1382 ss->pusb_dev = dev;
1383 ss->subclass = iface_desc->bInterfaceSubClass;
1384 ss->protocol = iface_desc->bInterfaceProtocol;
1385
1386
1387 ss->dev_priv = calloc(1, sizeof(struct r8152));
1388
1389 if (!ss->dev_priv)
1390 return 0;
1391
1392
1393
1394
1395
1396 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
1397
1398 if ((iface->ep_desc[i].bmAttributes &
1399 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
1400 u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
1401 if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
1402 ss->ep_in = ep_addr &
1403 USB_ENDPOINT_NUMBER_MASK;
1404 ep_in_found = 1;
1405 } else {
1406 if (!ep_out_found) {
1407 ss->ep_out = ep_addr &
1408 USB_ENDPOINT_NUMBER_MASK;
1409 ep_out_found = 1;
1410 }
1411 }
1412 }
1413
1414
1415 if ((iface->ep_desc[i].bmAttributes &
1416 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
1417 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
1418 USB_ENDPOINT_NUMBER_MASK;
1419 ss->irqinterval = iface->ep_desc[i].bInterval;
1420 }
1421 }
1422
1423 debug("Endpoints In %d Out %d Int %d\n",
1424 ss->ep_in, ss->ep_out, ss->ep_int);
1425
1426
1427 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
1428 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
1429 debug("Problems with device\n");
1430 return 0;
1431 }
1432
1433 dev->privptr = (void *)ss;
1434
1435 tp = ss->dev_priv;
1436 tp->udev = dev;
1437 tp->intf = iface;
1438
1439 r8152b_get_version(tp);
1440
1441 if (rtl_ops_init(tp))
1442 return 0;
1443
1444 tp->rtl_ops.init(tp);
1445 tp->rtl_ops.up(tp);
1446
1447 rtl8152_set_speed(tp, AUTONEG_ENABLE,
1448 tp->supports_gmii ? SPEED_1000 : SPEED_100,
1449 DUPLEX_FULL);
1450
1451 return 1;
1452}
1453
1454int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
1455 struct eth_device *eth)
1456{
1457 if (!eth) {
1458 debug("%s: missing parameter.\n", __func__);
1459 return 0;
1460 }
1461
1462 sprintf(eth->name, "%s#%d", R8152_BASE_NAME, curr_eth_dev++);
1463 eth->init = r8152_init;
1464 eth->send = r8152_send;
1465 eth->recv = r8152_recv;
1466 eth->halt = r8152_halt;
1467 eth->write_hwaddr = r8152_write_hwaddr;
1468 eth->priv = ss;
1469
1470
1471 if (r8152_read_mac(ss->dev_priv, eth->enetaddr) < 0)
1472 return 0;
1473
1474 debug("MAC %pM\n", eth->enetaddr);
1475 return 1;
1476}
1477#endif
1478
1479#ifdef CONFIG_DM_ETH
1480static int r8152_eth_start(struct udevice *dev)
1481{
1482 struct r8152 *tp = dev_get_priv(dev);
1483
1484 debug("** %s (%d)\n", __func__, __LINE__);
1485
1486 return r8152_init_common(tp);
1487}
1488
1489void r8152_eth_stop(struct udevice *dev)
1490{
1491 struct r8152 *tp = dev_get_priv(dev);
1492
1493 debug("** %s (%d)\n", __func__, __LINE__);
1494
1495 tp->rtl_ops.disable(tp);
1496}
1497
1498int r8152_eth_send(struct udevice *dev, void *packet, int length)
1499{
1500 struct r8152 *tp = dev_get_priv(dev);
1501
1502 return r8152_send_common(&tp->ueth, packet, length);
1503}
1504
1505int r8152_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1506{
1507 struct r8152 *tp = dev_get_priv(dev);
1508 struct ueth_data *ueth = &tp->ueth;
1509 uint8_t *ptr;
1510 int ret, len;
1511 struct rx_desc *rx_desc;
1512 u16 packet_len;
1513
1514 len = usb_ether_get_rx_bytes(ueth, &ptr);
1515 debug("%s: first try, len=%d\n", __func__, len);
1516 if (!len) {
1517 if (!(flags & ETH_RECV_CHECK_DEVICE))
1518 return -EAGAIN;
1519 ret = usb_ether_receive(ueth, RTL8152_AGG_BUF_SZ);
1520 if (ret)
1521 return ret;
1522
1523 len = usb_ether_get_rx_bytes(ueth, &ptr);
1524 debug("%s: second try, len=%d\n", __func__, len);
1525 }
1526
1527 rx_desc = (struct rx_desc *)ptr;
1528 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1529 packet_len -= CRC_SIZE;
1530
1531 if (packet_len > len - (sizeof(struct rx_desc) + CRC_SIZE)) {
1532 debug("Rx: too large packet: %d\n", packet_len);
1533 goto err;
1534 }
1535
1536 *packetp = ptr + sizeof(struct rx_desc);
1537 return packet_len;
1538
1539err:
1540 usb_ether_advance_rxbuf(ueth, -1);
1541 return -ENOSPC;
1542}
1543
1544static int r8152_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
1545{
1546 struct r8152 *tp = dev_get_priv(dev);
1547
1548 packet_len += sizeof(struct rx_desc) + CRC_SIZE;
1549 packet_len = ALIGN(packet_len, 8);
1550 usb_ether_advance_rxbuf(&tp->ueth, packet_len);
1551
1552 return 0;
1553}
1554
1555static int r8152_write_hwaddr(struct udevice *dev)
1556{
1557 struct eth_pdata *pdata = dev_get_platdata(dev);
1558 struct r8152 *tp = dev_get_priv(dev);
1559
1560 unsigned char enetaddr[8] = { 0 };
1561
1562 debug("** %s (%d)\n", __func__, __LINE__);
1563 memcpy(enetaddr, pdata->enetaddr, ETH_ALEN);
1564
1565 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1566 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
1567 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1568
1569 debug("MAC %pM\n", pdata->enetaddr);
1570 return 0;
1571}
1572
1573int r8152_read_rom_hwaddr(struct udevice *dev)
1574{
1575 struct eth_pdata *pdata = dev_get_platdata(dev);
1576 struct r8152 *tp = dev_get_priv(dev);
1577
1578 debug("** %s (%d)\n", __func__, __LINE__);
1579 r8152_read_mac(tp, pdata->enetaddr);
1580 return 0;
1581}
1582
1583static int r8152_eth_probe(struct udevice *dev)
1584{
1585 struct usb_device *udev = dev_get_parent_priv(dev);
1586 struct eth_pdata *pdata = dev_get_platdata(dev);
1587 struct r8152 *tp = dev_get_priv(dev);
1588 struct ueth_data *ueth = &tp->ueth;
1589 int ret;
1590
1591 tp->udev = udev;
1592 r8152_read_mac(tp, pdata->enetaddr);
1593
1594 r8152b_get_version(tp);
1595
1596 ret = rtl_ops_init(tp);
1597 if (ret)
1598 return ret;
1599
1600 tp->rtl_ops.init(tp);
1601 tp->rtl_ops.up(tp);
1602
1603 rtl8152_set_speed(tp, AUTONEG_ENABLE,
1604 tp->supports_gmii ? SPEED_1000 : SPEED_100,
1605 DUPLEX_FULL);
1606
1607 return usb_ether_register(dev, ueth, RTL8152_AGG_BUF_SZ);
1608}
1609
1610static const struct eth_ops r8152_eth_ops = {
1611 .start = r8152_eth_start,
1612 .send = r8152_eth_send,
1613 .recv = r8152_eth_recv,
1614 .free_pkt = r8152_free_pkt,
1615 .stop = r8152_eth_stop,
1616 .write_hwaddr = r8152_write_hwaddr,
1617 .read_rom_hwaddr = r8152_read_rom_hwaddr,
1618};
1619
1620U_BOOT_DRIVER(r8152_eth) = {
1621 .name = "r8152_eth",
1622 .id = UCLASS_ETH,
1623 .probe = r8152_eth_probe,
1624 .ops = &r8152_eth_ops,
1625 .priv_auto_alloc_size = sizeof(struct r8152),
1626 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1627};
1628
1629static const struct usb_device_id r8152_eth_id_table[] = {
1630
1631 { USB_DEVICE(0x0bda, 0x8050) },
1632 { USB_DEVICE(0x0bda, 0x8152) },
1633 { USB_DEVICE(0x0bda, 0x8153) },
1634
1635
1636 { USB_DEVICE(0x04e8, 0xa101) },
1637
1638
1639 { USB_DEVICE(0x17ef, 0x304f) },
1640 { USB_DEVICE(0x17ef, 0x3052) },
1641 { USB_DEVICE(0x17ef, 0x3054) },
1642 { USB_DEVICE(0x17ef, 0x3057) },
1643 { USB_DEVICE(0x17ef, 0x7205) },
1644 { USB_DEVICE(0x17ef, 0x720a) },
1645 { USB_DEVICE(0x17ef, 0x720b) },
1646 { USB_DEVICE(0x17ef, 0x720c) },
1647
1648
1649 { USB_DEVICE(0x2357, 0x0601) },
1650
1651
1652 { USB_DEVICE(0x0955, 0x09ff) },
1653
1654 { }
1655};
1656
1657U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table);
1658#endif
1659
1660
