1/* 2 * (C) Copyright 2001-2004 3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_405GP 1 /* This is a PPC405 CPU */ 21#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ 22#define CONFIG_CPCI405_VER2 1 /* ...version 2 */ 23#undef CONFIG_CPCI405_6U /* enable this for 6U boards */ 24 25#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 26 27#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ 28 29#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ 30 31#define CONFIG_BAUDRATE 9600 32 33#undef CONFIG_BOOTARGS 34#undef CONFIG_BOOTCOMMAND 35 36#define CONFIG_PREBOOT /* enable preboot variable */ 37 38#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 39#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 40 41#define CONFIG_PPC4xx_EMAC 42#define CONFIG_MII 1 /* MII PHY management */ 43#define CONFIG_PHY_ADDR 0 /* PHY address */ 44#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ 45#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ 46 47#undef CONFIG_HAS_ETH1 48 49#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ 50 51/* 52 * BOOTP options 53 */ 54#define CONFIG_BOOTP_SUBNETMASK 55#define CONFIG_BOOTP_GATEWAY 56#define CONFIG_BOOTP_HOSTNAME 57#define CONFIG_BOOTP_BOOTPATH 58#define CONFIG_BOOTP_DNS 59#define CONFIG_BOOTP_DNS2 60#define CONFIG_BOOTP_SEND_HOSTNAME 61 62/* 63 * Command line configuration. 64 */ 65#define CONFIG_CMD_PCI 66#define CONFIG_CMD_IRQ 67#define CONFIG_CMD_IDE 68#define CONFIG_CMD_DATE 69#define CONFIG_CMD_BSP 70#define CONFIG_CMD_EEPROM 71 72#define CONFIG_SUPPORT_VFAT 73 74#undef CONFIG_WATCHDOG /* watchdog disabled */ 75 76#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ 77 78/* 79 * Miscellaneous configurable options 80 */ 81#undef CONFIG_SYS_LONGHELP /* undef to save memory */ 82 83#if defined(CONFIG_CMD_KGDB) 84#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 85#else 86#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 87#endif 88#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 89#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 90#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 91 92#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 93 94#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ 95 96#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 97#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 98 99#define CONFIG_CONS_INDEX 1 /* Use UART0 */ 100#define CONFIG_SYS_NS16550_SERIAL 101#define CONFIG_SYS_NS16550_REG_SIZE 1 102#define CONFIG_SYS_NS16550_CLK get_serial_clock() 103 104#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ 105#define CONFIG_SYS_BASE_BAUD 691200 106 107#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 108#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 109 110#define CONFIG_CMDLINE_EDITING /* add command line history */ 111 112#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ 113 114/*----------------------------------------------------------------------- 115 * PCI stuff 116 *----------------------------------------------------------------------- 117 */ 118#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ 119#define PCI_HOST_FORCE 1 /* configure as pci host */ 120#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 121 122#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 123#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ 124 /* resource configuration */ 125 126#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ 127 128#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ 129 130#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ 131 132#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ 133#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ 134#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ 135#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ 136#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ 137#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ 138#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ 139#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ 140#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ 141#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */ 142 143#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ 144 145/*----------------------------------------------------------------------- 146 * IDE/ATA stuff 147 *----------------------------------------------------------------------- 148 */ 149#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ 150#undef CONFIG_IDE_LED /* no led for ide supported */ 151#define CONFIG_IDE_RESET 1 /* reset for ide supported */ 152 153#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ 154#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ 155 156#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 157#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 158 159#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ 160#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ 161#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ 162 163/*----------------------------------------------------------------------- 164 * Start addresses for the final memory configuration 165 * (Set up by the startup code) 166 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 167 */ 168#define CONFIG_SYS_SDRAM_BASE 0x00000000 169#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 170#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 171#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ 172#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ 173 174#define CONFIG_PRAM 0 /* use pram variable to overwrite */ 175 176/* 177 * For booting Linux, the board info and command line data 178 * have to be in the first 8 MB of memory, since this is 179 * the maximum mapped by the Linux kernel during initialization. 180 */ 181#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 182 183/*----------------------------------------------------------------------- 184 * FLASH organization 185 */ 186#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 187#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 188 189#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 190#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 191 192#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ 193#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ 194#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ 195/* 196 * The following defines are added for buggy IOP480 byte interface. 197 * All other boards should use the standard values (CPCI405 etc.) 198 */ 199#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ 200#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ 201#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ 202 203#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 204 205#if 0 /* Use NVRAM for environment variables */ 206/*----------------------------------------------------------------------- 207 * NVRAM organization 208 */ 209#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ 210#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ 211#define CONFIG_ENV_ADDR \ 212 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */ 213 214#else /* Use EEPROM for environment variables */ 215 216#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 217#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ 218#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ 219 /* total size of a CAT24WC16 is 2048 bytes */ 220#endif 221 222#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ 223#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ 224#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ 225 226/*----------------------------------------------------------------------- 227 * I2C EEPROM (CAT24WC16) for environment 228 */ 229#define CONFIG_SYS_I2C 230#define CONFIG_SYS_I2C_PPC4XX 231#define CONFIG_SYS_I2C_PPC4XX_CH0 232#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 233#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F 234 235#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ 236#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 237/* mask of address bits that overflow into the "EEPROM chip address" */ 238#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 239#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ 240 /* 16 byte page write mode using*/ 241 /* last 4 bits of the address */ 242#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 243 244/* 245 * Init Memory Controller: 246 * 247 * BR0/1 and OR0/1 (FLASH) 248 */ 249 250#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ 251#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ 252 253/*----------------------------------------------------------------------- 254 * External Bus Controller (EBC) Setup 255 */ 256 257/* Memory Bank 0 (Flash Bank 0) initialization */ 258#define CONFIG_SYS_EBC_PB0AP 0x92015480 259#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ 260 261/* Memory Bank 1 (Flash Bank 1) initialization */ 262#define CONFIG_SYS_EBC_PB1AP 0x92015480 263#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ 264 265/* Memory Bank 2 (CAN0, 1) initialization */ 266#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ 267#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ 268#define CONFIG_SYS_LED_ADDR 0xF0000380 269 270/* Memory Bank 3 (CompactFlash IDE) initialization */ 271#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ 272#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ 273 274/* Memory Bank 4 (NVRAM/RTC) initialization */ 275/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ 276#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ 277#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ 278 279/* Memory Bank 5 (optional Quart) initialization */ 280#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ 281#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ 282 283/* Memory Bank 6 (FPGA internal) initialization */ 284#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ 285#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ 286#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000 287 288/*----------------------------------------------------------------------- 289 * FPGA stuff 290 */ 291/* FPGA internal regs */ 292#define CONFIG_SYS_FPGA_MODE 0x00 293#define CONFIG_SYS_FPGA_STATUS 0x02 294#define CONFIG_SYS_FPGA_TS 0x04 295#define CONFIG_SYS_FPGA_TS_LOW 0x06 296#define CONFIG_SYS_FPGA_TS_CAP0 0x10 297#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 298#define CONFIG_SYS_FPGA_TS_CAP1 0x14 299#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 300#define CONFIG_SYS_FPGA_TS_CAP2 0x18 301#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a 302#define CONFIG_SYS_FPGA_TS_CAP3 0x1c 303#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e 304 305/* FPGA Mode Reg */ 306#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 307#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002 308#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ 309#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 310#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 311#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 312 313/* FPGA Status Reg */ 314#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 315#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 316#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 317#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 318#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 319 320#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ 321#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ 322 323/* FPGA program pin configuration */ 324#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ 325#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ 326#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ 327#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ 328#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ 329 330/*----------------------------------------------------------------------- 331 * Definitions for initial stack pointer and data area (in data cache) 332 */ 333#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ 334 335#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ 336#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ 337#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 338#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 339 340#endif /* __CONFIG_H */ 341