1/* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10/* 11 * board/config.h - configuration options, board specific 12 */ 13 14#ifndef _M5329EVB_H 15#define _M5329EVB_H 16 17/* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22#define CONFIG_MCFUART 23#define CONFIG_SYS_UART_PORT (0) 24#define CONFIG_BAUDRATE 115200 25 26#undef CONFIG_WATCHDOG 27#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 28 29/* Command line configuration */ 30#define CONFIG_CMD_DATE 31#define CONFIG_CMD_REGINFO 32 33#ifdef CONFIG_NANDFLASH_SIZE 34# define CONFIG_CMD_NAND 35#endif 36 37#define CONFIG_SYS_UNIFY_CACHE 38 39#define CONFIG_MCFFEC 40#ifdef CONFIG_MCFFEC 41# define CONFIG_MII 1 42# define CONFIG_MII_INIT 1 43# define CONFIG_SYS_DISCOVER_PHY 44# define CONFIG_SYS_RX_ETH_BUFFER 8 45# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 46 47# define CONFIG_SYS_FEC0_PINMUX 0 48# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 49# define MCFFEC_TOUT_LOOP 50000 50/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 51# ifndef CONFIG_SYS_DISCOVER_PHY 52# define FECDUPLEX FULL 53# define FECSPEED _100BASET 54# else 55# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 56# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 57# endif 58# endif /* CONFIG_SYS_DISCOVER_PHY */ 59#endif 60 61#define CONFIG_MCFRTC 62#undef RTC_DEBUG 63 64/* Timer */ 65#define CONFIG_MCFTMR 66#undef CONFIG_MCFPIT 67 68/* I2C */ 69#define CONFIG_SYS_I2C 70#define CONFIG_SYS_I2C_FSL 71#define CONFIG_SYS_FSL_I2C_SPEED 80000 72#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 73#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 74#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 75 76#define CONFIG_UDP_CHECKSUM 77 78#ifdef CONFIG_MCFFEC 79# define CONFIG_IPADDR 192.162.1.2 80# define CONFIG_NETMASK 255.255.255.0 81# define CONFIG_SERVERIP 192.162.1.1 82# define CONFIG_GATEWAYIP 192.162.1.1 83#endif /* FEC_ENET */ 84 85#define CONFIG_HOSTNAME M5329EVB 86#define CONFIG_EXTRA_ENV_SETTINGS \ 87 "netdev=eth0\0" \ 88 "loadaddr=40010000\0" \ 89 "u-boot=u-boot.bin\0" \ 90 "load=tftp ${loadaddr) ${u-boot}\0" \ 91 "upd=run load; run prog\0" \ 92 "prog=prot off 0 3ffff;" \ 93 "era 0 3ffff;" \ 94 "cp.b ${loadaddr} 0 ${filesize};" \ 95 "save\0" \ 96 "" 97 98#define CONFIG_PRAM 512 /* 512 KB */ 99#define CONFIG_SYS_LONGHELP /* undef to save memory */ 100 101#ifdef CONFIG_CMD_KGDB 102# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 103#else 104# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 105#endif 106 107#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 108#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 109#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 110#define CONFIG_SYS_LOAD_ADDR 0x40010000 111 112#define CONFIG_SYS_CLK 80000000 113#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 114 115#define CONFIG_SYS_MBAR 0xFC000000 116 117#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) 118 119/* 120 * Low Level Configuration Settings 121 * (address mappings, register initial values, etc.) 122 * You should know what you are doing if you make changes here. 123 */ 124/*----------------------------------------------------------------------- 125 * Definitions for initial stack pointer and data area (in DPRAM) 126 */ 127#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 128#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 129#define CONFIG_SYS_INIT_RAM_CTRL 0x221 130#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 131#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 132 133/*----------------------------------------------------------------------- 134 * Start addresses for the final memory configuration 135 * (Set up by the startup code) 136 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 137 */ 138#define CONFIG_SYS_SDRAM_BASE 0x40000000 139#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 140#define CONFIG_SYS_SDRAM_CFG1 0x53722730 141#define CONFIG_SYS_SDRAM_CFG2 0x56670000 142#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 143#define CONFIG_SYS_SDRAM_EMOD 0x40010000 144#define CONFIG_SYS_SDRAM_MODE 0x018D0000 145 146#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 147#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 148 149#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 150#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 151 152#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 153#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 154 155/* 156 * For booting Linux, the board info and command line data 157 * have to be in the first 8 MB of memory, since this is 158 * the maximum mapped by the Linux kernel during initialization ?? 159 */ 160#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 161#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 162 163/*----------------------------------------------------------------------- 164 * FLASH organization 165 */ 166#define CONFIG_SYS_FLASH_CFI 167#ifdef CONFIG_SYS_FLASH_CFI 168# define CONFIG_FLASH_CFI_DRIVER 1 169# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 170# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 171# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 172# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 173# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 174#endif 175 176#ifdef CONFIG_NANDFLASH_SIZE 177# define CONFIG_SYS_MAX_NAND_DEVICE 1 178# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE 179# define CONFIG_SYS_NAND_SIZE 1 180# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 181# define NAND_ALLOW_ERASE_ALL 1 182# define CONFIG_JFFS2_NAND 1 183# define CONFIG_JFFS2_DEV "nand0" 184# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) 185# define CONFIG_JFFS2_PART_OFFSET 0x00000000 186#endif 187 188#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 189 190/* Configuration for environment 191 * Environment is embedded in u-boot in the second sector of the flash 192 */ 193#define CONFIG_ENV_OFFSET 0x4000 194#define CONFIG_ENV_SECT_SIZE 0x2000 195#define CONFIG_ENV_IS_IN_FLASH 1 196 197#define LDS_BOARD_TEXT \ 198 . = DEFINED(env_offset) ? env_offset : .; \ 199 common/env_embedded.o (.text*); 200 201/*----------------------------------------------------------------------- 202 * Cache Configuration 203 */ 204#define CONFIG_SYS_CACHELINE_SIZE 16 205 206#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 207 CONFIG_SYS_INIT_RAM_SIZE - 8) 208#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 209 CONFIG_SYS_INIT_RAM_SIZE - 4) 210#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 211#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 212 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 213 CF_ACR_EN | CF_ACR_SM_ALL) 214#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 215 CF_CACR_DCM_P) 216 217/*----------------------------------------------------------------------- 218 * Chipselect bank definitions 219 */ 220/* 221 * CS0 - NOR Flash 1, 2, 4, or 8MB 222 * CS1 - CompactFlash and registers 223 * CS2 - NAND Flash 16, 32, or 64MB 224 * CS3 - Available 225 * CS4 - Available 226 * CS5 - Available 227 */ 228#define CONFIG_SYS_CS0_BASE 0 229#define CONFIG_SYS_CS0_MASK 0x007f0001 230#define CONFIG_SYS_CS0_CTRL 0x00001fa0 231 232#define CONFIG_SYS_CS1_BASE 0x10000000 233#define CONFIG_SYS_CS1_MASK 0x001f0001 234#define CONFIG_SYS_CS1_CTRL 0x002A3780 235 236#ifdef CONFIG_NANDFLASH_SIZE 237#define CONFIG_SYS_CS2_BASE 0x20000000 238#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) 239#define CONFIG_SYS_CS2_CTRL 0x00001f60 240#endif 241 242#endif /* _M5329EVB_H */ 243