1/* 2 * (C) Copyright 2001, 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/*********************************************************** 16 * High Level Configuration Options 17 * (easy to change) 18 ***********************************************************/ 19#define CONFIG_405GP 1 /* This is a PPC405 CPU */ 20 21#define CONFIG_SYS_TEXT_BASE 0xFFF80000 22 23/*********************************************************** 24 * Note that it may also be a MIP405T board which is a subset of the 25 * MIP405 26 ***********************************************************/ 27/*********************************************************** 28 * WARNING: 29 * CONFIG_BOOT_PCI is only used for first boot-up and should 30 * NOT be enabled for production bootloader 31 ***********************************************************/ 32/*#define CONFIG_BOOT_PCI 1*/ 33/*********************************************************** 34 * Clock 35 ***********************************************************/ 36#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ 37 38/* 39 * BOOTP options 40 */ 41#define CONFIG_BOOTP_BOOTFILESIZE 42#define CONFIG_BOOTP_BOOTPATH 43#define CONFIG_BOOTP_GATEWAY 44#define CONFIG_BOOTP_HOSTNAME 45 46/* 47 * Command line configuration. 48 */ 49#define CONFIG_CMD_DATE 50#define CONFIG_CMD_EEPROM 51#define CONFIG_CMD_IDE 52#define CONFIG_CMD_IRQ 53#define CONFIG_CMD_JFFS2 54#define CONFIG_CMD_PCI 55#define CONFIG_CMD_REGINFO 56#define CONFIG_CMD_SAVES 57#define CONFIG_CMD_BSP 58 59/************************************************************** 60 * I2C Stuff: 61 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address 62 * 0x53. 63 * The Atmel EEPROM uses 16Bit addressing. 64 ***************************************************************/ 65 66#define CONFIG_SYS_I2C 67#define CONFIG_SYS_I2C_PPC4XX 68#define CONFIG_SYS_I2C_PPC4XX_CH0 69#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000 70#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F 71 72#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */ 73#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ 74/* mask of address bits that overflow into the "EEPROM chip address" */ 75#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 76#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */ 77 /* 64 byte page write mode using*/ 78 /* last 6 bits of the address */ 79#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 80 81#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 82#define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */ 83#define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */ 84 85/*************************************************************** 86 * Definitions for Serial Presence Detect EEPROM address 87 * (to get SDRAM settings) 88 ***************************************************************/ 89/*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0 90#define SDRAM_EEPROM_READ_ADDRESS 0xA1 91*/ 92/************************************************************** 93 * Environment definitions 94 **************************************************************/ 95#define CONFIG_BAUDRATE 9600 /* STD Baudrate */ 96/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ 97/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ 98 99#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ 100#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ 101 102#define CONFIG_IPADDR 10.0.0.100 103#define CONFIG_SERVERIP 10.0.0.1 104#define CONFIG_PREBOOT 105/*************************************************************** 106 * defines if an overwrite_console function exists 107 *************************************************************/ 108/*************************************************************** 109 * defines if the overwrite_console should be stored in the 110 * environment 111 **************************************************************/ 112 113/************************************************************** 114 * loads config 115 *************************************************************/ 116#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 117#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 118 119#define CONFIG_MISC_INIT_R 120/*********************************************************** 121 * Miscellaneous configurable options 122 **********************************************************/ 123#define CONFIG_SYS_LONGHELP /* undef to save memory */ 124#if defined(CONFIG_CMD_KGDB) 125#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 126#else 127#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 128#endif 129#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 130#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 131#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 132 133#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ 134#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ 135 136#define CONFIG_CONS_INDEX 1 /* Use UART0 */ 137#define CONFIG_SYS_NS16550_SERIAL 138#define CONFIG_SYS_NS16550_REG_SIZE 1 139#define CONFIG_SYS_NS16550_CLK get_serial_clock() 140 141#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ 142#define CONFIG_SYS_BASE_BAUD 916667 143 144/* The following table includes the supported baudrates */ 145#define CONFIG_SYS_BAUDRATE_TABLE \ 146 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 147 57600, 115200, 230400, 460800, 921600 } 148 149#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ 150#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 151 152/*----------------------------------------------------------------------- 153 * PCI stuff 154 *----------------------------------------------------------------------- 155 */ 156#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ 157#define PCI_HOST_FORCE 1 /* configure as pci host */ 158#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 159 160#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 161#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */ 162 /* resource configuration */ 163#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ 164#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ 165#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ 166#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ 167#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ 168#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ 169#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ 170#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ 171 172/*----------------------------------------------------------------------- 173 * Start addresses for the final memory configuration 174 * (Set up by the startup code) 175 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 176 */ 177#define CONFIG_SYS_SDRAM_BASE 0x00000000 178#define CONFIG_SYS_FLASH_BASE 0xFFF80000 179#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 180#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ 181#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ 182 183/* 184 * For booting Linux, the board info and command line data 185 * have to be in the first 8 MB of memory, since this is 186 * the maximum mapped by the Linux kernel during initialization. 187 */ 188#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 189/*----------------------------------------------------------------------- 190 * FLASH organization 191 */ 192#define CONFIG_SYS_UPDATE_FLASH_SIZE 193#define CONFIG_SYS_FLASH_PROTECTION 194#define CONFIG_SYS_FLASH_EMPTY_INFO 195 196#define CONFIG_SYS_FLASH_CFI 197#define CONFIG_FLASH_CFI_DRIVER 198 199#define CONFIG_FLASH_SHOW_PROGRESS 45 200 201#define CONFIG_SYS_MAX_FLASH_BANKS 1 202#define CONFIG_SYS_MAX_FLASH_SECT 256 203 204/* 205 * JFFS2 partitions 206 * 207 */ 208/* No command line, one static partition, whole device */ 209#undef CONFIG_CMD_MTDPARTS 210#define CONFIG_JFFS2_DEV "nor0" 211#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF 212#define CONFIG_JFFS2_PART_OFFSET 0x00000000 213 214/* mtdparts command line support */ 215/* Note: fake mtd_id used, no linux mtd map file */ 216/* 217#define CONFIG_CMD_MTDPARTS 218#define MTDIDS_DEFAULT "nor0=mip405-0" 219#define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)" 220*/ 221 222/*----------------------------------------------------------------------- 223 * Logbuffer Configuration 224 */ 225#undef CONFIG_LOGBUFFER /* supported but not enabled */ 226/*----------------------------------------------------------------------- 227 * Bootcountlimit Configuration 228 */ 229#undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */ 230 231/*----------------------------------------------------------------------- 232 * POST Configuration 233 */ 234#if 0 /* enable this if POST is desired (is supported but not enabled) */ 235#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 236 CONFIG_SYS_POST_CPU | \ 237 CONFIG_SYS_POST_RTC | \ 238 CONFIG_SYS_POST_I2C) 239 240#endif 241/* 242 * Init Memory Controller: 243 */ 244#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */ 245#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */ 246/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ 247#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */ 248 249#define CONFIG_BOARD_EARLY_INIT_R 250 251/* Peripheral Bus Mapping */ 252#define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/ 253#define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/ 254#define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/ 255 256#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 257#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 258 259/*----------------------------------------------------------------------- 260 * Definitions for initial stack pointer and data area (in On Chip SRAM) 261 */ 262#define CONFIG_SYS_TEMP_STACK_OCM 1 263#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000 264#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 265#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */ 266#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */ 267#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 268/* reserve some memory for POST and BOOT limit info */ 269#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) 270 271#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */ 272#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12) 273#endif 274 275/*********************************************************************** 276 * External peripheral base address 277 ***********************************************************************/ 278#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000 279 280/*********************************************************************** 281 * Last Stage Init 282 ***********************************************************************/ 283#define CONFIG_LAST_STAGE_INIT 284/************************************************************ 285 * Ethernet Stuff 286 ***********************************************************/ 287#define CONFIG_PPC4xx_EMAC 288#define CONFIG_MII 1 /* MII PHY management */ 289#define CONFIG_PHY_ADDR 1 /* PHY address */ 290#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ 291#define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */ 292/************************************************************ 293 * RTC 294 ***********************************************************/ 295#define CONFIG_RTC_MC146818 296#undef CONFIG_WATCHDOG /* watchdog disabled */ 297 298/************************************************************ 299 * IDE/ATA stuff 300 ************************************************************/ 301#if defined(CONFIG_TARGET_MIP405T) 302#define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */ 303#else 304#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ 305#endif 306 307#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ 308 309#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */ 310#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ 311#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ 312#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ 313#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ 314#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ 315 316#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ 317#undef CONFIG_IDE_LED /* no led for ide supported */ 318#define CONFIG_IDE_RESET /* reset for ide supported... */ 319#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ 320#define CONFIG_SUPPORT_VFAT 321/************************************************************ 322 * ATAPI support (experimental) 323 ************************************************************/ 324#define CONFIG_ATAPI /* enable ATAPI Support */ 325 326/************************************************************ 327 * DISK Partition support 328 ************************************************************/ 329 330/************************************************************ 331 * Video support 332 ************************************************************/ 333#define CONFIG_VIDEO_LOGO 334#undef CONFIG_VIDEO_ONBOARD 335/************************************************************ 336 * USB support EXPERIMENTAL 337 ************************************************************/ 338#if !defined(CONFIG_TARGET_MIP405T) 339#define CONFIG_USB_UHCI 340 341/* Enable needed helper functions */ 342#endif 343/************************************************************ 344 * Debug support 345 ************************************************************/ 346#if defined(CONFIG_CMD_KGDB) 347#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 348#endif 349 350/************************************************************ 351 * support BZIP2 compression 352 ************************************************************/ 353#define CONFIG_BZIP2 1 354 355#endif /* __CONFIG_H */ 356