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8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12
13
14
15#define CONFIG_E300 1
16#define CONFIG_MPC830x 1
17#define CONFIG_MPC8308 1
18#define CONFIG_MPC8308RDB 1
19
20#define CONFIG_SYS_TEXT_BASE 0xFE000000
21
22#define CONFIG_MISC_INIT_R
23
24#ifdef CONFIG_MMC
25#define CONFIG_FSL_ESDHC
26#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
27#define CONFIG_SYS_FSL_ESDHC_USE_PIO
28#endif
29
30
31
32
33
34
35
36#define CONFIG_TSEC1
37#define CONFIG_VSC7385_ENET
38
39
40
41
42#define CONFIG_83XX_CLKIN 33333333
43#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
44
45
46
47
48
49
50
51#define CONFIG_SYS_HRCW_LOW (\
52 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
53 HRCWL_DDR_TO_SCB_CLK_2X1 |\
54 HRCWL_SVCOD_DIV_2 |\
55 HRCWL_CSB_TO_CLKIN_4X1 |\
56 HRCWL_CORE_TO_CSB_3X1)
57
58
59
60
61
62
63
64#define CONFIG_SYS_HRCW_HIGH (\
65 HRCWH_PCI_HOST |\
66 HRCWH_PCI1_ARBITER_ENABLE |\
67 HRCWH_CORE_ENABLE |\
68 HRCWH_FROM_0X00000100 |\
69 HRCWH_BOOTSEQ_DISABLE |\
70 HRCWH_SW_WATCHDOG_DISABLE |\
71 HRCWH_ROM_LOC_LOCAL_16BIT |\
72 HRCWH_RL_EXT_LEGACY |\
73 HRCWH_TSEC1M_IN_RGMII |\
74 HRCWH_TSEC2M_IN_RGMII |\
75 HRCWH_BIG_ENDIAN)
76
77
78
79
80#define CONFIG_SYS_SICRH (\
81 SICRH_ESDHC_A_SD |\
82 SICRH_ESDHC_B_SD |\
83 SICRH_ESDHC_C_SD |\
84 SICRH_GPIO_A_TSEC2 |\
85 SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
86 SICRH_IEEE1588_A_GPIO |\
87 SICRH_USB |\
88 SICRH_GTM_GPIO |\
89 SICRH_IEEE1588_B_GPIO |\
90 SICRH_ETSEC2_CRS |\
91 SICRH_GPIOSEL_1 |\
92 SICRH_TMROBI_V3P3 |\
93 SICRH_TSOBI1_V2P5 |\
94 SICRH_TSOBI2_V2P5)
95#define CONFIG_SYS_SICRL (\
96 SICRL_SPI_PF0 |\
97 SICRL_UART_PF0 |\
98 SICRL_IRQ_PF0 |\
99 SICRL_I2C2_PF0 |\
100 SICRL_ETSEC1_GTX_CLK125)
101
102
103
104
105#define CONFIG_SYS_IMMR 0xE0000000
106
107
108
109
110#define CONFIG_FSL_SERDES
111#define CONFIG_FSL_SERDES1 0xe3000
112
113
114
115
116#define CONFIG_SYS_ACR_PIPE_DEP 3
117#define CONFIG_SYS_ACR_RPTCNT 3
118#define CONFIG_SYS_SPCR_TSECEP 3
119
120
121
122
123#define CONFIG_SYS_DDR_BASE 0x00000000
124#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
125#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
126#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
127#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
128 | DDRCDR_PZ_LOZ \
129 | DDRCDR_NZ_LOZ \
130 | DDRCDR_ODT \
131 | DDRCDR_Q_DRN)
132
133
134
135
136
137
138#define CONFIG_SYS_DDR_SIZE 128
139
140#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
141#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
142 | CSCONFIG_ODT_RD_NEVER \
143 | CSCONFIG_ODT_WR_ONLY_CURRENT \
144 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
145
146#define CONFIG_SYS_DDR_TIMING_3 0x00000000
147#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
148 | (0 << TIMING_CFG0_WRT_SHIFT) \
149 | (0 << TIMING_CFG0_RRT_SHIFT) \
150 | (0 << TIMING_CFG0_WWT_SHIFT) \
151 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
152 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
153 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
154 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
155
156#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
157 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
158 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
159 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
160 | (6 << TIMING_CFG1_REFREC_SHIFT) \
161 | (2 << TIMING_CFG1_WRREC_SHIFT) \
162 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
163 | (2 << TIMING_CFG1_WRTORD_SHIFT))
164
165#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
166 | (4 << TIMING_CFG2_CPO_SHIFT) \
167 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
168 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
169 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
170 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
171 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
172
173#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
174 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
175
176#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
177 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
178 | SDRAM_CFG_DBW_32)
179
180
181#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
182#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
183 | (0x0232 << SDRAM_MODE_SD_SHIFT))
184
185#define CONFIG_SYS_DDR_MODE2 0x00000000
186
187
188
189
190#define CONFIG_SYS_MEMTEST_START 0x00001000
191#define CONFIG_SYS_MEMTEST_END 0x07f00000
192
193
194
195
196#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
197
198#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
199#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
200
201
202
203
204#define CONFIG_SYS_INIT_RAM_LOCK 1
205#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
206#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
207#define CONFIG_SYS_GBL_DATA_OFFSET \
208 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
209
210
211
212
213#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
214#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
215#define CONFIG_SYS_LBC_LBCR 0x00040000
216
217
218
219
220#define CONFIG_SYS_FLASH_CFI
221#define CONFIG_FLASH_CFI_DRIVER
222#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
223
224#define CONFIG_SYS_FLASH_BASE 0xFE000000
225#define CONFIG_SYS_FLASH_SIZE 8
226#define CONFIG_SYS_FLASH_PROTECTION 1
227
228
229#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
230#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
231
232#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
233 | BR_PS_16 \
234 | BR_MS_GPCM \
235 | BR_V)
236#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
237 | OR_UPM_XAM \
238 | OR_GPCM_CSNT \
239 | OR_GPCM_ACS_DIV2 \
240 | OR_GPCM_XACS \
241 | OR_GPCM_SCY_15 \
242 | OR_GPCM_TRLX_SET \
243 | OR_GPCM_EHTR_SET)
244
245#define CONFIG_SYS_MAX_FLASH_BANKS 1
246
247#define CONFIG_SYS_MAX_FLASH_SECT 135
248
249#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
250#define CONFIG_SYS_FLASH_WRITE_TOUT 500
251
252
253
254
255#define CONFIG_SYS_NAND_BASE 0xE0600000
256#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
257#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
258 | BR_DECC_CHK_GEN \
259 | BR_PS_8 \
260 | BR_MS_FCM \
261 | BR_V)
262#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
263 | OR_FCM_CSCT \
264 | OR_FCM_CST \
265 | OR_FCM_CHT \
266 | OR_FCM_SCY_1 \
267 | OR_FCM_TRLX \
268 | OR_FCM_EHTR)
269
270
271#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
272#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
273
274#ifdef CONFIG_VSC7385_ENET
275#define CONFIG_TSEC2
276
277#define CONFIG_SYS_VSC7385_BASE 0xF0000000
278#define CONFIG_SYS_VSC7385_SIZE (128 * 1024)
279#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
280 | BR_PS_8 \
281 | BR_MS_GPCM \
282 | BR_V)
283
284#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
285 | OR_GPCM_CSNT \
286 | OR_GPCM_XACS \
287 | OR_GPCM_SCY_15 \
288 | OR_GPCM_SETA \
289 | OR_GPCM_TRLX_SET \
290 | OR_GPCM_EHTR_SET)
291
292
293#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
294
295#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
296
297#define CONFIG_VSC7385_IMAGE 0xFE7FE000
298#define CONFIG_VSC7385_IMAGE_SIZE 8192
299#endif
300
301
302
303#define CONFIG_CONS_INDEX 1
304#define CONFIG_SYS_NS16550_SERIAL
305#define CONFIG_SYS_NS16550_REG_SIZE 1
306#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
307
308#define CONFIG_SYS_BAUDRATE_TABLE \
309 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
310
311#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
312#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
313
314
315#define CONFIG_SYS_I2C
316#define CONFIG_SYS_I2C_FSL
317#define CONFIG_SYS_FSL_I2C_SPEED 400000
318#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
319#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
320#define CONFIG_SYS_FSL_I2C2_SPEED 400000
321#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
322#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
323#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
324
325
326
327
328
329
330
331#ifdef CONFIG_MPC8XXX_SPI
332#define CONFIG_USE_SPIFLASH
333#endif
334
335
336
337
338#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
339
340
341
342
343#define CONFIG_RTC_DS1337
344#define CONFIG_SYS_I2C_RTC_ADDR 0x68
345
346
347
348
349
350#define CONFIG_SYS_PCIE1_BASE 0xA0000000
351#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
352#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
353#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
354#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
355#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
356#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
357#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
358#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
359
360
361#define CONFIG_SYS_SCCR_PCIEXP1CM 1
362
363#define CONFIG_PCI_INDIRECT_BRIDGE
364#define CONFIG_PCIE
365
366#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
367#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
368
369
370
371
372#define CONFIG_TSEC_ENET
373#define CONFIG_SYS_TSEC1_OFFSET 0x24000
374#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
375#define CONFIG_SYS_TSEC2_OFFSET 0x25000
376#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
377
378
379
380
381#define CONFIG_MII 1
382#define CONFIG_TSEC1_NAME "eTSEC0"
383#define CONFIG_TSEC2_NAME "eTSEC1"
384#define TSEC1_PHY_ADDR 2
385#define TSEC2_PHY_ADDR 1
386#define TSEC1_PHYIDX 0
387#define TSEC2_PHYIDX 0
388#define TSEC1_FLAGS TSEC_GIGABIT
389#define TSEC2_FLAGS TSEC_GIGABIT
390
391
392#define CONFIG_ETHPRIME "eTSEC0"
393
394
395
396
397#define CONFIG_ENV_IS_IN_FLASH 1
398#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
399 CONFIG_SYS_MONITOR_LEN)
400#define CONFIG_ENV_SECT_SIZE 0x10000
401#define CONFIG_ENV_SIZE 0x2000
402#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
403#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
404
405#define CONFIG_LOADS_ECHO 1
406#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
407
408
409
410
411#define CONFIG_BOOTP_BOOTFILESIZE
412#define CONFIG_BOOTP_BOOTPATH
413#define CONFIG_BOOTP_GATEWAY
414#define CONFIG_BOOTP_HOSTNAME
415
416
417
418
419#define CONFIG_CMD_DATE
420#define CONFIG_CMD_PCI
421
422#define CONFIG_CMDLINE_EDITING 1
423
424
425
426
427#define CONFIG_SYS_LONGHELP
428#define CONFIG_SYS_LOAD_ADDR 0x2000000
429
430#define CONFIG_SYS_CBSIZE 1024
431
432
433#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
434#define CONFIG_SYS_MAXARGS 16
435
436#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
437
438
439
440
441
442
443#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
444#define CONFIG_SYS_BOOTM_LEN (64 << 20)
445
446
447
448
449#define CONFIG_SYS_HID0_INIT 0x000000000
450#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
451 HID0_ENABLE_INSTRUCTION_CACHE | \
452 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
453#define CONFIG_SYS_HID2 HID2_HBE
454
455
456
457
458
459
460#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
461 BATL_MEMCOHERENCE)
462#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
463 BATU_VS | BATU_VP)
464#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
465#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
466
467
468#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
469 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
470#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
471 BATU_VP)
472#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
473#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
474
475
476#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
477 BATL_MEMCOHERENCE)
478#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
479 BATU_VS | BATU_VP)
480#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
481 BATL_CACHEINHIBIT | \
482 BATL_GUARDEDSTORAGE)
483#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
484
485
486#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
487#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
488 BATU_VS | BATU_VP)
489#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
490#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
491
492
493
494
495
496#define CONFIG_ENV_OVERWRITE
497
498#if defined(CONFIG_TSEC_ENET)
499#define CONFIG_HAS_ETH0
500#define CONFIG_HAS_ETH1
501#endif
502
503#define CONFIG_BAUDRATE 115200
504
505#define CONFIG_LOADADDR 800000
506
507
508#define CONFIG_EXTRA_ENV_SETTINGS \
509 "netdev=eth0\0" \
510 "consoledev=ttyS0\0" \
511 "nfsargs=setenv bootargs root=/dev/nfs rw " \
512 "nfsroot=${serverip}:${rootpath}\0" \
513 "ramargs=setenv bootargs root=/dev/ram rw\0" \
514 "addip=setenv bootargs ${bootargs} " \
515 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
516 ":${hostname}:${netdev}:off panic=1\0" \
517 "addtty=setenv bootargs ${bootargs}" \
518 " console=${consoledev},${baudrate}\0" \
519 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
520 "addmisc=setenv bootargs ${bootargs}\0" \
521 "kernel_addr=FE080000\0" \
522 "fdt_addr=FE280000\0" \
523 "ramdisk_addr=FE290000\0" \
524 "u-boot=mpc8308rdb/u-boot.bin\0" \
525 "kernel_addr_r=1000000\0" \
526 "fdt_addr_r=C00000\0" \
527 "hostname=mpc8308rdb\0" \
528 "bootfile=mpc8308rdb/uImage\0" \
529 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
530 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
531 "flash_self=run ramargs addip addtty addmtd addmisc;" \
532 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
533 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
534 "bootm ${kernel_addr} - ${fdt_addr}\0" \
535 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
536 "tftp ${fdt_addr_r} ${fdtfile};" \
537 "run nfsargs addip addtty addmtd addmisc;" \
538 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
539 "bootcmd=run flash_self\0" \
540 "load=tftp ${loadaddr} ${u-boot}\0" \
541 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
542 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
543 " +${filesize};cp.b ${fileaddr} " \
544 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
545 "upd=run load update\0" \
546
547#endif
548