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9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13
14
15
16#define CONFIG_E300 1
17#define CONFIG_MPC831x 1
18#define CONFIG_MPC8313 1
19#define CONFIG_MPC8313ERDB 1
20
21#ifdef CONFIG_NAND
22#define CONFIG_SPL_INIT_MINIMAL
23#define CONFIG_SPL_FLUSH_IMAGE
24#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
25#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
26
27#ifdef CONFIG_SPL_BUILD
28#define CONFIG_NS16550_MIN_FUNCTIONS
29#endif
30
31#define CONFIG_SYS_TEXT_BASE 0x00100000
32#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
33#define CONFIG_SPL_MAX_SIZE (4 * 1024)
34#define CONFIG_SPL_PAD_TO 0x4000
35
36#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
37#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
38#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
39#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
40#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
41#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
42
43#ifdef CONFIG_SPL_BUILD
44#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL
45#endif
46
47#endif
48
49#ifndef CONFIG_SYS_TEXT_BASE
50#define CONFIG_SYS_TEXT_BASE 0xFE000000
51#endif
52
53#ifndef CONFIG_SYS_MONITOR_BASE
54#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
55#endif
56
57#define CONFIG_PCI_INDIRECT_BRIDGE
58#define CONFIG_FSL_ELBC 1
59
60#define CONFIG_MISC_INIT_R
61
62
63
64
65
66
67
68#define CONFIG_VSC7385_ENET
69#define CONFIG_TSEC2
70
71#ifdef CONFIG_SYS_66MHZ
72#define CONFIG_83XX_CLKIN 66666667
73#elif defined(CONFIG_SYS_33MHZ)
74#define CONFIG_83XX_CLKIN 33333333
75#else
76#error Unknown oscillator frequency.
77#endif
78
79#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
80
81#define CONFIG_BOARD_EARLY_INIT_R
82
83#define CONFIG_SYS_IMMR 0xE0000000
84
85#if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
86#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
87#endif
88
89#define CONFIG_SYS_MEMTEST_START 0x00001000
90#define CONFIG_SYS_MEMTEST_END 0x07f00000
91
92
93
94
95
96#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
97
98#define CONFIG_SYS_ACR_PIPE_DEP 3
99#define CONFIG_SYS_ACR_RPTCNT 3
100
101
102
103
104
105
106
107#ifdef CONFIG_VSC7385_ENET
108
109#define CONFIG_TSEC1
110
111
112#define CONFIG_VSC7385_IMAGE 0xFE7FE000
113#define CONFIG_VSC7385_IMAGE_SIZE 8192
114
115#endif
116
117
118
119
120#define CONFIG_SYS_DDR_BASE 0x00000000
121#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
122#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
123
124
125
126
127
128#define CONFIG_SYS_DDR_SIZE 128
129#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
130 | CSCONFIG_ODT_RD_NEVER \
131 | CSCONFIG_ODT_WR_ONLY_CURRENT \
132 | CSCONFIG_ROW_BIT_13 \
133 | CSCONFIG_COL_BIT_10)
134
135
136#define CONFIG_SYS_DDR_TIMING_3 0x00000000
137#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
138 | (0 << TIMING_CFG0_WRT_SHIFT) \
139 | (0 << TIMING_CFG0_RRT_SHIFT) \
140 | (0 << TIMING_CFG0_WWT_SHIFT) \
141 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
142 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
143 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
144 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
145
146#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
147 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
148 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
149 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
150 | (10 << TIMING_CFG1_REFREC_SHIFT) \
151 | (3 << TIMING_CFG1_WRREC_SHIFT) \
152 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
153 | (2 << TIMING_CFG1_WRTORD_SHIFT))
154
155#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
156 | (5 << TIMING_CFG2_CPO_SHIFT) \
157 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
158 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
159 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
160 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
161 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
162
163#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
164 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
165
166#if defined(CONFIG_DDR_2T_TIMING)
167#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
168 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
169 | SDRAM_CFG_DBW_32 \
170 | SDRAM_CFG_2T_EN)
171
172#else
173#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
174 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
175 | SDRAM_CFG_DBW_32)
176
177#endif
178#define CONFIG_SYS_SDRAM_CFG2 0x00401000
179
180#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
181 | (0x0632 << SDRAM_MODE_SD_SHIFT))
182
183#define CONFIG_SYS_DDR_MODE_2 0x8000C000
184
185#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
186
187#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
188 | DDRCDR_PZ_NOMZ \
189 | DDRCDR_NZ_NOMZ \
190 | DDRCDR_M_ODR)
191
192
193
194
195#define CONFIG_SYS_FLASH_CFI
196#define CONFIG_FLASH_CFI_DRIVER
197#define CONFIG_SYS_FLASH_BASE 0xFE000000
198#define CONFIG_SYS_FLASH_SIZE 8
199#define CONFIG_SYS_FLASH_PROTECTION 1
200#define CONFIG_SYS_FLASH_EMPTY_INFO
201#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
202
203#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
204 | BR_PS_16 \
205 | BR_MS_GPCM \
206 | BR_V)
207#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
208 | OR_GPCM_XACS \
209 | OR_GPCM_SCY_9 \
210 | OR_GPCM_EHTR \
211 | OR_GPCM_EAD)
212
213
214#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
215
216#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
217
218#define CONFIG_SYS_MAX_FLASH_BANKS 1
219#define CONFIG_SYS_MAX_FLASH_SECT 135
220
221#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
222#define CONFIG_SYS_FLASH_WRITE_TOUT 500
223
224#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
225 !defined(CONFIG_SPL_BUILD)
226#define CONFIG_SYS_RAMBOOT
227#endif
228
229#define CONFIG_SYS_INIT_RAM_LOCK 1
230#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
231#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
232
233#define CONFIG_SYS_GBL_DATA_OFFSET \
234 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
235#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
236
237
238#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
239#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
240
241
242
243
244#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
245#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
246#define CONFIG_SYS_LBC_LBCR (0x00040000 \
247 | (0xFF << LBCR_BMT_SHIFT) \
248 | 0xF)
249
250
251#define CONFIG_SYS_LBC_MRTPR 0x20000000
252
253
254#if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
255#define CONFIG_SYS_NAND_BASE 0xFFF00000
256#else
257#define CONFIG_SYS_NAND_BASE 0xE2800000
258#endif
259
260#define CONFIG_MTD_DEVICE
261#define CONFIG_MTD_PARTITION
262#define CONFIG_CMD_MTDPARTS
263#define MTDIDS_DEFAULT "nand0=e2800000.flash"
264#define MTDPARTS_DEFAULT \
265 "mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
266
267#define CONFIG_SYS_MAX_NAND_DEVICE 1
268#define CONFIG_CMD_NAND 1
269#define CONFIG_NAND_FSL_ELBC 1
270#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
271#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
272
273#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
274 | BR_DECC_CHK_GEN \
275 | BR_PS_8 \
276 | BR_MS_FCM \
277 | BR_V)
278#define CONFIG_SYS_NAND_OR_PRELIM \
279 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
280 | OR_FCM_CSCT \
281 | OR_FCM_CST \
282 | OR_FCM_CHT \
283 | OR_FCM_SCY_1 \
284 | OR_FCM_TRLX \
285 | OR_FCM_EHTR)
286
287
288#ifdef CONFIG_NAND
289#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
290#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
291#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
292#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
293#else
294#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
295#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
296#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
297#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
298#endif
299
300#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
301#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
302
303#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
304#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
305
306
307#define CONFIG_SYS_BCSR_ADDR 0xFA000000
308#define CONFIG_SYS_BCSR_SIZE (32 * 1024)
309
310#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
311 | BR_PS_8 \
312 | BR_MS_GPCM \
313 | BR_V)
314
315#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
316 | OR_GPCM_CSNT \
317 | OR_GPCM_ACS_DIV2 \
318 | OR_GPCM_XACS \
319 | OR_GPCM_SCY_15 \
320 | OR_GPCM_TRLX_SET \
321 | OR_GPCM_EHTR_SET \
322 | OR_GPCM_EAD)
323
324#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
325#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
326
327
328
329#ifdef CONFIG_VSC7385_ENET
330
331
332#define CONFIG_SYS_VSC7385_BASE 0xF0000000
333#define CONFIG_SYS_VSC7385_SIZE (128 * 1024)
334
335#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
336 | BR_PS_8 \
337 | BR_MS_GPCM \
338 | BR_V)
339#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
340 | OR_GPCM_CSNT \
341 | OR_GPCM_XACS \
342 | OR_GPCM_SCY_15 \
343 | OR_GPCM_SETA \
344 | OR_GPCM_TRLX_SET \
345 | OR_GPCM_EHTR_SET \
346 | OR_GPCM_EAD)
347
348
349
350#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
351#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
352
353#endif
354
355#define CONFIG_MPC83XX_GPIO 1
356
357
358
359
360#define CONFIG_CONS_INDEX 1
361#define CONFIG_SYS_NS16550_SERIAL
362#define CONFIG_SYS_NS16550_REG_SIZE 1
363
364#define CONFIG_SYS_BAUDRATE_TABLE \
365 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
366
367#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
368#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
369
370
371#define CONFIG_SYS_I2C
372#define CONFIG_SYS_I2C_FSL
373#define CONFIG_SYS_FSL_I2C_SPEED 400000
374#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
375#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
376#define CONFIG_SYS_FSL_I2C2_SPEED 400000
377#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
378#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
379#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
380
381
382
383
384
385#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
386#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
387#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
388#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
389#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
390#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
391#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
392#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
393#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
394
395#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057
396
397
398
399
400#define CONFIG_TSEC_ENET
401
402#define CONFIG_GMII
403
404#ifdef CONFIG_TSEC1
405#define CONFIG_HAS_ETH0
406#define CONFIG_TSEC1_NAME "TSEC0"
407#define CONFIG_SYS_TSEC1_OFFSET 0x24000
408#define TSEC1_PHY_ADDR 0x1c
409#define TSEC1_FLAGS TSEC_GIGABIT
410#define TSEC1_PHYIDX 0
411#endif
412
413#ifdef CONFIG_TSEC2
414#define CONFIG_HAS_ETH1
415#define CONFIG_TSEC2_NAME "TSEC1"
416#define CONFIG_SYS_TSEC2_OFFSET 0x25000
417#define TSEC2_PHY_ADDR 4
418#define TSEC2_FLAGS TSEC_GIGABIT
419#define TSEC2_PHYIDX 0
420#endif
421
422
423#define CONFIG_ETHPRIME "TSEC1"
424
425
426
427
428#define CONFIG_RTC_DS1337
429#define CONFIG_SYS_I2C_RTC_ADDR 0x68
430
431
432
433
434#if defined(CONFIG_NAND)
435 #define CONFIG_ENV_IS_IN_NAND 1
436 #define CONFIG_ENV_OFFSET (512 * 1024)
437 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
438 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
439 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
440 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
441 #define CONFIG_ENV_OFFSET_REDUND \
442 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
443#elif !defined(CONFIG_SYS_RAMBOOT)
444 #define CONFIG_ENV_IS_IN_FLASH 1
445 #define CONFIG_ENV_ADDR \
446 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
447 #define CONFIG_ENV_SECT_SIZE 0x10000
448 #define CONFIG_ENV_SIZE 0x2000
449
450
451#else
452 #define CONFIG_ENV_IS_NOWHERE 1
453 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
454 #define CONFIG_ENV_SIZE 0x2000
455#endif
456
457#define CONFIG_LOADS_ECHO 1
458#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
459
460
461
462
463#define CONFIG_BOOTP_BOOTFILESIZE
464#define CONFIG_BOOTP_BOOTPATH
465#define CONFIG_BOOTP_GATEWAY
466#define CONFIG_BOOTP_HOSTNAME
467
468
469
470
471#define CONFIG_CMD_DATE
472#define CONFIG_CMD_PCI
473
474#define CONFIG_CMDLINE_EDITING 1
475#define CONFIG_AUTO_COMPLETE
476
477
478
479
480#define CONFIG_SYS_LONGHELP
481#define CONFIG_SYS_LOAD_ADDR 0x2000000
482#define CONFIG_SYS_CBSIZE 1024
483
484
485#define CONFIG_SYS_PBSIZE \
486 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
487#define CONFIG_SYS_MAXARGS 16
488
489#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
490
491
492
493
494
495
496
497#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
498#define CONFIG_SYS_BOOTM_LEN (64 << 20)
499
500#define CONFIG_SYS_RCWH_PCIHOST 0x80000000
501
502#ifdef CONFIG_SYS_66MHZ
503
504
505
506#define CONFIG_SYS_HRCW_LOW (\
507 0x20000000 |\
508 HRCWL_DDRCM |\
509 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
510 HRCWL_DDR_TO_SCB_CLK_2X1 |\
511 HRCWL_CSB_TO_CLKIN_2X1 |\
512 HRCWL_CORE_TO_CSB_2X1)
513
514#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
515
516#elif defined(CONFIG_SYS_33MHZ)
517
518
519
520#define CONFIG_SYS_HRCW_LOW (\
521 0x20000000 |\
522 HRCWL_DDRCM |\
523 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
524 HRCWL_DDR_TO_SCB_CLK_2X1 |\
525 HRCWL_CSB_TO_CLKIN_5X1 |\
526 HRCWL_CORE_TO_CSB_2X1)
527
528#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
529
530#endif
531
532#define CONFIG_SYS_HRCW_HIGH_BASE (\
533 HRCWH_PCI_HOST |\
534 HRCWH_PCI1_ARBITER_ENABLE |\
535 HRCWH_CORE_ENABLE |\
536 HRCWH_BOOTSEQ_DISABLE |\
537 HRCWH_SW_WATCHDOG_DISABLE |\
538 HRCWH_TSEC1M_IN_RGMII |\
539 HRCWH_TSEC2M_IN_RGMII |\
540 HRCWH_BIG_ENDIAN)
541
542#ifdef CONFIG_NAND
543#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
544 HRCWH_FROM_0XFFF00100 |\
545 HRCWH_ROM_LOC_NAND_SP_8BIT |\
546 HRCWH_RL_EXT_NAND)
547#else
548#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
549 HRCWH_FROM_0X00000100 |\
550 HRCWH_ROM_LOC_LOCAL_16BIT |\
551 HRCWH_RL_EXT_LEGACY)
552#endif
553
554
555#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2)
556
557#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
558
559#define CONFIG_SYS_HID0_INIT 0x000000000
560#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
561 HID0_ENABLE_INSTRUCTION_CACHE | \
562 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
563
564#define CONFIG_SYS_HID2 HID2_HBE
565
566#define CONFIG_HIGH_BATS 1
567
568
569#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
570#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
571 | BATU_BL_256M \
572 | BATU_VS \
573 | BATU_VP)
574
575
576#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
577#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
578 | BATU_BL_256M \
579 | BATU_VS \
580 | BATU_VP)
581#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
582 | BATL_PP_RW \
583 | BATL_CACHEINHIBIT \
584 | BATL_GUARDEDSTORAGE)
585#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
586 | BATU_BL_256M \
587 | BATU_VS \
588 | BATU_VP)
589
590
591#define CONFIG_SYS_IBAT3L (0)
592#define CONFIG_SYS_IBAT3U (0)
593#define CONFIG_SYS_IBAT4L (0)
594#define CONFIG_SYS_IBAT4U (0)
595
596
597#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
598 | BATL_PP_RW \
599 | BATL_CACHEINHIBIT \
600 | BATL_GUARDEDSTORAGE)
601#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
602 | BATU_BL_256M \
603 | BATU_VS \
604 | BATU_VP)
605
606
607#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
608#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
609
610#define CONFIG_SYS_IBAT7L (0)
611#define CONFIG_SYS_IBAT7U (0)
612
613#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
614#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
615#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
616#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
617#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
618#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
619#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
620#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
621#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
622#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
623#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
624#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
625#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
626#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
627#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
628#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
629
630
631
632
633#define CONFIG_ENV_OVERWRITE
634
635#define CONFIG_NETDEV "eth1"
636
637#define CONFIG_HOSTNAME mpc8313erdb
638#define CONFIG_ROOTPATH "/nfs/root/path"
639#define CONFIG_BOOTFILE "uImage"
640
641#define CONFIG_UBOOTPATH "u-boot.bin"
642#define CONFIG_FDTFILE "mpc8313erdb.dtb"
643
644
645#define CONFIG_LOADADDR 800000
646#define CONFIG_BAUDRATE 115200
647
648#define CONFIG_EXTRA_ENV_SETTINGS \
649 "netdev=" CONFIG_NETDEV "\0" \
650 "ethprime=TSEC1\0" \
651 "uboot=" CONFIG_UBOOTPATH "\0" \
652 "tftpflash=tftpboot $loadaddr $uboot; " \
653 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
654 " +$filesize; " \
655 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
656 " +$filesize; " \
657 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
658 " $filesize; " \
659 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
660 " +$filesize; " \
661 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
662 " $filesize\0" \
663 "fdtaddr=780000\0" \
664 "fdtfile=" CONFIG_FDTFILE "\0" \
665 "console=ttyS0\0" \
666 "setbootargs=setenv bootargs " \
667 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
668 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
669 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
670 "$netdev:off " \
671 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
672
673#define CONFIG_NFSBOOTCOMMAND \
674 "setenv rootdev /dev/nfs;" \
675 "run setbootargs;" \
676 "run setipargs;" \
677 "tftp $loadaddr $bootfile;" \
678 "tftp $fdtaddr $fdtfile;" \
679 "bootm $loadaddr - $fdtaddr"
680
681#define CONFIG_RAMBOOTCOMMAND \
682 "setenv rootdev /dev/ram;" \
683 "run setbootargs;" \
684 "tftp $ramdiskaddr $ramdiskfile;" \
685 "tftp $loadaddr $bootfile;" \
686 "tftp $fdtaddr $fdtfile;" \
687 "bootm $loadaddr $ramdiskaddr $fdtaddr"
688
689#endif
690