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39
40#ifndef __CONFIG_H
41#define __CONFIG_H
42
43#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
44#define CONFIG_SYS_LOWBOOT
45#endif
46
47
48
49
50#define CONFIG_MPC834x
51#define CONFIG_MPC8349
52
53#ifndef CONFIG_SYS_TEXT_BASE
54#define CONFIG_SYS_TEXT_BASE 0xFEF00000
55#endif
56
57#define CONFIG_SYS_IMMR 0xE0000000
58
59#define CONFIG_MISC_INIT_F
60#define CONFIG_MISC_INIT_R
61
62
63
64
65
66#ifdef CONFIG_MPC8349ITX
67
68#define CONFIG_COMPACT_FLASH
69#define CONFIG_VSC7385_ENET
70#define CONFIG_SATA_SIL3114
71#define CONFIG_SYS_USB_HOST
72#endif
73
74#define CONFIG_RTC_DS1337
75#define CONFIG_SYS_I2C
76#define CONFIG_TSEC_ENET
77
78
79
80
81
82
83#ifdef CONFIG_SYS_I2C
84#define CONFIG_SYS_I2C_FSL
85#define CONFIG_SYS_FSL_I2C_SPEED 400000
86#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
87#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
88#define CONFIG_SYS_FSL_I2C2_SPEED 400000
89#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
90#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
91
92#define CONFIG_SYS_SPD_BUS_NUM 1
93#define CONFIG_SYS_RTC_BUS_NUM 1
94
95#define CONFIG_SYS_I2C_8574_ADDR1 0x20
96#define CONFIG_SYS_I2C_8574_ADDR2 0x21
97#define CONFIG_SYS_I2C_8574A_ADDR1 0x38
98#define CONFIG_SYS_I2C_8574A_ADDR2 0x39
99#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
100#define CONFIG_SYS_I2C_RTC_ADDR 0x68
101#define SPD_EEPROM_ADDRESS 0x51
102
103
104#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
105 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
106 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
107 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
108
109
110#define I2C_8574_REVISION 0x03
111#define I2C_8574_CF 0x08
112#define I2C_8574_MPCICLKRN 0x10
113#define I2C_8574_PCI66 0x20
114#define I2C_8574_FLASHSIDE 0x40
115
116#endif
117
118
119#ifdef CONFIG_COMPACT_FLASH
120
121#define CONFIG_SYS_IDE_MAXBUS 1
122#define CONFIG_SYS_IDE_MAXDEVICE 1
123
124#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
125#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
126#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
127#define CONFIG_SYS_ATA_REG_OFFSET 0
128#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
129#define CONFIG_SYS_ATA_STRIDE 2
130
131
132#define ATA_RESET_TIME 1
133
134#endif
135
136
137
138
139#ifdef CONFIG_SATA_SIL3114
140
141#define CONFIG_SYS_SATA_MAX_DEVICE 4
142#define CONFIG_LIBATA
143#define CONFIG_LBA48
144
145#endif
146
147#ifdef CONFIG_SYS_USB_HOST
148
149
150
151#define CONFIG_USB_EHCI
152#define CONFIG_USB_EHCI_FSL
153
154
155
156#if 1
157#define CONFIG_HAS_FSL_MPH_USB
158#else
159#define CONFIG_HAS_FSL_DR_USB
160#endif
161
162#endif
163
164
165
166
167#define CONFIG_SYS_DDR_BASE 0x00000000
168#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
169#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
170#define CONFIG_SYS_83XX_DDR_USES_CS0
171#define CONFIG_SYS_MEMTEST_START 0x1000
172#define CONFIG_SYS_MEMTEST_END 0x2000
173
174#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
175 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
176
177#define CONFIG_VERY_BIG_RAM
178#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
179
180#ifdef CONFIG_SYS_I2C
181#define CONFIG_SPD_EEPROM
182#endif
183
184
185#ifndef CONFIG_SPD_EEPROM
186 #define CONFIG_SYS_DDR_SIZE 256
187 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
188 | CSCONFIG_ROW_BIT_13 \
189 | CSCONFIG_COL_BIT_10)
190
191 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
192 #define CONFIG_SYS_DDR_TIMING_2 0x00000800
193#endif
194
195
196
197
198
199#define CONFIG_SYS_FLASH_CFI
200#define CONFIG_FLASH_CFI_DRIVER
201#define CONFIG_SYS_FLASH_BASE 0xFE000000
202#define CONFIG_SYS_FLASH_EMPTY_INFO
203
204#define CONFIG_SYS_MAX_FLASH_SECT 135
205#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
206#define CONFIG_SYS_FLASH_WRITE_TOUT 500
207#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
208
209
210
211#define CONFIG_SYS_FLASH_QUIET_TEST
212#define CONFIG_SYS_MAX_FLASH_BANKS 2
213#define CONFIG_SYS_FLASH_BANKS_LIST \
214 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
215#define CONFIG_SYS_FLASH_SIZE 16
216#define CONFIG_SYS_FLASH_PROTECTION 1
217
218
219
220#ifdef CONFIG_VSC7385_ENET
221
222#define CONFIG_TSEC2
223
224
225#define CONFIG_VSC7385_IMAGE 0xFEFFE000
226#define CONFIG_VSC7385_IMAGE_SIZE 8192
227
228#endif
229
230
231
232
233
234
235
236#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
237 | BR_PS_16 \
238 | BR_MS_GPCM \
239 | BR_V)
240#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
241 | OR_UPM_XAM \
242 | OR_GPCM_CSNT \
243 | OR_GPCM_ACS_DIV2 \
244 | OR_GPCM_XACS \
245 | OR_GPCM_SCY_15 \
246 | OR_GPCM_TRLX_SET \
247 | OR_GPCM_EHTR_SET \
248 | OR_GPCM_EAD)
249#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
250#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
251
252
253
254#define CONFIG_SYS_VSC7385_BASE 0xF8000000
255
256#ifdef CONFIG_VSC7385_ENET
257
258#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
259 | BR_PS_8 \
260 | BR_MS_GPCM \
261 | BR_V)
262#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
263 | OR_GPCM_CSNT \
264 | OR_GPCM_XACS \
265 | OR_GPCM_SCY_15 \
266 | OR_GPCM_SETA \
267 | OR_GPCM_TRLX_SET \
268 | OR_GPCM_EHTR_SET \
269 | OR_GPCM_EAD)
270
271#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
272#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
273
274#endif
275
276
277
278#define CONFIG_SYS_LED_BASE 0xF9000000
279#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \
280 | BR_PS_8 \
281 | BR_MS_GPCM \
282 | BR_V)
283#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
284 | OR_GPCM_CSNT \
285 | OR_GPCM_ACS_DIV2 \
286 | OR_GPCM_XACS \
287 | OR_GPCM_SCY_9 \
288 | OR_GPCM_TRLX_SET \
289 | OR_GPCM_EHTR_SET \
290 | OR_GPCM_EAD)
291
292
293
294#ifdef CONFIG_COMPACT_FLASH
295
296#define CONFIG_SYS_CF_BASE 0xF0000000
297
298#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
299 | BR_PS_16 \
300 | BR_MS_UPMA \
301 | BR_V)
302#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
303
304#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
305#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
306
307#endif
308
309
310
311
312#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
313
314#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
315#define CONFIG_SYS_RAMBOOT
316#else
317#undef CONFIG_SYS_RAMBOOT
318#endif
319
320#define CONFIG_SYS_INIT_RAM_LOCK
321#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
322#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
323
324#define CONFIG_SYS_GBL_DATA_OFFSET \
325 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
326#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
327
328
329#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
330#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
331
332
333
334
335
336
337
338#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
339#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
340#define CONFIG_SYS_LBC_LBCR 0x00000000
341
342
343#define CONFIG_SYS_LBC_LSRT 0x32000000
344
345#define CONFIG_SYS_LBC_MRTPR 0x20000000
346
347
348
349
350#define CONFIG_CONS_INDEX 1
351#define CONFIG_SYS_NS16550_SERIAL
352#define CONFIG_SYS_NS16550_REG_SIZE 1
353#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
354
355#define CONFIG_SYS_BAUDRATE_TABLE \
356 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
357
358#define CONSOLE ttyS0
359#define CONFIG_BAUDRATE 115200
360
361#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
362#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
363
364
365
366
367#ifdef CONFIG_PCI
368#define CONFIG_PCI_INDIRECT_BRIDGE
369
370#define CONFIG_MPC83XX_PCI2
371
372
373
374
375
376#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
377#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
378#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
379#define CONFIG_SYS_PCI1_MMIO_BASE \
380 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
381#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
382#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
383#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
384#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
385#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
386
387#ifdef CONFIG_MPC83XX_PCI2
388#define CONFIG_SYS_PCI2_MEM_BASE \
389 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
390#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
391#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000
392#define CONFIG_SYS_PCI2_MMIO_BASE \
393 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
394#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
395#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000
396#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
397#define CONFIG_SYS_PCI2_IO_PHYS \
398 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
399#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000
400#endif
401
402#ifndef CONFIG_PCI_PNP
403 #define PCI_ENET0_IOADDR 0x00000000
404 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
405 #define PCI_IDSEL_NUMBER 0x0f
406#endif
407
408#define CONFIG_PCI_SCAN_SHOW
409
410#endif
411
412#define CONFIG_PCI_66M
413#ifdef CONFIG_PCI_66M
414#define CONFIG_83XX_CLKIN 66666666
415#else
416#define CONFIG_83XX_CLKIN 33333333
417#endif
418
419
420
421#ifdef CONFIG_TSEC_ENET
422
423#define CONFIG_MII
424#define CONFIG_PHY_GIGE
425
426#define CONFIG_TSEC1
427
428#ifdef CONFIG_TSEC1
429#define CONFIG_HAS_ETH0
430#define CONFIG_TSEC1_NAME "TSEC0"
431#define CONFIG_SYS_TSEC1_OFFSET 0x24000
432#define TSEC1_PHY_ADDR 0x1c
433#define TSEC1_PHYIDX 0
434#define TSEC1_FLAGS TSEC_GIGABIT
435#endif
436
437#ifdef CONFIG_TSEC2
438#define CONFIG_HAS_ETH1
439#define CONFIG_TSEC2_NAME "TSEC1"
440#define CONFIG_SYS_TSEC2_OFFSET 0x25000
441
442#define TSEC2_PHY_ADDR 4
443#define TSEC2_PHYIDX 0
444#define TSEC2_FLAGS TSEC_GIGABIT
445#endif
446
447#define CONFIG_ETHPRIME "Freescale TSEC"
448
449#endif
450
451
452
453
454#define CONFIG_ENV_OVERWRITE
455
456#ifndef CONFIG_SYS_RAMBOOT
457 #define CONFIG_ENV_IS_IN_FLASH
458 #define CONFIG_ENV_ADDR \
459 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
460 #define CONFIG_ENV_SECT_SIZE 0x10000
461 #define CONFIG_ENV_SIZE 0x2000
462#else
463 #undef CONFIG_FLASH_CFI_DRIVER
464 #define CONFIG_ENV_IS_NOWHERE
465 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
466 #define CONFIG_ENV_SIZE 0x2000
467#endif
468
469#define CONFIG_LOADS_ECHO
470#define CONFIG_SYS_LOADS_BAUD_CHANGE
471
472
473
474
475#define CONFIG_BOOTP_BOOTFILESIZE
476#define CONFIG_BOOTP_BOOTPATH
477#define CONFIG_BOOTP_GATEWAY
478#define CONFIG_BOOTP_HOSTNAME
479
480
481
482
483#define CONFIG_CMD_DATE
484#define CONFIG_CMD_IRQ
485#define CONFIG_CMD_SDRAM
486
487#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
488 || defined(CONFIG_USB_STORAGE)
489 #define CONFIG_SUPPORT_VFAT
490#endif
491
492#ifdef CONFIG_COMPACT_FLASH
493 #define CONFIG_CMD_IDE
494#endif
495
496#ifdef CONFIG_SATA_SIL3114
497 #define CONFIG_CMD_SATA
498#endif
499
500#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
501#endif
502
503#ifdef CONFIG_PCI
504 #define CONFIG_CMD_PCI
505#endif
506
507
508#undef CONFIG_WATCHDOG
509
510
511
512
513#define CONFIG_SYS_LONGHELP
514#define CONFIG_CMDLINE_EDITING
515#define CONFIG_AUTO_COMPLETE
516
517#define CONFIG_SYS_LOAD_ADDR 0x2000000
518#define CONFIG_LOADADDR 800000
519
520#if defined(CONFIG_CMD_KGDB)
521 #define CONFIG_SYS_CBSIZE 1024
522#else
523 #define CONFIG_SYS_CBSIZE 256
524#endif
525
526
527#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
528#define CONFIG_SYS_MAXARGS 16
529
530#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
531
532
533
534
535
536
537
538#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
539#define CONFIG_SYS_BOOTM_LEN (64 << 20)
540
541#define CONFIG_SYS_HRCW_LOW (\
542 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
543 HRCWL_DDR_TO_SCB_CLK_1X1 |\
544 HRCWL_CSB_TO_CLKIN_4X1 |\
545 HRCWL_VCO_1X2 |\
546 HRCWL_CORE_TO_CSB_2X1)
547
548#ifdef CONFIG_SYS_LOWBOOT
549#define CONFIG_SYS_HRCW_HIGH (\
550 HRCWH_PCI_HOST |\
551 HRCWH_32_BIT_PCI |\
552 HRCWH_PCI1_ARBITER_ENABLE |\
553 HRCWH_PCI2_ARBITER_ENABLE |\
554 HRCWH_CORE_ENABLE |\
555 HRCWH_FROM_0X00000100 |\
556 HRCWH_BOOTSEQ_DISABLE |\
557 HRCWH_SW_WATCHDOG_DISABLE |\
558 HRCWH_ROM_LOC_LOCAL_16BIT |\
559 HRCWH_TSEC1M_IN_GMII |\
560 HRCWH_TSEC2M_IN_GMII)
561#else
562#define CONFIG_SYS_HRCW_HIGH (\
563 HRCWH_PCI_HOST |\
564 HRCWH_32_BIT_PCI |\
565 HRCWH_PCI1_ARBITER_ENABLE |\
566 HRCWH_PCI2_ARBITER_ENABLE |\
567 HRCWH_CORE_ENABLE |\
568 HRCWH_FROM_0XFFF00100 |\
569 HRCWH_BOOTSEQ_DISABLE |\
570 HRCWH_SW_WATCHDOG_DISABLE |\
571 HRCWH_ROM_LOC_LOCAL_16BIT |\
572 HRCWH_TSEC1M_IN_GMII |\
573 HRCWH_TSEC2M_IN_GMII)
574#endif
575
576
577
578
579#define CONFIG_SYS_ACR_PIPE_DEP 3
580#define CONFIG_SYS_ACR_RPTCNT 3
581#define CONFIG_SYS_SPCR_TSEC1EP 3
582#define CONFIG_SYS_SPCR_TSEC2EP 3
583#define CONFIG_SYS_SCCR_TSEC1CM 1
584#define CONFIG_SYS_SCCR_TSEC2CM 1
585#define CONFIG_SYS_SCCR_USBMPHCM 3
586#define CONFIG_SYS_SCCR_USBDRCM 0
587
588
589
590
591
592#define CONFIG_SYS_SICRH SICRH_TSOBI1
593
594#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
595
596#define CONFIG_SYS_HID0_INIT 0x00000000
597#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
598
599#define CONFIG_SYS_HID2 HID2_HBE
600#define CONFIG_HIGH_BATS 1
601
602
603#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
604 | BATL_PP_RW \
605 | BATL_MEMCOHERENCE)
606#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
607 | BATU_BL_256M \
608 | BATU_VS \
609 | BATU_VP)
610
611
612#ifdef CONFIG_PCI
613#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
614 | BATL_PP_RW \
615 | BATL_MEMCOHERENCE)
616#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
617 | BATU_BL_256M \
618 | BATU_VS \
619 | BATU_VP)
620#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
621 | BATL_PP_RW \
622 | BATL_CACHEINHIBIT \
623 | BATL_GUARDEDSTORAGE)
624#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
625 | BATU_BL_256M \
626 | BATU_VS \
627 | BATU_VP)
628#else
629#define CONFIG_SYS_IBAT1L 0
630#define CONFIG_SYS_IBAT1U 0
631#define CONFIG_SYS_IBAT2L 0
632#define CONFIG_SYS_IBAT2U 0
633#endif
634
635#ifdef CONFIG_MPC83XX_PCI2
636#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
637 | BATL_PP_RW \
638 | BATL_MEMCOHERENCE)
639#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
640 | BATU_BL_256M \
641 | BATU_VS \
642 | BATU_VP)
643#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
644 | BATL_PP_RW \
645 | BATL_CACHEINHIBIT \
646 | BATL_GUARDEDSTORAGE)
647#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
648 | BATU_BL_256M \
649 | BATU_VS \
650 | BATU_VP)
651#else
652#define CONFIG_SYS_IBAT3L 0
653#define CONFIG_SYS_IBAT3U 0
654#define CONFIG_SYS_IBAT4L 0
655#define CONFIG_SYS_IBAT4U 0
656#endif
657
658
659#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
660 | BATL_PP_RW \
661 | BATL_CACHEINHIBIT \
662 | BATL_GUARDEDSTORAGE)
663#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
664 | BATU_BL_256M \
665 | BATU_VS \
666 | BATU_VP)
667
668
669#define CONFIG_SYS_IBAT6L (0xF0000000 \
670 | BATL_PP_RW \
671 | BATL_MEMCOHERENCE \
672 | BATL_GUARDEDSTORAGE)
673#define CONFIG_SYS_IBAT6U (0xF0000000 \
674 | BATU_BL_256M \
675 | BATU_VS \
676 | BATU_VP)
677
678#define CONFIG_SYS_IBAT7L 0
679#define CONFIG_SYS_IBAT7U 0
680
681#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
682#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
683#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
684#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
685#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
686#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
687#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
688#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
689#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
690#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
691#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
692#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
693#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
694#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
695#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
696#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
697
698#if defined(CONFIG_CMD_KGDB)
699#define CONFIG_KGDB_BAUDRATE 230400
700#endif
701
702
703
704
705#define CONFIG_ENV_OVERWRITE
706
707#define CONFIG_NETDEV "eth0"
708
709#ifdef CONFIG_MPC8349ITX
710#define CONFIG_HOSTNAME "mpc8349emitx"
711#else
712#define CONFIG_HOSTNAME "mpc8349emitxgp"
713#endif
714
715
716#define CONFIG_ROOTPATH "/nfsroot/rootfs"
717#define CONFIG_BOOTFILE "uImage"
718
719#define CONFIG_UBOOTPATH "u-boot.bin"
720
721#ifdef CONFIG_MPC8349ITX
722#define CONFIG_FDTFILE "mpc8349emitx.dtb"
723#else
724#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
725#endif
726
727
728#define CONFIG_BOOTARGS \
729 "root=/dev/nfs rw" \
730 " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \
731 " ip=" __stringify(CONFIG_IPADDR) ":" \
732 __stringify(CONFIG_SERVERIP) ":" \
733 __stringify(CONFIG_GATEWAYIP) ":" \
734 __stringify(CONFIG_NETMASK) ":" \
735 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \
736 " console=" __stringify(CONSOLE) "," __stringify(CONFIG_BAUDRATE)
737
738#define CONFIG_EXTRA_ENV_SETTINGS \
739 "console=" __stringify(CONSOLE) "\0" \
740 "netdev=" CONFIG_NETDEV "\0" \
741 "uboot=" CONFIG_UBOOTPATH "\0" \
742 "tftpflash=tftpboot $loadaddr $uboot; " \
743 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
744 " +$filesize; " \
745 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
746 " +$filesize; " \
747 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
748 " $filesize; " \
749 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
750 " +$filesize; " \
751 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
752 " $filesize\0" \
753 "fdtaddr=780000\0" \
754 "fdtfile=" CONFIG_FDTFILE "\0"
755
756#define CONFIG_NFSBOOTCOMMAND \
757 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
758 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
759 " console=$console,$baudrate $othbootargs; " \
760 "tftp $loadaddr $bootfile;" \
761 "tftp $fdtaddr $fdtfile;" \
762 "bootm $loadaddr - $fdtaddr"
763
764#define CONFIG_RAMBOOTCOMMAND \
765 "setenv bootargs root=/dev/ram rw" \
766 " console=$console,$baudrate $othbootargs; " \
767 "tftp $ramdiskaddr $ramdiskfile;" \
768 "tftp $loadaddr $bootfile;" \
769 "tftp $fdtaddr $fdtfile;" \
770 "bootm $loadaddr $ramdiskaddr $fdtaddr"
771
772#endif
773