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7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11
12
13
14#define CONFIG_E300 1
15#define CONFIG_MPC837x 1
16#define CONFIG_MPC837XEMDS 1
17
18#define CONFIG_SYS_TEXT_BASE 0xFE000000
19
20
21
22
23#ifdef CONFIG_PCISLAVE
24#define CONFIG_83XX_PCICLK 66000000
25#else
26#define CONFIG_83XX_CLKIN 66000000
27#endif
28
29#ifndef CONFIG_SYS_CLK_FREQ
30#define CONFIG_SYS_CLK_FREQ 66000000
31#endif
32
33
34
35
36
37
38#define CONFIG_SYS_HRCW_LOW (\
39 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
40 HRCWL_DDR_TO_SCB_CLK_1X1 |\
41 HRCWL_SVCOD_DIV_2 |\
42 HRCWL_CSB_TO_CLKIN_6X1 |\
43 HRCWL_CORE_TO_CSB_1_5X1)
44
45#ifdef CONFIG_PCISLAVE
46#define CONFIG_SYS_HRCW_HIGH (\
47 HRCWH_PCI_AGENT |\
48 HRCWH_PCI1_ARBITER_DISABLE |\
49 HRCWH_CORE_ENABLE |\
50 HRCWH_FROM_0XFFF00100 |\
51 HRCWH_BOOTSEQ_DISABLE |\
52 HRCWH_SW_WATCHDOG_DISABLE |\
53 HRCWH_ROM_LOC_LOCAL_16BIT |\
54 HRCWH_RL_EXT_LEGACY |\
55 HRCWH_TSEC1M_IN_RGMII |\
56 HRCWH_TSEC2M_IN_RGMII |\
57 HRCWH_BIG_ENDIAN |\
58 HRCWH_LDP_CLEAR)
59#else
60#define CONFIG_SYS_HRCW_HIGH (\
61 HRCWH_PCI_HOST |\
62 HRCWH_PCI1_ARBITER_ENABLE |\
63 HRCWH_CORE_ENABLE |\
64 HRCWH_FROM_0X00000100 |\
65 HRCWH_BOOTSEQ_DISABLE |\
66 HRCWH_SW_WATCHDOG_DISABLE |\
67 HRCWH_ROM_LOC_LOCAL_16BIT |\
68 HRCWH_RL_EXT_LEGACY |\
69 HRCWH_TSEC1M_IN_RGMII |\
70 HRCWH_TSEC2M_IN_RGMII |\
71 HRCWH_BIG_ENDIAN |\
72 HRCWH_LDP_CLEAR)
73#endif
74
75
76#define CONFIG_SYS_ACR_PIPE_DEP 3
77#define CONFIG_SYS_ACR_RPTCNT 3
78
79
80#define CONFIG_SYS_SPCR_TSECEP 3
81
82
83
84
85#define CONFIG_SYS_SCCR_TSEC1CM 1
86#define CONFIG_SYS_SCCR_TSEC2CM 1
87#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2
88
89
90
91
92#define CONFIG_SYS_SICRH 0x00000000
93#define CONFIG_SYS_SICRL 0x00000000
94
95
96
97
98#define CONFIG_SYS_OBIR 0x31100000
99
100#define CONFIG_BOARD_EARLY_INIT_R
101#define CONFIG_HWCONFIG
102
103
104
105
106#define CONFIG_SYS_IMMR 0xE0000000
107
108
109
110
111#define CONFIG_SYS_DDR_BASE 0x00000000
112#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
113#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
114#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
115#define CONFIG_SYS_83XX_DDR_USES_CS0
116#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
117 | DDRCDR_ODT \
118 | DDRCDR_Q_DRN)
119
120
121#undef CONFIG_DDR_ECC
122#undef CONFIG_DDR_ECC_CMD
123
124#define CONFIG_SPD_EEPROM
125#define CONFIG_NEVER_ASSERT_ODT_TO_CPU
126
127#if defined(CONFIG_SPD_EEPROM)
128#define SPD_EEPROM_ADDRESS 0x51
129#else
130
131
132
133
134
135#define CONFIG_SYS_DDR_SIZE 512
136#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
137#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
138 | CSCONFIG_ODT_RD_NEVER \
139 | CSCONFIG_ODT_WR_ONLY_CURRENT \
140 | CSCONFIG_ROW_BIT_14 \
141 | CSCONFIG_COL_BIT_10)
142
143#define CONFIG_SYS_DDR_TIMING_3 0x00000000
144#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
145 | (0 << TIMING_CFG0_WRT_SHIFT) \
146 | (0 << TIMING_CFG0_RRT_SHIFT) \
147 | (0 << TIMING_CFG0_WWT_SHIFT) \
148 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
149 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
150 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
151 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
152
153#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
154 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
155 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
156 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
157 | (13 << TIMING_CFG1_REFREC_SHIFT) \
158 | (3 << TIMING_CFG1_WRREC_SHIFT) \
159 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
160 | (2 << TIMING_CFG1_WRTORD_SHIFT))
161
162#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
163 | (6 << TIMING_CFG2_CPO_SHIFT) \
164 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
165 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
166 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
167 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
168 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
169
170#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
171 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
172
173#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
174#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000
175#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
176 | (0x1432 << SDRAM_MODE_SD_SHIFT))
177
178#define CONFIG_SYS_DDR_MODE2 0x00000000
179#endif
180
181
182
183
184#undef CONFIG_SYS_DRAM_TEST
185#define CONFIG_SYS_MEMTEST_START 0x00040000
186#define CONFIG_SYS_MEMTEST_END 0x00140000
187
188
189
190
191#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
192
193#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
194#define CONFIG_SYS_RAMBOOT
195#else
196#undef CONFIG_SYS_RAMBOOT
197#endif
198
199
200#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
201#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
202
203
204
205
206#define CONFIG_SYS_INIT_RAM_LOCK 1
207#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
208#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
209#define CONFIG_SYS_GBL_DATA_OFFSET \
210 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
211
212
213
214
215#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
216#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
217#define CONFIG_SYS_LBC_LBCR 0x00000000
218#define CONFIG_FSL_ELBC 1
219
220
221
222
223#define CONFIG_SYS_FLASH_CFI
224#define CONFIG_FLASH_CFI_DRIVER
225#define CONFIG_SYS_FLASH_BASE 0xFE000000
226#define CONFIG_SYS_FLASH_SIZE 32
227#define CONFIG_SYS_FLASH_PROTECTION 1
228
229
230#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
231#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
232
233#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
234 | BR_PS_16 \
235 | BR_MS_GPCM \
236 | BR_V)
237#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
238 | OR_UPM_XAM \
239 | OR_GPCM_CSNT \
240 | OR_GPCM_ACS_DIV2 \
241 | OR_GPCM_XACS \
242 | OR_GPCM_SCY_15 \
243 | OR_GPCM_TRLX_SET \
244 | OR_GPCM_EHTR_SET \
245 | OR_GPCM_EAD)
246
247
248#define CONFIG_SYS_MAX_FLASH_BANKS 1
249#define CONFIG_SYS_MAX_FLASH_SECT 256
250
251#undef CONFIG_SYS_FLASH_CHECKSUM
252#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
253#define CONFIG_SYS_FLASH_WRITE_TOUT 500
254
255
256
257
258#define CONFIG_SYS_BCSR 0xF8000000
259
260#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
261#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
262
263#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
264 | BR_PS_8 \
265 | BR_MS_GPCM \
266 | BR_V)
267
268#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
269 | OR_GPCM_XAM \
270 | OR_GPCM_CSNT \
271 | OR_GPCM_XACS \
272 | OR_GPCM_SCY_15 \
273 | OR_GPCM_TRLX_SET \
274 | OR_GPCM_EHTR_SET \
275 | OR_GPCM_EAD)
276
277
278
279
280
281#define CONFIG_CMD_NAND 1
282#define CONFIG_SYS_MAX_NAND_DEVICE 1
283#define CONFIG_NAND_FSL_ELBC 1
284
285#define CONFIG_SYS_NAND_BASE 0xE0600000
286#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
287 | BR_DECC_CHK_GEN \
288 | BR_PS_8 \
289 | BR_MS_FCM \
290 | BR_V)
291#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
292 | OR_FCM_BCTLD \
293 | OR_FCM_CST \
294 | OR_FCM_CHT \
295 | OR_FCM_SCY_1 \
296 | OR_FCM_RST \
297 | OR_FCM_TRLX \
298 | OR_FCM_EHTR)
299
300
301#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
302#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
303
304
305
306
307#define CONFIG_CONS_INDEX 1
308#define CONFIG_SYS_NS16550_SERIAL
309#define CONFIG_SYS_NS16550_REG_SIZE 1
310#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
311
312#define CONFIG_SYS_BAUDRATE_TABLE \
313 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
314
315#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
316#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
317
318
319#define CONFIG_SYS_I2C
320#define CONFIG_SYS_I2C_FSL
321#define CONFIG_SYS_FSL_I2C_SPEED 400000
322#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
323#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
324#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
325
326
327
328
329#define CONFIG_RTC_DS1374
330#define CONFIG_SYS_I2C_RTC_ADDR 0x68
331
332
333
334
335
336#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
337#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
338#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
339#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
340#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
341#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000
342#define CONFIG_SYS_PCI_IO_BASE 0x00000000
343#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
344#define CONFIG_SYS_PCI_IO_SIZE 0x100000
345
346#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
347#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
348#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
349
350#define CONFIG_SYS_PCIE1_BASE 0xA0000000
351#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
352#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
353#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
354#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
355#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
356#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
357#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
358#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
359
360#define CONFIG_SYS_PCIE2_BASE 0xC0000000
361#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
362#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
363#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
364#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
365#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
366#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
367#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
368#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
369
370#ifdef CONFIG_PCI
371#define CONFIG_PCI_INDIRECT_BRIDGE
372#ifndef __ASSEMBLY__
373extern int board_pci_host_broken(void);
374#endif
375#define CONFIG_PCIE
376#define CONFIG_PQ_MDS_PIB 1
377
378#define CONFIG_HAS_FSL_DR_USB 1
379#define CONFIG_USB_EHCI
380#define CONFIG_USB_EHCI_FSL
381#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
382
383#undef CONFIG_EEPRO100
384#undef CONFIG_PCI_SCAN_SHOW
385#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
386#endif
387
388
389
390
391#define CONFIG_TSEC_ENET
392#define CONFIG_SYS_TSEC1_OFFSET 0x24000
393#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
394#define CONFIG_SYS_TSEC2_OFFSET 0x25000
395#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
396
397
398
399
400#define CONFIG_MII 1
401#define CONFIG_TSEC1 1
402#define CONFIG_TSEC1_NAME "eTSEC0"
403#define CONFIG_TSEC2 1
404#define CONFIG_TSEC2_NAME "eTSEC1"
405#define TSEC1_PHY_ADDR 2
406#define TSEC2_PHY_ADDR 3
407#define TSEC1_PHY_ADDR_SGMII 8
408#define TSEC2_PHY_ADDR_SGMII 4
409#define TSEC1_PHYIDX 0
410#define TSEC2_PHYIDX 0
411#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
412#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
413
414
415#define CONFIG_ETHPRIME "eTSEC1"
416
417
418#define CONFIG_FSL_SERDES
419#define CONFIG_FSL_SERDES1 0xe3000
420#define CONFIG_FSL_SERDES2 0xe3100
421
422
423
424
425#define CONFIG_LIBATA
426#define CONFIG_FSL_SATA
427
428#define CONFIG_SYS_SATA_MAX_DEVICE 2
429#define CONFIG_SATA1
430#define CONFIG_SYS_SATA1_OFFSET 0x18000
431#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
432#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
433#define CONFIG_SATA2
434#define CONFIG_SYS_SATA2_OFFSET 0x19000
435#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
436#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
437
438#ifdef CONFIG_FSL_SATA
439#define CONFIG_LBA48
440#define CONFIG_CMD_SATA
441#endif
442
443
444
445
446#ifndef CONFIG_SYS_RAMBOOT
447 #define CONFIG_ENV_IS_IN_FLASH 1
448 #define CONFIG_ENV_ADDR \
449 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
450 #define CONFIG_ENV_SECT_SIZE 0x20000
451 #define CONFIG_ENV_SIZE 0x2000
452#else
453 #define CONFIG_ENV_IS_NOWHERE 1
454 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
455 #define CONFIG_ENV_SIZE 0x2000
456#endif
457
458#define CONFIG_LOADS_ECHO 1
459#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
460
461
462
463
464#define CONFIG_BOOTP_BOOTFILESIZE
465#define CONFIG_BOOTP_BOOTPATH
466#define CONFIG_BOOTP_GATEWAY
467#define CONFIG_BOOTP_HOSTNAME
468
469
470
471
472#define CONFIG_CMD_DATE
473
474#if defined(CONFIG_PCI)
475 #define CONFIG_CMD_PCI
476#endif
477
478#define CONFIG_CMDLINE_EDITING 1
479#define CONFIG_AUTO_COMPLETE
480
481#undef CONFIG_WATCHDOG
482
483#ifdef CONFIG_MMC
484#define CONFIG_FSL_ESDHC
485#define CONFIG_FSL_ESDHC_PIN_MUX
486#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
487#endif
488
489
490
491
492#define CONFIG_SYS_LONGHELP
493#define CONFIG_SYS_LOAD_ADDR 0x2000000
494
495#if defined(CONFIG_CMD_KGDB)
496 #define CONFIG_SYS_CBSIZE 1024
497#else
498 #define CONFIG_SYS_CBSIZE 256
499#endif
500
501
502#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
503#define CONFIG_SYS_MAXARGS 16
504
505#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
506
507
508
509
510
511
512#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
513#define CONFIG_SYS_BOOTM_LEN (64 << 20)
514
515
516
517
518#define CONFIG_SYS_HID0_INIT 0x000000000
519#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
520 HID0_ENABLE_INSTRUCTION_CACHE)
521#define CONFIG_SYS_HID2 HID2_HBE
522
523
524
525
526#define CONFIG_HIGH_BATS 1
527
528
529#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
530#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
531
532#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
533 | BATL_PP_RW \
534 | BATL_MEMCOHERENCE)
535#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
536 | BATU_BL_256M \
537 | BATU_VS \
538 | BATU_VP)
539#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
540#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
541
542#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
543 | BATL_PP_RW \
544 | BATL_MEMCOHERENCE)
545#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
546 | BATU_BL_256M \
547 | BATU_VS \
548 | BATU_VP)
549#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
550#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
551
552
553#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
554 | BATL_PP_RW \
555 | BATL_CACHEINHIBIT \
556 | BATL_GUARDEDSTORAGE)
557#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
558 | BATU_BL_8M \
559 | BATU_VS \
560 | BATU_VP)
561#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
562#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
563
564
565#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
566 | BATL_PP_RW \
567 | BATL_CACHEINHIBIT \
568 | BATL_GUARDEDSTORAGE)
569#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
570 | BATU_BL_128K \
571 | BATU_VS \
572 | BATU_VP)
573#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
574#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
575
576
577#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
578 | BATL_PP_RW \
579 | BATL_MEMCOHERENCE)
580#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
581 | BATU_BL_32M \
582 | BATU_VS \
583 | BATU_VP)
584#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
585 | BATL_PP_RW \
586 | BATL_CACHEINHIBIT \
587 | BATL_GUARDEDSTORAGE)
588#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
589
590
591#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
592#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
593 | BATU_BL_128K \
594 | BATU_VS \
595 | BATU_VP)
596#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
597#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
598
599#ifdef CONFIG_PCI
600
601#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
602 | BATL_PP_RW \
603 | BATL_MEMCOHERENCE)
604#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
605 | BATU_BL_256M \
606 | BATU_VS \
607 | BATU_VP)
608#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
609#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
610
611#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
612 | BATL_PP_RW \
613 | BATL_CACHEINHIBIT \
614 | BATL_GUARDEDSTORAGE)
615#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
616 | BATU_BL_256M \
617 | BATU_VS \
618 | BATU_VP)
619#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
620#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
621#else
622#define CONFIG_SYS_IBAT6L (0)
623#define CONFIG_SYS_IBAT6U (0)
624#define CONFIG_SYS_IBAT7L (0)
625#define CONFIG_SYS_IBAT7U (0)
626#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
627#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
628#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
629#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
630#endif
631
632#if defined(CONFIG_CMD_KGDB)
633#define CONFIG_KGDB_BAUDRATE 230400
634#endif
635
636
637
638
639
640#define CONFIG_ENV_OVERWRITE
641
642#if defined(CONFIG_TSEC_ENET)
643#define CONFIG_HAS_ETH0
644#define CONFIG_HAS_ETH1
645#endif
646
647#define CONFIG_BAUDRATE 115200
648
649#define CONFIG_LOADADDR 800000
650
651#undef CONFIG_BOOTARGS
652
653#define CONFIG_EXTRA_ENV_SETTINGS \
654 "netdev=eth0\0" \
655 "consoledev=ttyS0\0" \
656 "ramdiskaddr=1000000\0" \
657 "ramdiskfile=ramfs.83xx\0" \
658 "fdtaddr=780000\0" \
659 "fdtfile=mpc8379_mds.dtb\0" \
660 ""
661
662#define CONFIG_NFSBOOTCOMMAND \
663 "setenv bootargs root=/dev/nfs rw " \
664 "nfsroot=$serverip:$rootpath " \
665 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
666 "$netdev:off " \
667 "console=$consoledev,$baudrate $othbootargs;" \
668 "tftp $loadaddr $bootfile;" \
669 "tftp $fdtaddr $fdtfile;" \
670 "bootm $loadaddr - $fdtaddr"
671
672#define CONFIG_RAMBOOTCOMMAND \
673 "setenv bootargs root=/dev/ram rw " \
674 "console=$consoledev,$baudrate $othbootargs;" \
675 "tftp $ramdiskaddr $ramdiskfile;" \
676 "tftp $loadaddr $bootfile;" \
677 "tftp $fdtaddr $fdtfile;" \
678 "bootm $loadaddr $ramdiskaddr $fdtaddr"
679
680#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
681
682#endif
683