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11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#include "../board/freescale/common/ics307_clk.h"
15
16#ifndef CONFIG_SYS_TEXT_BASE
17#define CONFIG_SYS_TEXT_BASE 0xeff40000
18#endif
19
20#ifndef CONFIG_RESET_VECTOR_ADDRESS
21#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
22#endif
23
24#ifndef CONFIG_SYS_MONITOR_BASE
25#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
26#endif
27
28
29#define CONFIG_MP 1
30
31#define CONFIG_PCIE1 1
32#define CONFIG_PCIE2 1
33#define CONFIG_PCIE3 1
34#define CONFIG_FSL_PCI_INIT 1
35#define CONFIG_PCI_INDIRECT_BRIDGE 1
36#define CONFIG_FSL_PCIE_RESET 1
37#define CONFIG_SYS_PCI_64BIT 1
38
39#define CONFIG_TSEC_ENET
40#define CONFIG_ENV_OVERWRITE
41
42#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
43#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
44#define CONFIG_ICS307_REFCLK_HZ 33333000
45
46
47
48
49#define CONFIG_L2_CACHE
50#define CONFIG_BTB
51
52#define CONFIG_ENABLE_36BIT_PHYS 1
53
54#ifdef CONFIG_PHYS_64BIT
55#define CONFIG_ADDR_MAP 1
56#define CONFIG_SYS_NUM_ADDR_MAP 16
57#endif
58
59#define CONFIG_SYS_MEMTEST_START 0x00000000
60#define CONFIG_SYS_MEMTEST_END 0x7fffffff
61#define CONFIG_PANIC_HANG
62
63
64
65
66#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
67#ifdef CONFIG_PHYS_64BIT
68#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
69#else
70#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
71#endif
72#define CONFIG_SYS_L2_SIZE (512 << 10)
73#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
74
75#define CONFIG_SYS_CCSRBAR 0xffe00000
76#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
77
78#if defined(CONFIG_NAND_SPL)
79#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
80#endif
81
82
83#define CONFIG_VERY_BIG_RAM
84#undef CONFIG_FSL_DDR_INTERACTIVE
85#define CONFIG_SPD_EEPROM
86#define CONFIG_DDR_SPD
87
88#define CONFIG_DDR_ECC
89#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
90#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
91
92#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
93#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
94
95#define CONFIG_DIMM_SLOTS_PER_CTLR 1
96#define CONFIG_CHIP_SELECTS_PER_CTRL 2
97
98
99#define CONFIG_SYS_SPD_BUS_NUM 1
100#define SPD_EEPROM_ADDRESS1 0x51
101#define SPD_EEPROM_ADDRESS2 0x52
102
103
104#define CONFIG_SYS_SDRAM_SIZE 512
105#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
106#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202
107#define CONFIG_SYS_DDR_TIMING_3 0x00020000
108#define CONFIG_SYS_DDR_TIMING_0 0x00260802
109#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
110#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
111#define CONFIG_SYS_DDR_MODE_1 0x00440462
112#define CONFIG_SYS_DDR_MODE_2 0x00000000
113#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
114#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
115#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
116#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
117#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
118#define CONFIG_SYS_DDR_CONTROL 0xc3000008
119#define CONFIG_SYS_DDR_CONTROL2 0x24400000
120
121#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
122#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
123#define CONFIG_SYS_DDR_SBE 0x00010000
124
125
126
127
128#ifndef CONFIG_SPD_EEPROM
129#error ("CONFIG_SPD_EEPROM is required")
130#endif
131
132#undef CONFIG_CLOCKS_IN_MHZ
133
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154
155
156
157#define CONFIG_SYS_FLASH_BASE 0xe0000000
158#ifdef CONFIG_PHYS_64BIT
159#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
160#else
161#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
162#endif
163
164#define CONFIG_FLASH_BR_PRELIM \
165 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
166#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
167
168#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
169#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
170
171#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
172#define CONFIG_SYS_FLASH_QUIET_TEST
173#define CONFIG_FLASH_SHOW_PROGRESS 45
174
175#define CONFIG_SYS_MAX_FLASH_BANKS 2
176#define CONFIG_SYS_MAX_FLASH_SECT 1024
177#undef CONFIG_SYS_FLASH_CHECKSUM
178#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
179#define CONFIG_SYS_FLASH_WRITE_TOUT 500
180
181#undef CONFIG_SYS_RAMBOOT
182
183#define CONFIG_FLASH_CFI_DRIVER
184#define CONFIG_SYS_FLASH_CFI
185#define CONFIG_SYS_FLASH_EMPTY_INFO
186#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
187
188#define CONFIG_BOARD_EARLY_INIT_R
189
190#define CONFIG_HWCONFIG
191#define CONFIG_FSL_PIXIS 1
192#define PIXIS_BASE 0xffdf0000
193#ifdef CONFIG_PHYS_64BIT
194#define PIXIS_BASE_PHYS 0xfffdf0000ull
195#else
196#define PIXIS_BASE_PHYS PIXIS_BASE
197#endif
198
199#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
200#define CONFIG_SYS_OR3_PRELIM 0xffffeff7
201
202#define PIXIS_ID 0x0
203#define PIXIS_VER 0x1
204#define PIXIS_PVER 0x2
205#define PIXIS_CSR 0x3
206#define PIXIS_RST 0x4
207#define PIXIS_PWR 0x5
208#define PIXIS_AUX 0x6
209#define PIXIS_SPD 0x7
210#define PIXIS_AUX2 0x8
211#define PIXIS_VCTL 0x10
212#define PIXIS_VSTAT 0x11
213#define PIXIS_VCFGEN0 0x12
214#define PIXIS_VCFGEN1 0x13
215#define PIXIS_VCORE0 0x14
216#define PIXIS_VBOOT 0x16
217#define PIXIS_VBOOT_LBMAP 0xc0
218#define PIXIS_VBOOT_LBMAP_NOR0 0x00
219#define PIXIS_VBOOT_LBMAP_PJET 0x01
220#define PIXIS_VBOOT_LBMAP_NAND 0x02
221#define PIXIS_VBOOT_LBMAP_NOR1 0x03
222#define PIXIS_VSPEED0 0x17
223#define PIXIS_VSPEED1 0x18
224#define PIXIS_VSPEED2 0x19
225#define PIXIS_VSYSCLK0 0x1C
226#define PIXIS_VSYSCLK1 0x1D
227#define PIXIS_VSYSCLK2 0x1E
228#define PIXIS_VDDRCLK0 0x1F
229#define PIXIS_VDDRCLK1 0x20
230#define PIXIS_VDDRCLK2 0x21
231#define PIXIS_VWATCH 0x24
232#define PIXIS_LED 0x25
233
234#define PIXIS_SPD_SYSCLK_MASK 0x7
235
236
237#define PIXIS_VCLKH 0x19
238#define PIXIS_VCLKL 0x1A
239#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
240#define PIXIS_VSPEED2_TSEC1SER 0x8
241#define PIXIS_VSPEED2_TSEC2SER 0x4
242#define PIXIS_VSPEED2_TSEC3SER 0x2
243#define PIXIS_VSPEED2_TSEC4SER 0x1
244#define PIXIS_VCFGEN1_TSEC1SER 0x20
245#define PIXIS_VCFGEN1_TSEC2SER 0x20
246#define PIXIS_VCFGEN1_TSEC3SER 0x20
247#define PIXIS_VCFGEN1_TSEC4SER 0x20
248#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
249 | PIXIS_VSPEED2_TSEC2SER \
250 | PIXIS_VSPEED2_TSEC3SER \
251 | PIXIS_VSPEED2_TSEC4SER)
252#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
253 | PIXIS_VCFGEN1_TSEC2SER \
254 | PIXIS_VCFGEN1_TSEC3SER \
255 | PIXIS_VCFGEN1_TSEC4SER)
256
257#define CONFIG_SYS_INIT_RAM_LOCK 1
258#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
259#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
260
261#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
262#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
263
264#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
265#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
266
267#ifndef CONFIG_NAND_SPL
268#define CONFIG_SYS_NAND_BASE 0xffa00000
269#ifdef CONFIG_PHYS_64BIT
270#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
271#else
272#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
273#endif
274#else
275#define CONFIG_SYS_NAND_BASE 0xfff00000
276#ifdef CONFIG_PHYS_64BIT
277#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
278#else
279#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
280#endif
281#endif
282
283#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
284 CONFIG_SYS_NAND_BASE + 0x40000, \
285 CONFIG_SYS_NAND_BASE + 0x80000,\
286 CONFIG_SYS_NAND_BASE + 0xC0000}
287#define CONFIG_SYS_MAX_NAND_DEVICE 4
288#define CONFIG_CMD_NAND 1
289#define CONFIG_NAND_FSL_ELBC 1
290#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
291#define CONFIG_SYS_NAND_MAX_OOBFREE 5
292#define CONFIG_SYS_NAND_MAX_ECCPOS 56
293
294
295#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
296#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
297#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
298#define CONFIG_SYS_NAND_U_BOOT_START \
299 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
300#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
301#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
302#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
303
304
305#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
306 | (2<<BR_DECC_SHIFT) \
307 | BR_PS_8 \
308 | BR_MS_FCM \
309 | BR_V)
310#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 \
311 | OR_FCM_PGS \
312 | OR_FCM_CSCT \
313 | OR_FCM_CST \
314 | OR_FCM_CHT \
315 | OR_FCM_SCY_1 \
316 | OR_FCM_TRLX \
317 | OR_FCM_EHTR)
318
319#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
320#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
321#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM
322#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM
323#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
324 | (2<<BR_DECC_SHIFT) \
325 | BR_PS_8 \
326 | BR_MS_FCM \
327 | BR_V)
328#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM
329#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
330 | (2<<BR_DECC_SHIFT) \
331 | BR_PS_8 \
332 | BR_MS_FCM \
333 | BR_V)
334#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM
335
336#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
337 | (2<<BR_DECC_SHIFT) \
338 | BR_PS_8 \
339 | BR_MS_FCM \
340 | BR_V)
341#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM
342
343
344
345
346
347#define CONFIG_CONS_INDEX 1
348#define CONFIG_SYS_NS16550_SERIAL
349#define CONFIG_SYS_NS16550_REG_SIZE 1
350#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
351#ifdef CONFIG_NAND_SPL
352#define CONFIG_NS16550_MIN_FUNCTIONS
353#endif
354
355#define CONFIG_SYS_BAUDRATE_TABLE \
356 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
357
358#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
359#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
360
361
362#define CONFIG_SYS_I2C
363#define CONFIG_SYS_I2C_FSL
364#define CONFIG_SYS_FSL_I2C_SPEED 400000
365#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
366#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
367#define CONFIG_SYS_FSL_I2C2_SPEED 400000
368#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
369#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
370#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
371#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
372
373
374
375
376#define CONFIG_ID_EEPROM
377#ifdef CONFIG_ID_EEPROM
378#define CONFIG_SYS_I2C_EEPROM_NXID
379#endif
380#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
381#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
382#define CONFIG_SYS_EEPROM_BUS_NUM 1
383
384
385
386
387
388
389
390#define CONFIG_SYS_PCIE3_NAME "ULI"
391#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
392#ifdef CONFIG_PHYS_64BIT
393#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
394#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
395#else
396#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
397#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
398#endif
399#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
400#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
401#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
402#ifdef CONFIG_PHYS_64BIT
403#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
404#else
405#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
406#endif
407#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
408
409
410#define CONFIG_SYS_PCIE2_NAME "Slot 1"
411#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
412#ifdef CONFIG_PHYS_64BIT
413#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
414#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
415#else
416#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
417#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
418#endif
419#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
420#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
421#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
422#ifdef CONFIG_PHYS_64BIT
423#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
424#else
425#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
426#endif
427#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
428
429
430#define CONFIG_SYS_PCIE1_NAME "Slot 2"
431#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
432#ifdef CONFIG_PHYS_64BIT
433#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
434#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
435#else
436#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
437#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
438#endif
439#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
440#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
441#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
442#ifdef CONFIG_PHYS_64BIT
443#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
444#else
445#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
446#endif
447#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
448
449#if defined(CONFIG_PCI)
450
451
452#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
453
454
455
456#if defined(CONFIG_VIDEO)
457#define CONFIG_BIOSEMU
458#define CONFIG_ATI_RADEON_FB
459#define CONFIG_VIDEO_LOGO
460#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
461#endif
462
463#undef CONFIG_EEPRO100
464#undef CONFIG_TULIP
465
466#ifndef CONFIG_PCI_PNP
467 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
468 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
469 #define PCI_IDSEL_NUMBER 0x11
470#endif
471
472#define CONFIG_PCI_SCAN_SHOW
473#define CONFIG_SCSI_AHCI
474
475#ifdef CONFIG_SCSI_AHCI
476#define CONFIG_LIBATA
477#define CONFIG_SATA_ULI5288
478#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
479#define CONFIG_SYS_SCSI_MAX_LUN 1
480#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
481#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
482#endif
483
484#endif
485
486#if defined(CONFIG_TSEC_ENET)
487
488#define CONFIG_MII 1
489#define CONFIG_MII_DEFAULT_TSEC 1
490#define CONFIG_TSEC1 1
491#define CONFIG_TSEC1_NAME "eTSEC1"
492#define CONFIG_TSEC2 1
493#define CONFIG_TSEC2_NAME "eTSEC2"
494#define CONFIG_TSEC3 1
495#define CONFIG_TSEC3_NAME "eTSEC3"
496#define CONFIG_TSEC4 1
497#define CONFIG_TSEC4_NAME "eTSEC4"
498
499#define CONFIG_PIXIS_SGMII_CMD
500#define CONFIG_FSL_SGMII_RISER 1
501#define SGMII_RISER_PHY_OFFSET 0x1c
502
503#ifdef CONFIG_FSL_SGMII_RISER
504#define CONFIG_SYS_TBIPA_VALUE 0x10
505#endif
506
507#define TSEC1_PHY_ADDR 0
508#define TSEC2_PHY_ADDR 1
509#define TSEC3_PHY_ADDR 2
510#define TSEC4_PHY_ADDR 3
511
512#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
513#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
514#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
515#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
516
517#define TSEC1_PHYIDX 0
518#define TSEC2_PHYIDX 0
519#define TSEC3_PHYIDX 0
520#define TSEC4_PHYIDX 0
521
522#define CONFIG_ETHPRIME "eTSEC1"
523
524#define CONFIG_PHY_GIGE 1
525#endif
526
527
528
529
530
531#if defined(CONFIG_SYS_RAMBOOT)
532
533#else
534 #define CONFIG_ENV_IS_IN_FLASH 1
535 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
536 #define CONFIG_ENV_ADDR 0xfff80000
537 #else
538 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
539 #endif
540 #define CONFIG_ENV_SIZE 0x2000
541 #define CONFIG_ENV_SECT_SIZE 0x20000
542#endif
543
544#define CONFIG_LOADS_ECHO 1
545#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
546
547
548
549
550#define CONFIG_CMD_ERRATA
551#define CONFIG_CMD_IRQ
552#define CONFIG_CMD_REGINFO
553
554#if defined(CONFIG_PCI)
555#define CONFIG_CMD_PCI
556#define CONFIG_SCSI
557#endif
558
559
560
561
562#define CONFIG_USB_EHCI
563
564#ifdef CONFIG_USB_EHCI
565#define CONFIG_USB_EHCI_PCI
566#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
567#define CONFIG_PCI_EHCI_DEVICE 0
568#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
569#endif
570
571#undef CONFIG_WATCHDOG
572
573
574
575
576#define CONFIG_SYS_LONGHELP
577#define CONFIG_CMDLINE_EDITING
578#define CONFIG_AUTO_COMPLETE
579#define CONFIG_SYS_LOAD_ADDR 0x2000000
580#if defined(CONFIG_CMD_KGDB)
581#define CONFIG_SYS_CBSIZE 1024
582#else
583#define CONFIG_SYS_CBSIZE 256
584#endif
585#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
586#define CONFIG_SYS_MAXARGS 16
587#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
588
589
590
591
592
593
594#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
595#define CONFIG_SYS_BOOTM_LEN (64 << 20)
596
597#if defined(CONFIG_CMD_KGDB)
598#define CONFIG_KGDB_BAUDRATE 230400
599#endif
600
601
602
603
604#if defined(CONFIG_TSEC_ENET)
605#define CONFIG_HAS_ETH0
606#define CONFIG_HAS_ETH1
607#define CONFIG_HAS_ETH2
608#define CONFIG_HAS_ETH3
609#endif
610
611#define CONFIG_IPADDR 192.168.1.254
612
613#define CONFIG_HOSTNAME unknown
614#define CONFIG_ROOTPATH "/opt/nfsroot"
615#define CONFIG_BOOTFILE "uImage"
616#define CONFIG_UBOOTPATH u-boot.bin
617
618#define CONFIG_SERVERIP 192.168.1.1
619#define CONFIG_GATEWAYIP 192.168.1.1
620#define CONFIG_NETMASK 255.255.255.0
621
622
623#define CONFIG_LOADADDR 1000000
624
625#undef CONFIG_BOOTARGS
626
627#define CONFIG_BAUDRATE 115200
628
629#define CONFIG_EXTRA_ENV_SETTINGS \
630"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
631"netdev=eth0\0" \
632"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
633"tftpflash=tftpboot $loadaddr $uboot; " \
634 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
635 " +$filesize; " \
636 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
637 " +$filesize; " \
638 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
639 " $filesize; " \
640 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
641 " +$filesize; " \
642 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
643 " $filesize\0" \
644"consoledev=ttyS0\0" \
645"ramdiskaddr=2000000\0" \
646"ramdiskfile=8572ds/ramdisk.uboot\0" \
647"fdtaddr=1e00000\0" \
648"fdtfile=8572ds/mpc8572ds.dtb\0" \
649"bdev=sda3\0"
650
651#define CONFIG_HDBOOT \
652 "setenv bootargs root=/dev/$bdev rw " \
653 "console=$consoledev,$baudrate $othbootargs;" \
654 "tftp $loadaddr $bootfile;" \
655 "tftp $fdtaddr $fdtfile;" \
656 "bootm $loadaddr - $fdtaddr"
657
658#define CONFIG_NFSBOOTCOMMAND \
659 "setenv bootargs root=/dev/nfs rw " \
660 "nfsroot=$serverip:$rootpath " \
661 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
662 "console=$consoledev,$baudrate $othbootargs;" \
663 "tftp $loadaddr $bootfile;" \
664 "tftp $fdtaddr $fdtfile;" \
665 "bootm $loadaddr - $fdtaddr"
666
667#define CONFIG_RAMBOOTCOMMAND \
668 "setenv bootargs root=/dev/ram rw " \
669 "console=$consoledev,$baudrate $othbootargs;" \
670 "tftp $ramdiskaddr $ramdiskfile;" \
671 "tftp $loadaddr $bootfile;" \
672 "tftp $fdtaddr $fdtfile;" \
673 "bootm $loadaddr $ramdiskaddr $fdtaddr"
674
675#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
676
677#endif
678